1 //===---------------------------- StackMaps.cpp ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "stackmaps"
12 #include "llvm/CodeGen/StackMaps.h"
13 #include "llvm/CodeGen/AsmPrinter.h"
14 #include "llvm/CodeGen/MachineFrameInfo.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/IR/DataLayout.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCObjectFileInfo.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOpcodes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
32 PatchPointOpers::PatchPointOpers(const MachineInstr *MI)
34 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
35 !MI->getOperand(0).isImplicit()),
36 IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg)
39 unsigned CheckStartIdx = 0, e = MI->getNumOperands();
40 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
41 MI->getOperand(CheckStartIdx).isDef() &&
42 !MI->getOperand(CheckStartIdx).isImplicit())
45 assert(getMetaIdx() == CheckStartIdx &&
46 "Unexpected additional definition in Patchpoint intrinsic.");
50 unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
52 StartIdx = getVarIdx();
54 // Find the next scratch register (implicit def and early clobber)
55 unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
56 while (ScratchIdx < e &&
57 !(MI->getOperand(ScratchIdx).isReg() &&
58 MI->getOperand(ScratchIdx).isDef() &&
59 MI->getOperand(ScratchIdx).isImplicit() &&
60 MI->getOperand(ScratchIdx).isEarlyClobber()))
63 assert(ScratchIdx != e && "No scratch register available");
67 MachineInstr::const_mop_iterator
68 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
69 MachineInstr::const_mop_iterator MOE,
70 LocationVec &Locs, LiveOutVec &LiveOuts) const {
72 switch (MOI->getImm()) {
73 default: llvm_unreachable("Unrecognized operand type.");
74 case StackMaps::DirectMemRefOp: {
75 unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits();
76 assert((Size % 8) == 0 && "Need pointer size in bytes.");
78 unsigned Reg = (++MOI)->getReg();
79 int64_t Imm = (++MOI)->getImm();
80 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm));
83 case StackMaps::IndirectMemRefOp: {
84 int64_t Size = (++MOI)->getImm();
85 assert(Size > 0 && "Need a valid size for indirect memory locations.");
86 unsigned Reg = (++MOI)->getReg();
87 int64_t Imm = (++MOI)->getImm();
88 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm));
91 case StackMaps::ConstantOp: {
93 assert(MOI->isImm() && "Expected constant operand.");
94 int64_t Imm = MOI->getImm();
95 Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm));
102 // The physical register number will ultimately be encoded as a DWARF regno.
103 // The stack map also records the size of a spill slot that can hold the
104 // register content. (The runtime can track the actual size of the data type
107 // Skip implicit registers (this includes our scratch registers)
108 if (MOI->isImplicit())
111 assert(TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) &&
112 "Virtreg operands should have been rewritten before now.");
113 const TargetRegisterClass *RC =
114 AP.TM.getRegisterInfo()->getMinimalPhysRegClass(MOI->getReg());
115 assert(!MOI->getSubReg() && "Physical subreg still around.");
117 Location(Location::Register, RC->getSize(), MOI->getReg(), 0));
121 if (MOI->isRegLiveOut())
122 LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
127 /// Go up the super-register chain until we hit a valid dwarf register number.
128 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
129 int RegNo = TRI->getDwarfRegNum(Reg, false);
130 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR)
131 RegNo = TRI->getDwarfRegNum(*SR, false);
133 assert(RegNo >= 0 && "Invalid Dwarf register number.");
134 return (unsigned) RegNo;
137 /// Create a live-out register record for the given register Reg.
138 StackMaps::LiveOutReg
139 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
140 unsigned RegNo = getDwarfRegNum(Reg, TRI);
141 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
142 return LiveOutReg(Reg, RegNo, Size);
145 /// Parse the register live-out mask and return a vector of live-out registers
146 /// that need to be recorded in the stackmap.
147 StackMaps::LiveOutVec
148 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
149 assert(Mask && "No register mask specified");
150 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
153 // Create a LiveOutReg for each bit that is set in the register mask.
154 for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
155 if ((Mask[Reg / 32] >> Reg % 32) & 1)
156 LiveOuts.push_back(createLiveOutReg(Reg, TRI));
158 // We don't need to keep track of a register if its super-register is already
159 // in the list. Merge entries that refer to the same dwarf register and use
160 // the maximum size that needs to be spilled.
161 std::sort(LiveOuts.begin(), LiveOuts.end());
162 for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end();
164 for (LiveOutVec::iterator II = std::next(I); II != E; ++II) {
165 if (I->RegNo != II->RegNo) {
166 // Skip all the now invalid entries.
170 I->Size = std::max(I->Size, II->Size);
171 if (TRI->isSuperRegister(I->Reg, II->Reg))
176 LiveOuts.erase(std::remove_if(LiveOuts.begin(), LiveOuts.end(),
177 LiveOutReg::IsInvalid), LiveOuts.end());
181 void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
182 MachineInstr::const_mop_iterator MOI,
183 MachineInstr::const_mop_iterator MOE,
186 MCContext &OutContext = AP.OutStreamer.getContext();
187 MCSymbol *MILabel = OutContext.CreateTempSymbol();
188 AP.OutStreamer.EmitLabel(MILabel);
190 LocationVec Locations;
194 assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
195 parseOperand(MI.operands_begin(), std::next(MI.operands_begin()),
196 Locations, LiveOuts);
201 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
204 // Move large constants into the constant pool.
205 for (LocationVec::iterator I = Locations.begin(), E = Locations.end();
207 // Constants are encoded as sign-extended integers.
208 // -1 is directly encoded as .long 0xFFFFFFFF with no constant pool.
209 if (I->LocType == Location::Constant &&
210 ((I->Offset + (int64_t(1)<<31)) >> 32) != 0) {
211 I->LocType = Location::ConstantIndex;
212 I->Offset = ConstPool.getConstantIndex(I->Offset);
216 // Create an expression to calculate the offset of the callsite from function
218 const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
219 MCSymbolRefExpr::Create(MILabel, OutContext),
220 MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext),
223 CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, Locations, LiveOuts));
225 // Record the stack size of the current function.
226 const MachineFrameInfo *MFI = AP.MF->getFrameInfo();
227 FnStackSize[AP.CurrentFnSym] =
228 MFI->hasVarSizedObjects() ? UINT64_MAX : MFI->getStackSize();
231 void StackMaps::recordStackMap(const MachineInstr &MI) {
232 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
234 int64_t ID = MI.getOperand(0).getImm();
235 recordStackMapOpers(MI, ID, std::next(MI.operands_begin(), 2),
239 void StackMaps::recordPatchPoint(const MachineInstr &MI) {
240 assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
242 PatchPointOpers opers(&MI);
243 int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
245 MachineInstr::const_mop_iterator MOI =
246 std::next(MI.operands_begin(), opers.getStackMapStartIdx());
247 recordStackMapOpers(MI, ID, MOI, MI.operands_end(),
248 opers.isAnyReg() && opers.hasDef());
252 LocationVec &Locations = CSInfos.back().Locations;
253 if (opers.isAnyReg()) {
254 unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm();
255 for (unsigned i = 0, e = (opers.hasDef() ? NArgs+1 : NArgs); i != e; ++i)
256 assert(Locations[i].LocType == Location::Register &&
257 "anyreg arg must be in reg.");
262 /// serializeToStackMapSection conceptually populates the following fields:
265 /// uint8 : Stack Map Version (currently 1)
266 /// uint8 : Reserved (expected to be 0)
267 /// uint16 : Reserved (expected to be 0)
269 /// uint32 : NumFunctions
270 /// uint32 : NumConstants
271 /// uint32 : NumRecords
272 /// StkSizeRecord[NumFunctions] {
273 /// uint64 : Function Address
274 /// uint64 : Stack Size
276 /// int64 : Constants[NumConstants]
277 /// StkMapRecord[NumRecords] {
278 /// uint64 : PatchPoint ID
279 /// uint32 : Instruction Offset
280 /// uint16 : Reserved (record flags)
281 /// uint16 : NumLocations
282 /// Location[NumLocations] {
283 /// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
284 /// uint8 : Size in Bytes
285 /// uint16 : Dwarf RegNum
289 /// uint16 : NumLiveOuts
290 /// LiveOuts[NumLiveOuts] {
291 /// uint16 : Dwarf RegNum
293 /// uint8 : Size in Bytes
295 /// uint32 : Padding (only if required to align to 8 byte)
298 /// Location Encoding, Type, Value:
299 /// 0x1, Register, Reg (value in register)
300 /// 0x2, Direct, Reg + Offset (frame index)
301 /// 0x3, Indirect, [Reg + Offset] (spilled value)
302 /// 0x4, Constant, Offset (small constant)
303 /// 0x5, ConstIndex, Constants[Offset] (large constant)
305 void StackMaps::serializeToStackMapSection() {
306 // Bail out if there's no stack map data.
310 MCContext &OutContext = AP.OutStreamer.getContext();
311 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
313 // Create the section.
314 const MCSection *StackMapSection =
315 OutContext.getObjectFileInfo()->getStackMapSection();
316 AP.OutStreamer.SwitchSection(StackMapSection);
318 // Emit a dummy symbol to force section inclusion.
319 AP.OutStreamer.EmitLabel(
320 OutContext.GetOrCreateSymbol(Twine("__LLVM_StackMaps")));
323 const char *WSMP = "Stack Maps: ";
326 DEBUG(dbgs() << "********** Stack Map Output **********\n");
329 AP.OutStreamer.EmitIntValue(1, 1); // Version.
330 AP.OutStreamer.EmitIntValue(0, 1); // Reserved.
331 AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
334 DEBUG(dbgs() << WSMP << "#functions = " << FnStackSize.size() << '\n');
335 AP.OutStreamer.EmitIntValue(FnStackSize.size(), 4);
337 DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.getNumConstants()
339 AP.OutStreamer.EmitIntValue(ConstPool.getNumConstants(), 4);
341 DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n');
342 AP.OutStreamer.EmitIntValue(CSInfos.size(), 4);
344 // Function stack size entries.
345 for (FnStackSizeMap::iterator I = FnStackSize.begin(), E = FnStackSize.end();
347 AP.OutStreamer.EmitSymbolValue(I->first, 8);
348 AP.OutStreamer.EmitIntValue(I->second, 8);
351 // Constant pool entries.
352 for (unsigned i = 0; i < ConstPool.getNumConstants(); ++i)
353 AP.OutStreamer.EmitIntValue(ConstPool.getConstant(i), 8);
356 for (CallsiteInfoList::const_iterator CSII = CSInfos.begin(),
357 CSIE = CSInfos.end(); CSII != CSIE; ++CSII) {
358 uint64_t CallsiteID = CSII->ID;
359 const LocationVec &CSLocs = CSII->Locations;
360 const LiveOutVec &LiveOuts = CSII->LiveOuts;
362 DEBUG(dbgs() << WSMP << "callsite " << CallsiteID << "\n");
364 // Verify stack map entry. It's better to communicate a problem to the
365 // runtime than crash in case of in-process compilation. Currently, we do
366 // simple overflow checks, but we may eventually communicate other
367 // compilation errors this way.
368 if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
369 AP.OutStreamer.EmitIntValue(UINT64_MAX, 8); // Invalid ID.
370 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
371 AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
372 AP.OutStreamer.EmitIntValue(0, 2); // 0 locations.
373 AP.OutStreamer.EmitIntValue(0, 2); // padding.
374 AP.OutStreamer.EmitIntValue(0, 2); // 0 live-out registers.
375 AP.OutStreamer.EmitIntValue(0, 4); // padding.
379 AP.OutStreamer.EmitIntValue(CallsiteID, 8);
380 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
382 // Reserved for flags.
383 AP.OutStreamer.EmitIntValue(0, 2);
385 DEBUG(dbgs() << WSMP << " has " << CSLocs.size() << " locations\n");
387 AP.OutStreamer.EmitIntValue(CSLocs.size(), 2);
389 unsigned operIdx = 0;
390 for (LocationVec::const_iterator LocI = CSLocs.begin(), LocE = CSLocs.end();
391 LocI != LocE; ++LocI, ++operIdx) {
392 const Location &Loc = *LocI;
394 int Offset = Loc.Offset;
396 RegNo = getDwarfRegNum(Loc.Reg, TRI);
398 // If this is a register location, put the subregister byte offset in
399 // the location offset.
400 if (Loc.LocType == Location::Register) {
401 assert(!Loc.Offset && "Register location should have zero offset");
402 unsigned LLVMRegNo = TRI->getLLVMRegNum(RegNo, false);
403 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNo, Loc.Reg);
405 Offset = TRI->getSubRegIdxOffset(SubRegIdx);
409 assert(Loc.LocType != Location::Register &&
410 "Missing location register");
414 dbgs() << WSMP << " Loc " << operIdx << ": ";
415 switch (Loc.LocType) {
416 case Location::Unprocessed:
417 dbgs() << "<Unprocessed operand>";
419 case Location::Register:
420 dbgs() << "Register " << TRI->getName(Loc.Reg);
422 case Location::Direct:
423 dbgs() << "Direct " << TRI->getName(Loc.Reg);
425 dbgs() << " + " << Loc.Offset;
427 case Location::Indirect:
428 dbgs() << "Indirect " << TRI->getName(Loc.Reg)
429 << " + " << Loc.Offset;
431 case Location::Constant:
432 dbgs() << "Constant " << Loc.Offset;
434 case Location::ConstantIndex:
435 dbgs() << "Constant Index " << Loc.Offset;
438 dbgs() << " [encoding: .byte " << Loc.LocType
439 << ", .byte " << Loc.Size
440 << ", .short " << RegNo
441 << ", .int " << Offset << "]\n";
444 AP.OutStreamer.EmitIntValue(Loc.LocType, 1);
445 AP.OutStreamer.EmitIntValue(Loc.Size, 1);
446 AP.OutStreamer.EmitIntValue(RegNo, 2);
447 AP.OutStreamer.EmitIntValue(Offset, 4);
450 DEBUG(dbgs() << WSMP << " has " << LiveOuts.size()
451 << " live-out registers\n");
453 // Num live-out registers and padding to align to 4 byte.
454 AP.OutStreamer.EmitIntValue(0, 2);
455 AP.OutStreamer.EmitIntValue(LiveOuts.size(), 2);
458 for (LiveOutVec::const_iterator LI = LiveOuts.begin(), LE = LiveOuts.end();
459 LI != LE; ++LI, ++operIdx) {
460 DEBUG(dbgs() << WSMP << " LO " << operIdx << ": "
461 << TRI->getName(LI->Reg)
462 << " [encoding: .short " << LI->RegNo
463 << ", .byte 0, .byte " << LI->Size << "]\n");
465 AP.OutStreamer.EmitIntValue(LI->RegNo, 2);
466 AP.OutStreamer.EmitIntValue(0, 1);
467 AP.OutStreamer.EmitIntValue(LI->Size, 1);
469 // Emit alignment to 8 byte.
470 AP.OutStreamer.EmitValueToAlignment(8);
473 AP.OutStreamer.AddBlankLine();