1 //===---------------------------- StackMaps.cpp ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "stackmaps"
12 #include "llvm/CodeGen/StackMaps.h"
14 #include "llvm/CodeGen/AsmPrinter.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/IR/DataLayout.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCObjectFileInfo.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetOpcodes.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
32 PatchPointOpers::PatchPointOpers(const MachineInstr *MI):
34 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
35 !MI->getOperand(0).isImplicit()),
36 IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg) {
40 unsigned CheckStartIdx = 0, e = MI->getNumOperands();
41 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
42 MI->getOperand(CheckStartIdx).isDef() &&
43 !MI->getOperand(CheckStartIdx).isImplicit())
46 assert(getMetaIdx() == CheckStartIdx &&
47 "Unexpected additonal definition in Patchpoint intrinsic.");
52 unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
54 StartIdx = getVarIdx();
56 // Find the next scratch register (implicit def and early clobber)
57 unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
58 while (ScratchIdx < e &&
59 !(MI->getOperand(ScratchIdx).isReg() &&
60 MI->getOperand(ScratchIdx).isDef() &&
61 MI->getOperand(ScratchIdx).isImplicit() &&
62 MI->getOperand(ScratchIdx).isEarlyClobber()))
65 assert(ScratchIdx != e && "No scratch register available");
69 std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
70 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
71 MachineInstr::const_mop_iterator MOE) {
72 const MachineOperand &MOP = *MOI;
73 assert(!MOP.isRegMask() && (!MOP.isReg() || !MOP.isImplicit()) &&
74 "Register mask and implicit operands should not be processed.");
78 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
80 switch (MOP.getImm()) {
81 default: llvm_unreachable("Unrecognized operand type.");
82 case StackMaps::DirectMemRefOp: {
83 unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits();
84 assert((Size % 8) == 0 && "Need pointer size in bytes.");
86 unsigned Reg = (++MOI)->getReg();
87 int64_t Imm = (++MOI)->getImm();
88 return std::make_pair(
89 Location(StackMaps::Location::Direct, Size, Reg, Imm), ++MOI);
91 case StackMaps::IndirectMemRefOp: {
92 int64_t Size = (++MOI)->getImm();
93 assert(Size > 0 && "Need a valid size for indirect memory locations.");
94 unsigned Reg = (++MOI)->getReg();
95 int64_t Imm = (++MOI)->getImm();
96 return std::make_pair(
97 Location(StackMaps::Location::Indirect, Size, Reg, Imm), ++MOI);
99 case StackMaps::ConstantOp: {
101 assert(MOI->isImm() && "Expected constant operand.");
102 int64_t Imm = MOI->getImm();
103 return std::make_pair(
104 Location(Location::Constant, sizeof(int64_t), 0, Imm), ++MOI);
109 // Otherwise this is a reg operand. The physical register number will
110 // ultimately be encoded as a DWARF regno. The stack map also records the size
111 // of a spill slot that can hold the register content. (The runtime can
112 // track the actual size of the data type if it needs to.)
113 assert(MOP.isReg() && "Expected register operand here.");
114 assert(TargetRegisterInfo::isPhysicalRegister(MOP.getReg()) &&
115 "Virtreg operands should have been rewritten before now.");
116 const TargetRegisterClass *RC =
117 AP.TM.getRegisterInfo()->getMinimalPhysRegClass(MOP.getReg());
118 assert(!MOP.getSubReg() && "Physical subreg still around.");
119 return std::make_pair(
120 Location(Location::Register, RC->getSize(), MOP.getReg(), 0), ++MOI);
123 void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint32_t ID,
124 MachineInstr::const_mop_iterator MOI,
125 MachineInstr::const_mop_iterator MOE,
128 MCContext &OutContext = AP.OutStreamer.getContext();
129 MCSymbol *MILabel = OutContext.CreateTempSymbol();
130 AP.OutStreamer.EmitLabel(MILabel);
132 LocationVec CallsiteLocs;
135 std::pair<Location, MachineInstr::const_mop_iterator> ParseResult =
136 parseOperand(MI.operands_begin(), llvm::next(MI.operands_begin()));
138 Location &Loc = ParseResult.first;
139 assert(Loc.LocType == Location::Register &&
140 "Stackmap return location must be a register.");
141 CallsiteLocs.push_back(Loc);
146 tie(Loc, MOI) = parseOperand(MOI, MOE);
148 // Move large constants into the constant pool.
149 if (Loc.LocType == Location::Constant && (Loc.Offset & ~0xFFFFFFFFULL)) {
150 Loc.LocType = Location::ConstantIndex;
151 Loc.Offset = ConstPool.getConstantIndex(Loc.Offset);
154 CallsiteLocs.push_back(Loc);
157 const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
158 MCSymbolRefExpr::Create(MILabel, OutContext),
159 MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext),
162 CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, CallsiteLocs));
165 static MachineInstr::const_mop_iterator
166 getStackMapEndMOP(MachineInstr::const_mop_iterator MOI,
167 MachineInstr::const_mop_iterator MOE) {
168 for (; MOI != MOE; ++MOI)
169 if (MOI->isRegMask() || (MOI->isReg() && MOI->isImplicit()))
175 void StackMaps::recordStackMap(const MachineInstr &MI) {
176 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "exected stackmap");
178 int64_t ID = MI.getOperand(0).getImm();
179 assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs");
180 recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2),
181 getStackMapEndMOP(MI.operands_begin(),
185 void StackMaps::recordPatchPoint(const MachineInstr &MI) {
186 assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "exected stackmap");
188 PatchPointOpers opers(&MI);
189 int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
190 assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs");
191 MachineInstr::const_mop_iterator MOI =
192 llvm::next(MI.operands_begin(), opers.getStackMapStartIdx());
193 recordStackMapOpers(MI, ID, MOI, getStackMapEndMOP(MOI, MI.operands_end()),
194 opers.isAnyReg() && opers.hasDef());
198 LocationVec &Locations = CSInfos.back().Locations;
199 if (opers.isAnyReg()) {
200 unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm();
201 for (unsigned i = 0, e = (opers.hasDef() ? NArgs+1 : NArgs); i != e; ++i)
202 assert(Locations[i].LocType == Location::Register &&
203 "anyreg arg must be in reg.");
208 /// serializeToStackMapSection conceptually populates the following fields:
210 /// uint32 : Reserved (header)
211 /// uint32 : NumConstants
212 /// int64 : Constants[NumConstants]
213 /// uint32 : NumRecords
214 /// StkMapRecord[NumRecords] {
215 /// uint32 : PatchPoint ID
216 /// uint32 : Instruction Offset
217 /// uint16 : Reserved (record flags)
218 /// uint16 : NumLocations
219 /// Location[NumLocations] {
220 /// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
221 /// uint8 : Size in Bytes
222 /// uint16 : Dwarf RegNum
227 /// Location Encoding, Type, Value:
228 /// 0x1, Register, Reg (value in register)
229 /// 0x2, Direct, Reg + Offset (frame index)
230 /// 0x3, Indirect, [Reg + Offset] (spilled value)
231 /// 0x4, Constant, Offset (small constant)
232 /// 0x5, ConstIndex, Constants[Offset] (large constant)
234 void StackMaps::serializeToStackMapSection() {
235 // Bail out if there's no stack map data.
239 MCContext &OutContext = AP.OutStreamer.getContext();
240 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
242 // Create the section.
243 const MCSection *StackMapSection =
244 OutContext.getObjectFileInfo()->getStackMapSection();
245 AP.OutStreamer.SwitchSection(StackMapSection);
247 // Emit a dummy symbol to force section inclusion.
248 AP.OutStreamer.EmitLabel(
249 OutContext.GetOrCreateSymbol(Twine("__LLVM_StackMaps")));
252 const char *WSMP = "Stack Maps: ";
254 const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo();
256 DEBUG(dbgs() << "********** Stack Map Output **********\n");
259 AP.OutStreamer.EmitIntValue(0, 4);
262 AP.OutStreamer.EmitIntValue(ConstPool.getNumConstants(), 4);
264 // Constant pool entries.
265 for (unsigned i = 0; i < ConstPool.getNumConstants(); ++i)
266 AP.OutStreamer.EmitIntValue(ConstPool.getConstant(i), 8);
268 DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << "\n");
269 AP.OutStreamer.EmitIntValue(CSInfos.size(), 4);
271 for (CallsiteInfoList::const_iterator CSII = CSInfos.begin(),
272 CSIE = CSInfos.end();
273 CSII != CSIE; ++CSII) {
275 unsigned CallsiteID = CSII->ID;
276 const LocationVec &CSLocs = CSII->Locations;
278 DEBUG(dbgs() << WSMP << "callsite " << CallsiteID << "\n");
280 // Verify stack map entry. It's better to communicate a problem to the
281 // runtime than crash in case of in-process compilation. Currently, we do
282 // simple overflow checks, but we may eventually communicate other
283 // compilation errors this way.
284 if (CSLocs.size() > UINT16_MAX) {
285 AP.OutStreamer.EmitIntValue(UINT32_MAX, 4); // Invalid ID.
286 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
287 AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
288 AP.OutStreamer.EmitIntValue(0, 2); // 0 locations.
292 AP.OutStreamer.EmitIntValue(CallsiteID, 4);
293 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
295 // Reserved for flags.
296 AP.OutStreamer.EmitIntValue(0, 2);
298 DEBUG(dbgs() << WSMP << " has " << CSLocs.size() << " locations\n");
300 AP.OutStreamer.EmitIntValue(CSLocs.size(), 2);
302 unsigned operIdx = 0;
303 for (LocationVec::const_iterator LocI = CSLocs.begin(), LocE = CSLocs.end();
304 LocI != LocE; ++LocI, ++operIdx) {
305 const Location &Loc = *LocI;
307 int Offset = Loc.Offset;
309 RegNo = MCRI.getDwarfRegNum(Loc.Reg, false);
310 for (MCSuperRegIterator SR(Loc.Reg, TRI);
311 SR.isValid() && (int)RegNo < 0; ++SR) {
312 RegNo = TRI->getDwarfRegNum(*SR, false);
314 // If this is a register location, put the subregister byte offset in
315 // the location offset.
316 if (Loc.LocType == Location::Register) {
317 assert(!Loc.Offset && "Register location should have zero offset");
318 unsigned LLVMRegNo = MCRI.getLLVMRegNum(RegNo, false);
319 unsigned SubRegIdx = MCRI.getSubRegIndex(LLVMRegNo, Loc.Reg);
321 Offset = MCRI.getSubRegIdxOffset(SubRegIdx);
325 assert(Loc.LocType != Location::Register &&
326 "Missing location register");
330 dbgs() << WSMP << " Loc " << operIdx << ": ";
331 switch (Loc.LocType) {
332 case Location::Unprocessed:
333 dbgs() << "<Unprocessed operand>";
335 case Location::Register:
336 dbgs() << "Register " << MCRI.getName(Loc.Reg);
338 case Location::Direct:
339 dbgs() << "Direct " << MCRI.getName(Loc.Reg);
341 dbgs() << " + " << Loc.Offset;
343 case Location::Indirect:
344 dbgs() << "Indirect " << MCRI.getName(Loc.Reg)
345 << " + " << Loc.Offset;
347 case Location::Constant:
348 dbgs() << "Constant " << Loc.Offset;
350 case Location::ConstantIndex:
351 dbgs() << "Constant Index " << Loc.Offset;
354 dbgs() << " [encoding: .byte " << Loc.LocType
355 << ", .byte " << Loc.Size
356 << ", .short " << RegNo
357 << ", .int " << Offset << "]\n";
360 AP.OutStreamer.EmitIntValue(Loc.LocType, 1);
361 AP.OutStreamer.EmitIntValue(Loc.Size, 1);
362 AP.OutStreamer.EmitIntValue(RegNo, 2);
363 AP.OutStreamer.EmitIntValue(Offset, 4);
367 AP.OutStreamer.AddBlankLine();