1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineMemOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
21 #include "llvm/CodeGen/StackMaps.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
34 static cl::opt<bool> DisableHazardRecognizer(
35 "disable-sched-hazard", cl::Hidden, cl::init(false),
36 cl::desc("Disable hazard detection during preRA scheduling"));
38 TargetInstrInfo::~TargetInstrInfo() {
41 const TargetRegisterClass*
42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
43 const TargetRegisterInfo *TRI,
44 const MachineFunction &MF) const {
45 if (OpNum >= MCID.getNumOperands())
48 short RegClass = MCID.OpInfo[OpNum].RegClass;
49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
50 return TRI->getPointerRegClass(MF, RegClass);
52 // Instructions like INSERT_SUBREG do not have fixed register classes.
56 // Otherwise just look it up normally.
57 return TRI->getRegClass(RegClass);
60 /// insertNoop - Insert a noop into the instruction stream at the specified
62 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI) const {
64 llvm_unreachable("Target didn't implement insertNoop!");
67 /// Measure the specified inline asm to determine an approximation of its
69 /// Comments (which run till the next SeparatorString or newline) do not
70 /// count as an instruction.
71 /// Any other non-whitespace text is considered an instruction, with
72 /// multiple instructions separated by SeparatorString or newlines.
73 /// Variable-length instructions are not handled here; this function
74 /// may be overloaded in the target code to do that.
75 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
76 const MCAsmInfo &MAI) const {
79 // Count the number of instructions in the asm.
80 bool atInsnStart = true;
83 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
84 strlen(MAI.getSeparatorString())) == 0)
86 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
87 Length += MAI.getMaxInstLength();
90 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
91 strlen(MAI.getCommentString())) == 0)
98 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
99 /// after it, replacing it with an unconditional branch to NewDest.
101 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
102 MachineBasicBlock *NewDest) const {
103 MachineBasicBlock *MBB = Tail->getParent();
105 // Remove all the old successors of MBB from the CFG.
106 while (!MBB->succ_empty())
107 MBB->removeSuccessor(MBB->succ_begin());
109 // Remove all the dead instructions from the end of MBB.
110 MBB->erase(Tail, MBB->end());
112 // If MBB isn't immediately before MBB, insert a branch to it.
113 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
114 InsertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(),
115 Tail->getDebugLoc());
116 MBB->addSuccessor(NewDest);
119 // commuteInstruction - The default implementation of this method just exchanges
120 // the two operands returned by findCommutedOpIndices.
121 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
123 const MCInstrDesc &MCID = MI->getDesc();
124 bool HasDef = MCID.getNumDefs();
125 if (HasDef && !MI->getOperand(0).isReg())
126 // No idea how to commute this instruction. Target should implement its own.
129 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
130 assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
135 "This only knows how to commute register operands so far");
136 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
137 unsigned Reg1 = MI->getOperand(Idx1).getReg();
138 unsigned Reg2 = MI->getOperand(Idx2).getReg();
139 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
140 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
141 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
142 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
143 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
144 // If destination is tied to either of the commuted source register, then
145 // it must be updated.
146 if (HasDef && Reg0 == Reg1 &&
147 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
151 } else if (HasDef && Reg0 == Reg2 &&
152 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
159 // Create a new instruction.
160 MachineFunction &MF = *MI->getParent()->getParent();
161 MI = MF.CloneMachineInstr(MI);
165 MI->getOperand(0).setReg(Reg0);
166 MI->getOperand(0).setSubReg(SubReg0);
168 MI->getOperand(Idx2).setReg(Reg1);
169 MI->getOperand(Idx1).setReg(Reg2);
170 MI->getOperand(Idx2).setSubReg(SubReg1);
171 MI->getOperand(Idx1).setSubReg(SubReg2);
172 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
173 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
177 /// findCommutedOpIndices - If specified MI is commutable, return the two
178 /// operand indices that would swap value. Return true if the instruction
179 /// is not in a form which this routine understands.
180 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
182 unsigned &SrcOpIdx2) const {
183 assert(!MI->isBundle() &&
184 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
186 const MCInstrDesc &MCID = MI->getDesc();
187 if (!MCID.isCommutable())
189 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
190 // is not true, then the target must implement this.
191 SrcOpIdx1 = MCID.getNumDefs();
192 SrcOpIdx2 = SrcOpIdx1 + 1;
193 if (!MI->getOperand(SrcOpIdx1).isReg() ||
194 !MI->getOperand(SrcOpIdx2).isReg())
202 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
203 if (!MI->isTerminator()) return false;
205 // Conditional branch is a special case.
206 if (MI->isBranch() && !MI->isBarrier())
208 if (!MI->isPredicable())
210 return !isPredicated(MI);
214 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
215 const SmallVectorImpl<MachineOperand> &Pred) const {
216 bool MadeChange = false;
218 assert(!MI->isBundle() &&
219 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
221 const MCInstrDesc &MCID = MI->getDesc();
222 if (!MI->isPredicable())
225 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
226 if (MCID.OpInfo[i].isPredicate()) {
227 MachineOperand &MO = MI->getOperand(i);
229 MO.setReg(Pred[j].getReg());
231 } else if (MO.isImm()) {
232 MO.setImm(Pred[j].getImm());
234 } else if (MO.isMBB()) {
235 MO.setMBB(Pred[j].getMBB());
244 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
245 const MachineMemOperand *&MMO,
246 int &FrameIndex) const {
247 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
248 oe = MI->memoperands_end();
251 if ((*o)->isLoad()) {
252 if (const FixedStackPseudoSourceValue *Value =
253 dyn_cast_or_null<FixedStackPseudoSourceValue>(
254 (*o)->getPseudoValue())) {
255 FrameIndex = Value->getFrameIndex();
264 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
265 const MachineMemOperand *&MMO,
266 int &FrameIndex) const {
267 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
268 oe = MI->memoperands_end();
271 if ((*o)->isStore()) {
272 if (const FixedStackPseudoSourceValue *Value =
273 dyn_cast_or_null<FixedStackPseudoSourceValue>(
274 (*o)->getPseudoValue())) {
275 FrameIndex = Value->getFrameIndex();
284 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
285 unsigned SubIdx, unsigned &Size,
287 const TargetMachine *TM) const {
289 Size = RC->getSize();
294 TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxSize(SubIdx);
295 // Convert bit size to byte size to be consistent with
296 // MCRegisterClass::getSize().
301 TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxOffset(SubIdx);
302 if (BitOffset < 0 || BitOffset % 8)
306 Offset = (unsigned)BitOffset / 8;
308 assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
310 if (!TM->getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
311 Offset = RC->getSize() - (Offset + Size);
316 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
317 MachineBasicBlock::iterator I,
320 const MachineInstr *Orig,
321 const TargetRegisterInfo &TRI) const {
322 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
323 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
328 TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
329 const MachineInstr *MI1,
330 const MachineRegisterInfo *MRI) const {
331 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
334 MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
335 MachineFunction &MF) const {
336 assert(!Orig->isNotDuplicable() &&
337 "Instruction cannot be duplicated");
338 return MF.CloneMachineInstr(Orig);
341 // If the COPY instruction in MI can be folded to a stack operation, return
342 // the register class to use.
343 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
345 assert(MI->isCopy() && "MI must be a COPY instruction");
346 if (MI->getNumOperands() != 2)
348 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
350 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
351 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
353 if (FoldOp.getSubReg() || LiveOp.getSubReg())
356 unsigned FoldReg = FoldOp.getReg();
357 unsigned LiveReg = LiveOp.getReg();
359 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
360 "Cannot fold physregs");
362 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
363 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
365 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
366 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
368 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
371 // FIXME: Allow folding when register classes are memory compatible.
375 bool TargetInstrInfo::
376 canFoldMemoryOperand(const MachineInstr *MI,
377 const SmallVectorImpl<unsigned> &Ops) const {
378 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
381 static MachineInstr* foldPatchpoint(MachineFunction &MF,
383 const SmallVectorImpl<unsigned> &Ops,
385 const TargetInstrInfo &TII) {
386 unsigned StartIdx = 0;
387 switch (MI->getOpcode()) {
388 case TargetOpcode::STACKMAP:
389 StartIdx = 2; // Skip ID, nShadowBytes.
391 case TargetOpcode::PATCHPOINT: {
392 // For PatchPoint, the call args are not foldable.
393 PatchPointOpers opers(MI);
394 StartIdx = opers.getVarIdx();
398 llvm_unreachable("unexpected stackmap opcode");
401 // Return false if any operands requested for folding are not foldable (not
402 // part of the stackmap's live values).
403 for (SmallVectorImpl<unsigned>::const_iterator I = Ops.begin(), E = Ops.end();
409 MachineInstr *NewMI =
410 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
411 MachineInstrBuilder MIB(MF, NewMI);
413 // No need to fold return, the meta data, and function arguments
414 for (unsigned i = 0; i < StartIdx; ++i)
415 MIB.addOperand(MI->getOperand(i));
417 for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
418 MachineOperand &MO = MI->getOperand(i);
419 if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
421 unsigned SpillOffset;
422 // Compute the spill slot size and offset.
423 const TargetRegisterClass *RC =
424 MF.getRegInfo().getRegClass(MO.getReg());
425 bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize,
426 SpillOffset, &MF.getTarget());
428 report_fatal_error("cannot spill patchpoint subregister operand");
429 MIB.addImm(StackMaps::IndirectMemRefOp);
430 MIB.addImm(SpillSize);
431 MIB.addFrameIndex(FrameIndex);
432 MIB.addImm(SpillOffset);
440 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
441 /// slot into the specified machine instruction for the specified operand(s).
442 /// If this is possible, a new instruction is returned with the specified
443 /// operand folded, otherwise NULL is returned. The client is responsible for
444 /// removing the old instruction and adding the new one in the instruction
447 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
448 const SmallVectorImpl<unsigned> &Ops,
451 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
452 if (MI->getOperand(Ops[i]).isDef())
453 Flags |= MachineMemOperand::MOStore;
455 Flags |= MachineMemOperand::MOLoad;
457 MachineBasicBlock *MBB = MI->getParent();
458 assert(MBB && "foldMemoryOperand needs an inserted instruction");
459 MachineFunction &MF = *MBB->getParent();
461 MachineInstr *NewMI = nullptr;
463 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
464 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
465 // Fold stackmap/patchpoint.
466 NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
468 // Ask the target to do the actual folding.
469 NewMI =foldMemoryOperandImpl(MF, MI, Ops, FI);
473 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
474 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
475 assert((!(Flags & MachineMemOperand::MOStore) ||
476 NewMI->mayStore()) &&
477 "Folded a def to a non-store!");
478 assert((!(Flags & MachineMemOperand::MOLoad) ||
480 "Folded a use to a non-load!");
481 const MachineFrameInfo &MFI = *MF.getFrameInfo();
482 assert(MFI.getObjectOffset(FI) != -1);
483 MachineMemOperand *MMO =
484 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
485 Flags, MFI.getObjectSize(FI),
486 MFI.getObjectAlignment(FI));
487 NewMI->addMemOperand(MF, MMO);
489 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
490 return MBB->insert(MI, NewMI);
493 // Straight COPY may fold as load/store.
494 if (!MI->isCopy() || Ops.size() != 1)
497 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
501 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
502 MachineBasicBlock::iterator Pos = MI;
503 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
505 if (Flags == MachineMemOperand::MOStore)
506 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
508 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
512 /// foldMemoryOperand - Same as the previous version except it allows folding
513 /// of any load and store from / to any address, not just from a specific
516 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
517 const SmallVectorImpl<unsigned> &Ops,
518 MachineInstr* LoadMI) const {
519 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
521 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
522 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
524 MachineBasicBlock &MBB = *MI->getParent();
525 MachineFunction &MF = *MBB.getParent();
527 // Ask the target to do the actual folding.
528 MachineInstr *NewMI = nullptr;
531 if ((MI->getOpcode() == TargetOpcode::STACKMAP ||
532 MI->getOpcode() == TargetOpcode::PATCHPOINT) &&
533 isLoadFromStackSlot(LoadMI, FrameIndex)) {
534 // Fold stackmap/patchpoint.
535 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
537 // Ask the target to do the actual folding.
538 NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
541 if (!NewMI) return nullptr;
543 NewMI = MBB.insert(MI, NewMI);
545 // Copy the memoperands from the load to the folded instruction.
546 if (MI->memoperands_empty()) {
547 NewMI->setMemRefs(LoadMI->memoperands_begin(),
548 LoadMI->memoperands_end());
551 // Handle the rare case of folding multiple loads.
552 NewMI->setMemRefs(MI->memoperands_begin(),
553 MI->memoperands_end());
554 for (MachineInstr::mmo_iterator I = LoadMI->memoperands_begin(),
555 E = LoadMI->memoperands_end(); I != E; ++I) {
556 NewMI->addMemOperand(MF, *I);
562 bool TargetInstrInfo::
563 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
564 AliasAnalysis *AA) const {
565 const MachineFunction &MF = *MI->getParent()->getParent();
566 const MachineRegisterInfo &MRI = MF.getRegInfo();
568 // Remat clients assume operand 0 is the defined register.
569 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
571 unsigned DefReg = MI->getOperand(0).getReg();
573 // A sub-register definition can only be rematerialized if the instruction
574 // doesn't read the other parts of the register. Otherwise it is really a
575 // read-modify-write operation on the full virtual register which cannot be
577 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
578 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
581 // A load from a fixed stack slot can be rematerialized. This may be
582 // redundant with subsequent checks, but it's target-independent,
583 // simple, and a common case.
585 if (isLoadFromStackSlot(MI, FrameIdx) &&
586 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
589 // Avoid instructions obviously unsafe for remat.
590 if (MI->isNotDuplicable() || MI->mayStore() ||
591 MI->hasUnmodeledSideEffects())
594 // Don't remat inline asm. We have no idea how expensive it is
595 // even if it's side effect free.
596 if (MI->isInlineAsm())
599 // Avoid instructions which load from potentially varying memory.
600 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
603 // If any of the registers accessed are non-constant, conservatively assume
604 // the instruction is not rematerializable.
605 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
606 const MachineOperand &MO = MI->getOperand(i);
607 if (!MO.isReg()) continue;
608 unsigned Reg = MO.getReg();
612 // Check for a well-behaved physical register.
613 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
615 // If the physreg has no defs anywhere, it's just an ambient register
616 // and we can freely move its uses. Alternatively, if it's allocatable,
617 // it could get allocated to something with a def during allocation.
618 if (!MRI.isConstantPhysReg(Reg, MF))
621 // A physreg def. We can't remat it.
627 // Only allow one virtual-register def. There may be multiple defs of the
628 // same virtual register, though.
629 if (MO.isDef() && Reg != DefReg)
632 // Don't allow any virtual-register uses. Rematting an instruction with
633 // virtual register uses would length the live ranges of the uses, which
634 // is not necessarily a good idea, certainly not "trivial".
639 // Everything checked out.
643 /// isSchedulingBoundary - Test if the given instruction should be
644 /// considered a scheduling boundary. This primarily includes labels
646 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
647 const MachineBasicBlock *MBB,
648 const MachineFunction &MF) const {
649 // Terminators and labels can't be scheduled around.
650 if (MI->isTerminator() || MI->isPosition())
653 // Don't attempt to schedule around any instruction that defines
654 // a stack-oriented pointer, as it's unlikely to be profitable. This
655 // saves compile time, because it doesn't require every single
656 // stack slot reference to depend on the instruction that does the
658 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
659 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
660 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
666 // Provide a global flag for disabling the PreRA hazard recognizer that targets
667 // may choose to honor.
668 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
669 return !DisableHazardRecognizer;
672 // Default implementation of CreateTargetRAHazardRecognizer.
673 ScheduleHazardRecognizer *TargetInstrInfo::
674 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
675 const ScheduleDAG *DAG) const {
676 // Dummy hazard recognizer allows all instructions to issue.
677 return new ScheduleHazardRecognizer();
680 // Default implementation of CreateTargetMIHazardRecognizer.
681 ScheduleHazardRecognizer *TargetInstrInfo::
682 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
683 const ScheduleDAG *DAG) const {
684 return (ScheduleHazardRecognizer *)
685 new ScoreboardHazardRecognizer(II, DAG, "misched");
688 // Default implementation of CreateTargetPostRAHazardRecognizer.
689 ScheduleHazardRecognizer *TargetInstrInfo::
690 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
691 const ScheduleDAG *DAG) const {
692 return (ScheduleHazardRecognizer *)
693 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
696 //===----------------------------------------------------------------------===//
697 // SelectionDAG latency interface.
698 //===----------------------------------------------------------------------===//
701 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
702 SDNode *DefNode, unsigned DefIdx,
703 SDNode *UseNode, unsigned UseIdx) const {
704 if (!ItinData || ItinData->isEmpty())
707 if (!DefNode->isMachineOpcode())
710 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
711 if (!UseNode->isMachineOpcode())
712 return ItinData->getOperandCycle(DefClass, DefIdx);
713 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
714 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
717 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
719 if (!ItinData || ItinData->isEmpty())
722 if (!N->isMachineOpcode())
725 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
728 //===----------------------------------------------------------------------===//
729 // MachineInstr latency interface.
730 //===----------------------------------------------------------------------===//
733 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
734 const MachineInstr *MI) const {
735 if (!ItinData || ItinData->isEmpty())
738 unsigned Class = MI->getDesc().getSchedClass();
739 int UOps = ItinData->Itineraries[Class].NumMicroOps;
743 // The # of u-ops is dynamically determined. The specific target should
744 // override this function to return the right number.
748 /// Return the default expected latency for a def based on it's opcode.
749 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
750 const MachineInstr *DefMI) const {
751 if (DefMI->isTransient())
753 if (DefMI->mayLoad())
754 return SchedModel->LoadLatency;
755 if (isHighLatencyDef(DefMI->getOpcode()))
756 return SchedModel->HighLatency;
760 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
764 unsigned TargetInstrInfo::
765 getInstrLatency(const InstrItineraryData *ItinData,
766 const MachineInstr *MI,
767 unsigned *PredCost) const {
768 // Default to one cycle for no itinerary. However, an "empty" itinerary may
769 // still have a MinLatency property, which getStageLatency checks.
771 return MI->mayLoad() ? 2 : 1;
773 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
776 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
777 const MachineInstr *DefMI,
778 unsigned DefIdx) const {
779 if (!ItinData || ItinData->isEmpty())
782 unsigned DefClass = DefMI->getDesc().getSchedClass();
783 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
784 return (DefCycle != -1 && DefCycle <= 1);
787 /// Both DefMI and UseMI must be valid. By default, call directly to the
788 /// itinerary. This may be overriden by the target.
789 int TargetInstrInfo::
790 getOperandLatency(const InstrItineraryData *ItinData,
791 const MachineInstr *DefMI, unsigned DefIdx,
792 const MachineInstr *UseMI, unsigned UseIdx) const {
793 unsigned DefClass = DefMI->getDesc().getSchedClass();
794 unsigned UseClass = UseMI->getDesc().getSchedClass();
795 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
798 /// If we can determine the operand latency from the def only, without itinerary
799 /// lookup, do so. Otherwise return -1.
800 int TargetInstrInfo::computeDefOperandLatency(
801 const InstrItineraryData *ItinData,
802 const MachineInstr *DefMI) const {
804 // Let the target hook getInstrLatency handle missing itineraries.
806 return getInstrLatency(ItinData, DefMI);
808 if(ItinData->isEmpty())
809 return defaultDefLatency(ItinData->SchedModel, DefMI);
811 // ...operand lookup required
815 /// computeOperandLatency - Compute and return the latency of the given data
816 /// dependent def and use when the operand indices are already known. UseMI may
817 /// be NULL for an unknown use.
819 /// FindMin may be set to get the minimum vs. expected latency. Minimum
820 /// latency is used for scheduling groups, while expected latency is for
821 /// instruction cost and critical path.
823 /// Depending on the subtarget's itinerary properties, this may or may not need
824 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
825 /// UseIdx to compute min latency.
826 unsigned TargetInstrInfo::
827 computeOperandLatency(const InstrItineraryData *ItinData,
828 const MachineInstr *DefMI, unsigned DefIdx,
829 const MachineInstr *UseMI, unsigned UseIdx) const {
831 int DefLatency = computeDefOperandLatency(ItinData, DefMI);
835 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
839 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
841 unsigned DefClass = DefMI->getDesc().getSchedClass();
842 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
844 if (OperLatency >= 0)
847 // No operand latency was found.
848 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
850 // Expected latency is the max of the stage latency and itinerary props.
851 InstrLatency = std::max(InstrLatency,
852 defaultDefLatency(ItinData->SchedModel, DefMI));
856 bool TargetInstrInfo::getRegSequenceInputs(
857 const MachineInstr &MI, unsigned DefIdx,
858 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
859 assert((MI.isRegSequence() ||
860 MI.isRegSequenceLike()) && "Instruction do not have the proper type");
862 if (!MI.isRegSequence())
863 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
865 // We are looking at:
866 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
867 assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
868 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
870 const MachineOperand &MOReg = MI.getOperand(OpIdx);
871 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
872 assert(MOSubIdx.isImm() &&
873 "One of the subindex of the reg_sequence is not an immediate");
874 // Record Reg:SubReg, SubIdx.
875 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
876 (unsigned)MOSubIdx.getImm()));
881 bool TargetInstrInfo::getExtractSubregInputs(
882 const MachineInstr &MI, unsigned DefIdx,
883 RegSubRegPairAndIdx &InputReg) const {
884 assert((MI.isExtractSubreg() ||
885 MI.isExtractSubregLike()) && "Instruction do not have the proper type");
887 if (!MI.isExtractSubreg())
888 return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
890 // We are looking at:
891 // Def = EXTRACT_SUBREG v0.sub1, sub0.
892 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
893 const MachineOperand &MOReg = MI.getOperand(1);
894 const MachineOperand &MOSubIdx = MI.getOperand(2);
895 assert(MOSubIdx.isImm() &&
896 "The subindex of the extract_subreg is not an immediate");
898 InputReg.Reg = MOReg.getReg();
899 InputReg.SubReg = MOReg.getSubReg();
900 InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
904 bool TargetInstrInfo::getInsertSubregInputs(
905 const MachineInstr &MI, unsigned DefIdx,
906 RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
907 assert((MI.isInsertSubreg() ||
908 MI.isInsertSubregLike()) && "Instruction do not have the proper type");
910 if (!MI.isInsertSubreg())
911 return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
913 // We are looking at:
914 // Def = INSERT_SEQUENCE v0, v1, sub0.
915 assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
916 const MachineOperand &MOBaseReg = MI.getOperand(1);
917 const MachineOperand &MOInsertedReg = MI.getOperand(2);
918 const MachineOperand &MOSubIdx = MI.getOperand(3);
919 assert(MOSubIdx.isImm() &&
920 "One of the subindex of the reg_sequence is not an immediate");
921 BaseReg.Reg = MOBaseReg.getReg();
922 BaseReg.SubReg = MOBaseReg.getSubReg();
924 InsertedReg.Reg = MOInsertedReg.getReg();
925 InsertedReg.SubReg = MOInsertedReg.getSubReg();
926 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();