1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineMemOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
21 #include "llvm/CodeGen/StackMaps.h"
22 #include "llvm/CodeGen/TargetSchedule.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 static cl::opt<bool> DisableHazardRecognizer(
37 "disable-sched-hazard", cl::Hidden, cl::init(false),
38 cl::desc("Disable hazard detection during preRA scheduling"));
40 TargetInstrInfo::~TargetInstrInfo() {
43 const TargetRegisterClass*
44 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
45 const TargetRegisterInfo *TRI,
46 const MachineFunction &MF) const {
47 if (OpNum >= MCID.getNumOperands())
50 short RegClass = MCID.OpInfo[OpNum].RegClass;
51 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
52 return TRI->getPointerRegClass(MF, RegClass);
54 // Instructions like INSERT_SUBREG do not have fixed register classes.
58 // Otherwise just look it up normally.
59 return TRI->getRegClass(RegClass);
62 /// insertNoop - Insert a noop into the instruction stream at the specified
64 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI) const {
66 llvm_unreachable("Target didn't implement insertNoop!");
69 /// Measure the specified inline asm to determine an approximation of its
71 /// Comments (which run till the next SeparatorString or newline) do not
72 /// count as an instruction.
73 /// Any other non-whitespace text is considered an instruction, with
74 /// multiple instructions separated by SeparatorString or newlines.
75 /// Variable-length instructions are not handled here; this function
76 /// may be overloaded in the target code to do that.
77 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
78 const MCAsmInfo &MAI) const {
81 // Count the number of instructions in the asm.
82 bool atInsnStart = true;
85 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
86 strlen(MAI.getSeparatorString())) == 0)
88 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
89 Length += MAI.getMaxInstLength();
92 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
93 strlen(MAI.getCommentString())) == 0)
100 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
101 /// after it, replacing it with an unconditional branch to NewDest.
103 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
104 MachineBasicBlock *NewDest) const {
105 MachineBasicBlock *MBB = Tail->getParent();
107 // Remove all the old successors of MBB from the CFG.
108 while (!MBB->succ_empty())
109 MBB->removeSuccessor(MBB->succ_begin());
111 // Remove all the dead instructions from the end of MBB.
112 MBB->erase(Tail, MBB->end());
114 // If MBB isn't immediately before MBB, insert a branch to it.
115 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
116 InsertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(),
117 Tail->getDebugLoc());
118 MBB->addSuccessor(NewDest);
121 // commuteInstruction - The default implementation of this method just exchanges
122 // the two operands returned by findCommutedOpIndices.
123 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
125 const MCInstrDesc &MCID = MI->getDesc();
126 bool HasDef = MCID.getNumDefs();
127 if (HasDef && !MI->getOperand(0).isReg())
128 // No idea how to commute this instruction. Target should implement its own.
131 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
132 assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
136 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
137 "This only knows how to commute register operands so far");
138 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
139 unsigned Reg1 = MI->getOperand(Idx1).getReg();
140 unsigned Reg2 = MI->getOperand(Idx2).getReg();
141 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
142 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
143 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
144 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
145 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
146 bool Reg1IsUndef = MI->getOperand(Idx1).isUndef();
147 bool Reg2IsUndef = MI->getOperand(Idx2).isUndef();
148 bool Reg1IsInternal = MI->getOperand(Idx1).isInternalRead();
149 bool Reg2IsInternal = MI->getOperand(Idx2).isInternalRead();
150 // If destination is tied to either of the commuted source register, then
151 // it must be updated.
152 if (HasDef && Reg0 == Reg1 &&
153 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
157 } else if (HasDef && Reg0 == Reg2 &&
158 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
165 // Create a new instruction.
166 MachineFunction &MF = *MI->getParent()->getParent();
167 MI = MF.CloneMachineInstr(MI);
171 MI->getOperand(0).setReg(Reg0);
172 MI->getOperand(0).setSubReg(SubReg0);
174 MI->getOperand(Idx2).setReg(Reg1);
175 MI->getOperand(Idx1).setReg(Reg2);
176 MI->getOperand(Idx2).setSubReg(SubReg1);
177 MI->getOperand(Idx1).setSubReg(SubReg2);
178 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
179 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
180 MI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
181 MI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
182 MI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
183 MI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
187 /// findCommutedOpIndices - If specified MI is commutable, return the two
188 /// operand indices that would swap value. Return true if the instruction
189 /// is not in a form which this routine understands.
190 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
192 unsigned &SrcOpIdx2) const {
193 assert(!MI->isBundle() &&
194 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
196 const MCInstrDesc &MCID = MI->getDesc();
197 if (!MCID.isCommutable())
199 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
200 // is not true, then the target must implement this.
201 SrcOpIdx1 = MCID.getNumDefs();
202 SrcOpIdx2 = SrcOpIdx1 + 1;
203 if (!MI->getOperand(SrcOpIdx1).isReg() ||
204 !MI->getOperand(SrcOpIdx2).isReg())
212 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
213 if (!MI->isTerminator()) return false;
215 // Conditional branch is a special case.
216 if (MI->isBranch() && !MI->isBarrier())
218 if (!MI->isPredicable())
220 return !isPredicated(MI);
223 bool TargetInstrInfo::PredicateInstruction(
224 MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
225 bool MadeChange = false;
227 assert(!MI->isBundle() &&
228 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
230 const MCInstrDesc &MCID = MI->getDesc();
231 if (!MI->isPredicable())
234 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
235 if (MCID.OpInfo[i].isPredicate()) {
236 MachineOperand &MO = MI->getOperand(i);
238 MO.setReg(Pred[j].getReg());
240 } else if (MO.isImm()) {
241 MO.setImm(Pred[j].getImm());
243 } else if (MO.isMBB()) {
244 MO.setMBB(Pred[j].getMBB());
253 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
254 const MachineMemOperand *&MMO,
255 int &FrameIndex) const {
256 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
257 oe = MI->memoperands_end();
260 if ((*o)->isLoad()) {
261 if (const FixedStackPseudoSourceValue *Value =
262 dyn_cast_or_null<FixedStackPseudoSourceValue>(
263 (*o)->getPseudoValue())) {
264 FrameIndex = Value->getFrameIndex();
273 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
274 const MachineMemOperand *&MMO,
275 int &FrameIndex) const {
276 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
277 oe = MI->memoperands_end();
280 if ((*o)->isStore()) {
281 if (const FixedStackPseudoSourceValue *Value =
282 dyn_cast_or_null<FixedStackPseudoSourceValue>(
283 (*o)->getPseudoValue())) {
284 FrameIndex = Value->getFrameIndex();
293 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
294 unsigned SubIdx, unsigned &Size,
296 const MachineFunction &MF) const {
298 Size = RC->getSize();
302 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
303 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
304 // Convert bit size to byte size to be consistent with
305 // MCRegisterClass::getSize().
309 int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
310 if (BitOffset < 0 || BitOffset % 8)
314 Offset = (unsigned)BitOffset / 8;
316 assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
318 if (!MF.getDataLayout().isLittleEndian()) {
319 Offset = RC->getSize() - (Offset + Size);
324 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
325 MachineBasicBlock::iterator I,
328 const MachineInstr *Orig,
329 const TargetRegisterInfo &TRI) const {
330 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
331 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
336 TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
337 const MachineInstr *MI1,
338 const MachineRegisterInfo *MRI) const {
339 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
342 MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
343 MachineFunction &MF) const {
344 assert(!Orig->isNotDuplicable() &&
345 "Instruction cannot be duplicated");
346 return MF.CloneMachineInstr(Orig);
349 // If the COPY instruction in MI can be folded to a stack operation, return
350 // the register class to use.
351 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
353 assert(MI->isCopy() && "MI must be a COPY instruction");
354 if (MI->getNumOperands() != 2)
356 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
358 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
359 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
361 if (FoldOp.getSubReg() || LiveOp.getSubReg())
364 unsigned FoldReg = FoldOp.getReg();
365 unsigned LiveReg = LiveOp.getReg();
367 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
368 "Cannot fold physregs");
370 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
371 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
373 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
374 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
376 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
379 // FIXME: Allow folding when register classes are memory compatible.
383 void TargetInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
384 llvm_unreachable("Not a MachO target");
387 static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr *MI,
388 ArrayRef<unsigned> Ops, int FrameIndex,
389 const TargetInstrInfo &TII) {
390 unsigned StartIdx = 0;
391 switch (MI->getOpcode()) {
392 case TargetOpcode::STACKMAP:
393 StartIdx = 2; // Skip ID, nShadowBytes.
395 case TargetOpcode::PATCHPOINT: {
396 // For PatchPoint, the call args are not foldable.
397 PatchPointOpers opers(MI);
398 StartIdx = opers.getVarIdx();
402 llvm_unreachable("unexpected stackmap opcode");
405 // Return false if any operands requested for folding are not foldable (not
406 // part of the stackmap's live values).
407 for (unsigned Op : Ops) {
412 MachineInstr *NewMI =
413 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
414 MachineInstrBuilder MIB(MF, NewMI);
416 // No need to fold return, the meta data, and function arguments
417 for (unsigned i = 0; i < StartIdx; ++i)
418 MIB.addOperand(MI->getOperand(i));
420 for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
421 MachineOperand &MO = MI->getOperand(i);
422 if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
424 unsigned SpillOffset;
425 // Compute the spill slot size and offset.
426 const TargetRegisterClass *RC =
427 MF.getRegInfo().getRegClass(MO.getReg());
429 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
431 report_fatal_error("cannot spill patchpoint subregister operand");
432 MIB.addImm(StackMaps::IndirectMemRefOp);
433 MIB.addImm(SpillSize);
434 MIB.addFrameIndex(FrameIndex);
435 MIB.addImm(SpillOffset);
443 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
444 /// slot into the specified machine instruction for the specified operand(s).
445 /// If this is possible, a new instruction is returned with the specified
446 /// operand folded, otherwise NULL is returned. The client is responsible for
447 /// removing the old instruction and adding the new one in the instruction
449 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
450 ArrayRef<unsigned> Ops,
453 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
454 if (MI->getOperand(Ops[i]).isDef())
455 Flags |= MachineMemOperand::MOStore;
457 Flags |= MachineMemOperand::MOLoad;
459 MachineBasicBlock *MBB = MI->getParent();
460 assert(MBB && "foldMemoryOperand needs an inserted instruction");
461 MachineFunction &MF = *MBB->getParent();
463 MachineInstr *NewMI = nullptr;
465 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
466 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
467 // Fold stackmap/patchpoint.
468 NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
470 MBB->insert(MI, NewMI);
472 // Ask the target to do the actual folding.
473 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI);
477 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
478 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
479 assert((!(Flags & MachineMemOperand::MOStore) ||
480 NewMI->mayStore()) &&
481 "Folded a def to a non-store!");
482 assert((!(Flags & MachineMemOperand::MOLoad) ||
484 "Folded a use to a non-load!");
485 const MachineFrameInfo &MFI = *MF.getFrameInfo();
486 assert(MFI.getObjectOffset(FI) != -1);
487 MachineMemOperand *MMO =
488 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
489 Flags, MFI.getObjectSize(FI),
490 MFI.getObjectAlignment(FI));
491 NewMI->addMemOperand(MF, MMO);
496 // Straight COPY may fold as load/store.
497 if (!MI->isCopy() || Ops.size() != 1)
500 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
504 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
505 MachineBasicBlock::iterator Pos = MI;
506 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
508 if (Flags == MachineMemOperand::MOStore)
509 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
511 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
515 /// foldMemoryOperand - Same as the previous version except it allows folding
516 /// of any load and store from / to any address, not just from a specific
518 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
519 ArrayRef<unsigned> Ops,
520 MachineInstr *LoadMI) const {
521 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
523 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
524 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
526 MachineBasicBlock &MBB = *MI->getParent();
527 MachineFunction &MF = *MBB.getParent();
529 // Ask the target to do the actual folding.
530 MachineInstr *NewMI = nullptr;
533 if ((MI->getOpcode() == TargetOpcode::STACKMAP ||
534 MI->getOpcode() == TargetOpcode::PATCHPOINT) &&
535 isLoadFromStackSlot(LoadMI, FrameIndex)) {
536 // Fold stackmap/patchpoint.
537 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
539 NewMI = MBB.insert(MI, NewMI);
541 // Ask the target to do the actual folding.
542 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI);
545 if (!NewMI) return nullptr;
547 // Copy the memoperands from the load to the folded instruction.
548 if (MI->memoperands_empty()) {
549 NewMI->setMemRefs(LoadMI->memoperands_begin(),
550 LoadMI->memoperands_end());
553 // Handle the rare case of folding multiple loads.
554 NewMI->setMemRefs(MI->memoperands_begin(),
555 MI->memoperands_end());
556 for (MachineInstr::mmo_iterator I = LoadMI->memoperands_begin(),
557 E = LoadMI->memoperands_end(); I != E; ++I) {
558 NewMI->addMemOperand(MF, *I);
564 bool TargetInstrInfo::
565 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
566 AliasAnalysis *AA) const {
567 const MachineFunction &MF = *MI->getParent()->getParent();
568 const MachineRegisterInfo &MRI = MF.getRegInfo();
570 // Remat clients assume operand 0 is the defined register.
571 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
573 unsigned DefReg = MI->getOperand(0).getReg();
575 // A sub-register definition can only be rematerialized if the instruction
576 // doesn't read the other parts of the register. Otherwise it is really a
577 // read-modify-write operation on the full virtual register which cannot be
579 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
580 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
583 // A load from a fixed stack slot can be rematerialized. This may be
584 // redundant with subsequent checks, but it's target-independent,
585 // simple, and a common case.
587 if (isLoadFromStackSlot(MI, FrameIdx) &&
588 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
591 // Avoid instructions obviously unsafe for remat.
592 if (MI->isNotDuplicable() || MI->mayStore() ||
593 MI->hasUnmodeledSideEffects())
596 // Don't remat inline asm. We have no idea how expensive it is
597 // even if it's side effect free.
598 if (MI->isInlineAsm())
601 // Avoid instructions which load from potentially varying memory.
602 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
605 // If any of the registers accessed are non-constant, conservatively assume
606 // the instruction is not rematerializable.
607 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
608 const MachineOperand &MO = MI->getOperand(i);
609 if (!MO.isReg()) continue;
610 unsigned Reg = MO.getReg();
614 // Check for a well-behaved physical register.
615 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
617 // If the physreg has no defs anywhere, it's just an ambient register
618 // and we can freely move its uses. Alternatively, if it's allocatable,
619 // it could get allocated to something with a def during allocation.
620 if (!MRI.isConstantPhysReg(Reg, MF))
623 // A physreg def. We can't remat it.
629 // Only allow one virtual-register def. There may be multiple defs of the
630 // same virtual register, though.
631 if (MO.isDef() && Reg != DefReg)
634 // Don't allow any virtual-register uses. Rematting an instruction with
635 // virtual register uses would length the live ranges of the uses, which
636 // is not necessarily a good idea, certainly not "trivial".
641 // Everything checked out.
645 int TargetInstrInfo::getSPAdjust(const MachineInstr *MI) const {
646 const MachineFunction *MF = MI->getParent()->getParent();
647 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
648 bool StackGrowsDown =
649 TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
651 unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
652 unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
654 if (MI->getOpcode() != FrameSetupOpcode &&
655 MI->getOpcode() != FrameDestroyOpcode)
658 int SPAdj = MI->getOperand(0).getImm();
660 if ((!StackGrowsDown && MI->getOpcode() == FrameSetupOpcode) ||
661 (StackGrowsDown && MI->getOpcode() == FrameDestroyOpcode))
667 /// isSchedulingBoundary - Test if the given instruction should be
668 /// considered a scheduling boundary. This primarily includes labels
670 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
671 const MachineBasicBlock *MBB,
672 const MachineFunction &MF) const {
673 // Terminators and labels can't be scheduled around.
674 if (MI->isTerminator() || MI->isPosition())
677 // Don't attempt to schedule around any instruction that defines
678 // a stack-oriented pointer, as it's unlikely to be profitable. This
679 // saves compile time, because it doesn't require every single
680 // stack slot reference to depend on the instruction that does the
682 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
683 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
684 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
690 // Provide a global flag for disabling the PreRA hazard recognizer that targets
691 // may choose to honor.
692 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
693 return !DisableHazardRecognizer;
696 // Default implementation of CreateTargetRAHazardRecognizer.
697 ScheduleHazardRecognizer *TargetInstrInfo::
698 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
699 const ScheduleDAG *DAG) const {
700 // Dummy hazard recognizer allows all instructions to issue.
701 return new ScheduleHazardRecognizer();
704 // Default implementation of CreateTargetMIHazardRecognizer.
705 ScheduleHazardRecognizer *TargetInstrInfo::
706 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
707 const ScheduleDAG *DAG) const {
708 return (ScheduleHazardRecognizer *)
709 new ScoreboardHazardRecognizer(II, DAG, "misched");
712 // Default implementation of CreateTargetPostRAHazardRecognizer.
713 ScheduleHazardRecognizer *TargetInstrInfo::
714 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
715 const ScheduleDAG *DAG) const {
716 return (ScheduleHazardRecognizer *)
717 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
720 //===----------------------------------------------------------------------===//
721 // SelectionDAG latency interface.
722 //===----------------------------------------------------------------------===//
725 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
726 SDNode *DefNode, unsigned DefIdx,
727 SDNode *UseNode, unsigned UseIdx) const {
728 if (!ItinData || ItinData->isEmpty())
731 if (!DefNode->isMachineOpcode())
734 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
735 if (!UseNode->isMachineOpcode())
736 return ItinData->getOperandCycle(DefClass, DefIdx);
737 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
738 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
741 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
743 if (!ItinData || ItinData->isEmpty())
746 if (!N->isMachineOpcode())
749 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
752 //===----------------------------------------------------------------------===//
753 // MachineInstr latency interface.
754 //===----------------------------------------------------------------------===//
757 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
758 const MachineInstr *MI) const {
759 if (!ItinData || ItinData->isEmpty())
762 unsigned Class = MI->getDesc().getSchedClass();
763 int UOps = ItinData->Itineraries[Class].NumMicroOps;
767 // The # of u-ops is dynamically determined. The specific target should
768 // override this function to return the right number.
772 /// Return the default expected latency for a def based on it's opcode.
773 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
774 const MachineInstr *DefMI) const {
775 if (DefMI->isTransient())
777 if (DefMI->mayLoad())
778 return SchedModel.LoadLatency;
779 if (isHighLatencyDef(DefMI->getOpcode()))
780 return SchedModel.HighLatency;
784 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
788 unsigned TargetInstrInfo::
789 getInstrLatency(const InstrItineraryData *ItinData,
790 const MachineInstr *MI,
791 unsigned *PredCost) const {
792 // Default to one cycle for no itinerary. However, an "empty" itinerary may
793 // still have a MinLatency property, which getStageLatency checks.
795 return MI->mayLoad() ? 2 : 1;
797 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
800 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
801 const MachineInstr *DefMI,
802 unsigned DefIdx) const {
803 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
804 if (!ItinData || ItinData->isEmpty())
807 unsigned DefClass = DefMI->getDesc().getSchedClass();
808 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
809 return (DefCycle != -1 && DefCycle <= 1);
812 /// Both DefMI and UseMI must be valid. By default, call directly to the
813 /// itinerary. This may be overriden by the target.
814 int TargetInstrInfo::
815 getOperandLatency(const InstrItineraryData *ItinData,
816 const MachineInstr *DefMI, unsigned DefIdx,
817 const MachineInstr *UseMI, unsigned UseIdx) const {
818 unsigned DefClass = DefMI->getDesc().getSchedClass();
819 unsigned UseClass = UseMI->getDesc().getSchedClass();
820 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
823 /// If we can determine the operand latency from the def only, without itinerary
824 /// lookup, do so. Otherwise return -1.
825 int TargetInstrInfo::computeDefOperandLatency(
826 const InstrItineraryData *ItinData,
827 const MachineInstr *DefMI) const {
829 // Let the target hook getInstrLatency handle missing itineraries.
831 return getInstrLatency(ItinData, DefMI);
833 if(ItinData->isEmpty())
834 return defaultDefLatency(ItinData->SchedModel, DefMI);
836 // ...operand lookup required
840 /// computeOperandLatency - Compute and return the latency of the given data
841 /// dependent def and use when the operand indices are already known. UseMI may
842 /// be NULL for an unknown use.
844 /// FindMin may be set to get the minimum vs. expected latency. Minimum
845 /// latency is used for scheduling groups, while expected latency is for
846 /// instruction cost and critical path.
848 /// Depending on the subtarget's itinerary properties, this may or may not need
849 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
850 /// UseIdx to compute min latency.
851 unsigned TargetInstrInfo::
852 computeOperandLatency(const InstrItineraryData *ItinData,
853 const MachineInstr *DefMI, unsigned DefIdx,
854 const MachineInstr *UseMI, unsigned UseIdx) const {
856 int DefLatency = computeDefOperandLatency(ItinData, DefMI);
860 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
864 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
866 unsigned DefClass = DefMI->getDesc().getSchedClass();
867 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
869 if (OperLatency >= 0)
872 // No operand latency was found.
873 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
875 // Expected latency is the max of the stage latency and itinerary props.
876 InstrLatency = std::max(InstrLatency,
877 defaultDefLatency(ItinData->SchedModel, DefMI));
881 bool TargetInstrInfo::getRegSequenceInputs(
882 const MachineInstr &MI, unsigned DefIdx,
883 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
884 assert((MI.isRegSequence() ||
885 MI.isRegSequenceLike()) && "Instruction do not have the proper type");
887 if (!MI.isRegSequence())
888 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
890 // We are looking at:
891 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
892 assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
893 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
895 const MachineOperand &MOReg = MI.getOperand(OpIdx);
896 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
897 assert(MOSubIdx.isImm() &&
898 "One of the subindex of the reg_sequence is not an immediate");
899 // Record Reg:SubReg, SubIdx.
900 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
901 (unsigned)MOSubIdx.getImm()));
906 bool TargetInstrInfo::getExtractSubregInputs(
907 const MachineInstr &MI, unsigned DefIdx,
908 RegSubRegPairAndIdx &InputReg) const {
909 assert((MI.isExtractSubreg() ||
910 MI.isExtractSubregLike()) && "Instruction do not have the proper type");
912 if (!MI.isExtractSubreg())
913 return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
915 // We are looking at:
916 // Def = EXTRACT_SUBREG v0.sub1, sub0.
917 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
918 const MachineOperand &MOReg = MI.getOperand(1);
919 const MachineOperand &MOSubIdx = MI.getOperand(2);
920 assert(MOSubIdx.isImm() &&
921 "The subindex of the extract_subreg is not an immediate");
923 InputReg.Reg = MOReg.getReg();
924 InputReg.SubReg = MOReg.getSubReg();
925 InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
929 bool TargetInstrInfo::getInsertSubregInputs(
930 const MachineInstr &MI, unsigned DefIdx,
931 RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
932 assert((MI.isInsertSubreg() ||
933 MI.isInsertSubregLike()) && "Instruction do not have the proper type");
935 if (!MI.isInsertSubreg())
936 return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
938 // We are looking at:
939 // Def = INSERT_SEQUENCE v0, v1, sub0.
940 assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
941 const MachineOperand &MOBaseReg = MI.getOperand(1);
942 const MachineOperand &MOInsertedReg = MI.getOperand(2);
943 const MachineOperand &MOSubIdx = MI.getOperand(3);
944 assert(MOSubIdx.isImm() &&
945 "One of the subindex of the reg_sequence is not an immediate");
946 BaseReg.Reg = MOBaseReg.getReg();
947 BaseReg.SubReg = MOBaseReg.getSubReg();
949 InsertedReg.Reg = MOInsertedReg.getReg();
950 InsertedReg.SubReg = MOInsertedReg.getSubReg();
951 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();