1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineMemOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
21 #include "llvm/CodeGen/StackMaps.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
34 static cl::opt<bool> DisableHazardRecognizer(
35 "disable-sched-hazard", cl::Hidden, cl::init(false),
36 cl::desc("Disable hazard detection during preRA scheduling"));
38 TargetInstrInfo::~TargetInstrInfo() {
41 const TargetRegisterClass*
42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
43 const TargetRegisterInfo *TRI,
44 const MachineFunction &MF) const {
45 if (OpNum >= MCID.getNumOperands())
48 short RegClass = MCID.OpInfo[OpNum].RegClass;
49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
50 return TRI->getPointerRegClass(MF, RegClass);
52 // Instructions like INSERT_SUBREG do not have fixed register classes.
56 // Otherwise just look it up normally.
57 return TRI->getRegClass(RegClass);
60 /// insertNoop - Insert a noop into the instruction stream at the specified
62 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI) const {
64 llvm_unreachable("Target didn't implement insertNoop!");
67 /// Measure the specified inline asm to determine an approximation of its
69 /// Comments (which run till the next SeparatorString or newline) do not
70 /// count as an instruction.
71 /// Any other non-whitespace text is considered an instruction, with
72 /// multiple instructions separated by SeparatorString or newlines.
73 /// Variable-length instructions are not handled here; this function
74 /// may be overloaded in the target code to do that.
75 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
76 const MCAsmInfo &MAI) const {
79 // Count the number of instructions in the asm.
80 bool atInsnStart = true;
83 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
84 strlen(MAI.getSeparatorString())) == 0)
86 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
87 Length += MAI.getMaxInstLength();
90 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
91 strlen(MAI.getCommentString())) == 0)
98 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
99 /// after it, replacing it with an unconditional branch to NewDest.
101 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
102 MachineBasicBlock *NewDest) const {
103 MachineBasicBlock *MBB = Tail->getParent();
105 // Remove all the old successors of MBB from the CFG.
106 while (!MBB->succ_empty())
107 MBB->removeSuccessor(MBB->succ_begin());
109 // Remove all the dead instructions from the end of MBB.
110 MBB->erase(Tail, MBB->end());
112 // If MBB isn't immediately before MBB, insert a branch to it.
113 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
114 InsertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(),
115 Tail->getDebugLoc());
116 MBB->addSuccessor(NewDest);
119 // commuteInstruction - The default implementation of this method just exchanges
120 // the two operands returned by findCommutedOpIndices.
121 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
123 const MCInstrDesc &MCID = MI->getDesc();
124 bool HasDef = MCID.getNumDefs();
125 if (HasDef && !MI->getOperand(0).isReg())
126 // No idea how to commute this instruction. Target should implement its own.
129 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
130 assert(MI->isCommutable() && "Precondition violation: MI must be commutable.");
134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
135 "This only knows how to commute register operands so far");
136 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
137 unsigned Reg1 = MI->getOperand(Idx1).getReg();
138 unsigned Reg2 = MI->getOperand(Idx2).getReg();
139 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
140 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
141 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
142 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
143 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
144 // If destination is tied to either of the commuted source register, then
145 // it must be updated.
146 if (HasDef && Reg0 == Reg1 &&
147 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
151 } else if (HasDef && Reg0 == Reg2 &&
152 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
159 // Create a new instruction.
160 MachineFunction &MF = *MI->getParent()->getParent();
161 MI = MF.CloneMachineInstr(MI);
165 MI->getOperand(0).setReg(Reg0);
166 MI->getOperand(0).setSubReg(SubReg0);
168 MI->getOperand(Idx2).setReg(Reg1);
169 MI->getOperand(Idx1).setReg(Reg2);
170 MI->getOperand(Idx2).setSubReg(SubReg1);
171 MI->getOperand(Idx1).setSubReg(SubReg2);
172 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
173 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
177 /// findCommutedOpIndices - If specified MI is commutable, return the two
178 /// operand indices that would swap value. Return true if the instruction
179 /// is not in a form which this routine understands.
180 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
182 unsigned &SrcOpIdx2) const {
183 assert(!MI->isBundle() &&
184 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
186 const MCInstrDesc &MCID = MI->getDesc();
187 if (!MCID.isCommutable())
189 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
190 // is not true, then the target must implement this.
191 SrcOpIdx1 = MCID.getNumDefs();
192 SrcOpIdx2 = SrcOpIdx1 + 1;
193 if (!MI->getOperand(SrcOpIdx1).isReg() ||
194 !MI->getOperand(SrcOpIdx2).isReg())
202 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
203 if (!MI->isTerminator()) return false;
205 // Conditional branch is a special case.
206 if (MI->isBranch() && !MI->isBarrier())
208 if (!MI->isPredicable())
210 return !isPredicated(MI);
214 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
215 const SmallVectorImpl<MachineOperand> &Pred) const {
216 bool MadeChange = false;
218 assert(!MI->isBundle() &&
219 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
221 const MCInstrDesc &MCID = MI->getDesc();
222 if (!MI->isPredicable())
225 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
226 if (MCID.OpInfo[i].isPredicate()) {
227 MachineOperand &MO = MI->getOperand(i);
229 MO.setReg(Pred[j].getReg());
231 } else if (MO.isImm()) {
232 MO.setImm(Pred[j].getImm());
234 } else if (MO.isMBB()) {
235 MO.setMBB(Pred[j].getMBB());
244 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
245 const MachineMemOperand *&MMO,
246 int &FrameIndex) const {
247 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
248 oe = MI->memoperands_end();
251 if ((*o)->isLoad()) {
252 if (const FixedStackPseudoSourceValue *Value =
253 dyn_cast_or_null<FixedStackPseudoSourceValue>(
254 (*o)->getPseudoValue())) {
255 FrameIndex = Value->getFrameIndex();
264 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
265 const MachineMemOperand *&MMO,
266 int &FrameIndex) const {
267 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
268 oe = MI->memoperands_end();
271 if ((*o)->isStore()) {
272 if (const FixedStackPseudoSourceValue *Value =
273 dyn_cast_or_null<FixedStackPseudoSourceValue>(
274 (*o)->getPseudoValue())) {
275 FrameIndex = Value->getFrameIndex();
284 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
285 unsigned SubIdx, unsigned &Size,
287 const TargetMachine *TM) const {
289 Size = RC->getSize();
294 TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxSize(SubIdx);
295 // Convert bit size to byte size to be consistent with
296 // MCRegisterClass::getSize().
301 TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxOffset(SubIdx);
302 if (BitOffset < 0 || BitOffset % 8)
306 Offset = (unsigned)BitOffset / 8;
308 assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
310 if (!TM->getSubtargetImpl()->getDataLayout()->isLittleEndian()) {
311 Offset = RC->getSize() - (Offset + Size);
316 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
317 MachineBasicBlock::iterator I,
320 const MachineInstr *Orig,
321 const TargetRegisterInfo &TRI) const {
322 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
323 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
328 TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
329 const MachineInstr *MI1,
330 const MachineRegisterInfo *MRI) const {
331 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
334 MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
335 MachineFunction &MF) const {
336 assert(!Orig->isNotDuplicable() &&
337 "Instruction cannot be duplicated");
338 return MF.CloneMachineInstr(Orig);
341 // If the COPY instruction in MI can be folded to a stack operation, return
342 // the register class to use.
343 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
345 assert(MI->isCopy() && "MI must be a COPY instruction");
346 if (MI->getNumOperands() != 2)
348 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
350 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
351 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
353 if (FoldOp.getSubReg() || LiveOp.getSubReg())
356 unsigned FoldReg = FoldOp.getReg();
357 unsigned LiveReg = LiveOp.getReg();
359 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
360 "Cannot fold physregs");
362 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
363 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
365 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
366 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
368 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
371 // FIXME: Allow folding when register classes are memory compatible.
375 void TargetInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
376 llvm_unreachable("Not a MachO target");
379 bool TargetInstrInfo::
380 canFoldMemoryOperand(const MachineInstr *MI,
381 const SmallVectorImpl<unsigned> &Ops) const {
382 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
385 static MachineInstr* foldPatchpoint(MachineFunction &MF,
387 const SmallVectorImpl<unsigned> &Ops,
389 const TargetInstrInfo &TII) {
390 unsigned StartIdx = 0;
391 switch (MI->getOpcode()) {
392 case TargetOpcode::STACKMAP:
393 StartIdx = 2; // Skip ID, nShadowBytes.
395 case TargetOpcode::PATCHPOINT: {
396 // For PatchPoint, the call args are not foldable.
397 PatchPointOpers opers(MI);
398 StartIdx = opers.getVarIdx();
402 llvm_unreachable("unexpected stackmap opcode");
405 // Return false if any operands requested for folding are not foldable (not
406 // part of the stackmap's live values).
407 for (SmallVectorImpl<unsigned>::const_iterator I = Ops.begin(), E = Ops.end();
413 MachineInstr *NewMI =
414 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
415 MachineInstrBuilder MIB(MF, NewMI);
417 // No need to fold return, the meta data, and function arguments
418 for (unsigned i = 0; i < StartIdx; ++i)
419 MIB.addOperand(MI->getOperand(i));
421 for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
422 MachineOperand &MO = MI->getOperand(i);
423 if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
425 unsigned SpillOffset;
426 // Compute the spill slot size and offset.
427 const TargetRegisterClass *RC =
428 MF.getRegInfo().getRegClass(MO.getReg());
429 bool Valid = TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize,
430 SpillOffset, &MF.getTarget());
432 report_fatal_error("cannot spill patchpoint subregister operand");
433 MIB.addImm(StackMaps::IndirectMemRefOp);
434 MIB.addImm(SpillSize);
435 MIB.addFrameIndex(FrameIndex);
436 MIB.addImm(SpillOffset);
444 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
445 /// slot into the specified machine instruction for the specified operand(s).
446 /// If this is possible, a new instruction is returned with the specified
447 /// operand folded, otherwise NULL is returned. The client is responsible for
448 /// removing the old instruction and adding the new one in the instruction
451 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
452 const SmallVectorImpl<unsigned> &Ops,
455 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
456 if (MI->getOperand(Ops[i]).isDef())
457 Flags |= MachineMemOperand::MOStore;
459 Flags |= MachineMemOperand::MOLoad;
461 MachineBasicBlock *MBB = MI->getParent();
462 assert(MBB && "foldMemoryOperand needs an inserted instruction");
463 MachineFunction &MF = *MBB->getParent();
465 MachineInstr *NewMI = nullptr;
467 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
468 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
469 // Fold stackmap/patchpoint.
470 NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
472 // Ask the target to do the actual folding.
473 NewMI =foldMemoryOperandImpl(MF, MI, Ops, FI);
477 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
478 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
479 assert((!(Flags & MachineMemOperand::MOStore) ||
480 NewMI->mayStore()) &&
481 "Folded a def to a non-store!");
482 assert((!(Flags & MachineMemOperand::MOLoad) ||
484 "Folded a use to a non-load!");
485 const MachineFrameInfo &MFI = *MF.getFrameInfo();
486 assert(MFI.getObjectOffset(FI) != -1);
487 MachineMemOperand *MMO =
488 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
489 Flags, MFI.getObjectSize(FI),
490 MFI.getObjectAlignment(FI));
491 NewMI->addMemOperand(MF, MMO);
493 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
494 return MBB->insert(MI, NewMI);
497 // Straight COPY may fold as load/store.
498 if (!MI->isCopy() || Ops.size() != 1)
501 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
505 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
506 MachineBasicBlock::iterator Pos = MI;
507 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
509 if (Flags == MachineMemOperand::MOStore)
510 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
512 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
516 /// foldMemoryOperand - Same as the previous version except it allows folding
517 /// of any load and store from / to any address, not just from a specific
520 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
521 const SmallVectorImpl<unsigned> &Ops,
522 MachineInstr* LoadMI) const {
523 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
525 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
526 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
528 MachineBasicBlock &MBB = *MI->getParent();
529 MachineFunction &MF = *MBB.getParent();
531 // Ask the target to do the actual folding.
532 MachineInstr *NewMI = nullptr;
535 if ((MI->getOpcode() == TargetOpcode::STACKMAP ||
536 MI->getOpcode() == TargetOpcode::PATCHPOINT) &&
537 isLoadFromStackSlot(LoadMI, FrameIndex)) {
538 // Fold stackmap/patchpoint.
539 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
541 // Ask the target to do the actual folding.
542 NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
545 if (!NewMI) return nullptr;
547 NewMI = MBB.insert(MI, NewMI);
549 // Copy the memoperands from the load to the folded instruction.
550 if (MI->memoperands_empty()) {
551 NewMI->setMemRefs(LoadMI->memoperands_begin(),
552 LoadMI->memoperands_end());
555 // Handle the rare case of folding multiple loads.
556 NewMI->setMemRefs(MI->memoperands_begin(),
557 MI->memoperands_end());
558 for (MachineInstr::mmo_iterator I = LoadMI->memoperands_begin(),
559 E = LoadMI->memoperands_end(); I != E; ++I) {
560 NewMI->addMemOperand(MF, *I);
566 bool TargetInstrInfo::
567 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
568 AliasAnalysis *AA) const {
569 const MachineFunction &MF = *MI->getParent()->getParent();
570 const MachineRegisterInfo &MRI = MF.getRegInfo();
572 // Remat clients assume operand 0 is the defined register.
573 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
575 unsigned DefReg = MI->getOperand(0).getReg();
577 // A sub-register definition can only be rematerialized if the instruction
578 // doesn't read the other parts of the register. Otherwise it is really a
579 // read-modify-write operation on the full virtual register which cannot be
581 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
582 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
585 // A load from a fixed stack slot can be rematerialized. This may be
586 // redundant with subsequent checks, but it's target-independent,
587 // simple, and a common case.
589 if (isLoadFromStackSlot(MI, FrameIdx) &&
590 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
593 // Avoid instructions obviously unsafe for remat.
594 if (MI->isNotDuplicable() || MI->mayStore() ||
595 MI->hasUnmodeledSideEffects())
598 // Don't remat inline asm. We have no idea how expensive it is
599 // even if it's side effect free.
600 if (MI->isInlineAsm())
603 // Avoid instructions which load from potentially varying memory.
604 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
607 // If any of the registers accessed are non-constant, conservatively assume
608 // the instruction is not rematerializable.
609 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
610 const MachineOperand &MO = MI->getOperand(i);
611 if (!MO.isReg()) continue;
612 unsigned Reg = MO.getReg();
616 // Check for a well-behaved physical register.
617 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
619 // If the physreg has no defs anywhere, it's just an ambient register
620 // and we can freely move its uses. Alternatively, if it's allocatable,
621 // it could get allocated to something with a def during allocation.
622 if (!MRI.isConstantPhysReg(Reg, MF))
625 // A physreg def. We can't remat it.
631 // Only allow one virtual-register def. There may be multiple defs of the
632 // same virtual register, though.
633 if (MO.isDef() && Reg != DefReg)
636 // Don't allow any virtual-register uses. Rematting an instruction with
637 // virtual register uses would length the live ranges of the uses, which
638 // is not necessarily a good idea, certainly not "trivial".
643 // Everything checked out.
647 /// isSchedulingBoundary - Test if the given instruction should be
648 /// considered a scheduling boundary. This primarily includes labels
650 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
651 const MachineBasicBlock *MBB,
652 const MachineFunction &MF) const {
653 // Terminators and labels can't be scheduled around.
654 if (MI->isTerminator() || MI->isPosition())
657 // Don't attempt to schedule around any instruction that defines
658 // a stack-oriented pointer, as it's unlikely to be profitable. This
659 // saves compile time, because it doesn't require every single
660 // stack slot reference to depend on the instruction that does the
662 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
663 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
664 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
670 // Provide a global flag for disabling the PreRA hazard recognizer that targets
671 // may choose to honor.
672 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
673 return !DisableHazardRecognizer;
676 // Default implementation of CreateTargetRAHazardRecognizer.
677 ScheduleHazardRecognizer *TargetInstrInfo::
678 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
679 const ScheduleDAG *DAG) const {
680 // Dummy hazard recognizer allows all instructions to issue.
681 return new ScheduleHazardRecognizer();
684 // Default implementation of CreateTargetMIHazardRecognizer.
685 ScheduleHazardRecognizer *TargetInstrInfo::
686 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
687 const ScheduleDAG *DAG) const {
688 return (ScheduleHazardRecognizer *)
689 new ScoreboardHazardRecognizer(II, DAG, "misched");
692 // Default implementation of CreateTargetPostRAHazardRecognizer.
693 ScheduleHazardRecognizer *TargetInstrInfo::
694 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
695 const ScheduleDAG *DAG) const {
696 return (ScheduleHazardRecognizer *)
697 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
700 //===----------------------------------------------------------------------===//
701 // SelectionDAG latency interface.
702 //===----------------------------------------------------------------------===//
705 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
706 SDNode *DefNode, unsigned DefIdx,
707 SDNode *UseNode, unsigned UseIdx) const {
708 if (!ItinData || ItinData->isEmpty())
711 if (!DefNode->isMachineOpcode())
714 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
715 if (!UseNode->isMachineOpcode())
716 return ItinData->getOperandCycle(DefClass, DefIdx);
717 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
718 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
721 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
723 if (!ItinData || ItinData->isEmpty())
726 if (!N->isMachineOpcode())
729 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
732 //===----------------------------------------------------------------------===//
733 // MachineInstr latency interface.
734 //===----------------------------------------------------------------------===//
737 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
738 const MachineInstr *MI) const {
739 if (!ItinData || ItinData->isEmpty())
742 unsigned Class = MI->getDesc().getSchedClass();
743 int UOps = ItinData->Itineraries[Class].NumMicroOps;
747 // The # of u-ops is dynamically determined. The specific target should
748 // override this function to return the right number.
752 /// Return the default expected latency for a def based on it's opcode.
753 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
754 const MachineInstr *DefMI) const {
755 if (DefMI->isTransient())
757 if (DefMI->mayLoad())
758 return SchedModel.LoadLatency;
759 if (isHighLatencyDef(DefMI->getOpcode()))
760 return SchedModel.HighLatency;
764 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
768 unsigned TargetInstrInfo::
769 getInstrLatency(const InstrItineraryData *ItinData,
770 const MachineInstr *MI,
771 unsigned *PredCost) const {
772 // Default to one cycle for no itinerary. However, an "empty" itinerary may
773 // still have a MinLatency property, which getStageLatency checks.
775 return MI->mayLoad() ? 2 : 1;
777 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
780 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
781 const MachineInstr *DefMI,
782 unsigned DefIdx) const {
783 if (!ItinData || ItinData->isEmpty())
786 unsigned DefClass = DefMI->getDesc().getSchedClass();
787 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
788 return (DefCycle != -1 && DefCycle <= 1);
791 /// Both DefMI and UseMI must be valid. By default, call directly to the
792 /// itinerary. This may be overriden by the target.
793 int TargetInstrInfo::
794 getOperandLatency(const InstrItineraryData *ItinData,
795 const MachineInstr *DefMI, unsigned DefIdx,
796 const MachineInstr *UseMI, unsigned UseIdx) const {
797 unsigned DefClass = DefMI->getDesc().getSchedClass();
798 unsigned UseClass = UseMI->getDesc().getSchedClass();
799 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
802 /// If we can determine the operand latency from the def only, without itinerary
803 /// lookup, do so. Otherwise return -1.
804 int TargetInstrInfo::computeDefOperandLatency(
805 const InstrItineraryData *ItinData,
806 const MachineInstr *DefMI) const {
808 // Let the target hook getInstrLatency handle missing itineraries.
810 return getInstrLatency(ItinData, DefMI);
812 if(ItinData->isEmpty())
813 return defaultDefLatency(ItinData->SchedModel, DefMI);
815 // ...operand lookup required
819 /// computeOperandLatency - Compute and return the latency of the given data
820 /// dependent def and use when the operand indices are already known. UseMI may
821 /// be NULL for an unknown use.
823 /// FindMin may be set to get the minimum vs. expected latency. Minimum
824 /// latency is used for scheduling groups, while expected latency is for
825 /// instruction cost and critical path.
827 /// Depending on the subtarget's itinerary properties, this may or may not need
828 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
829 /// UseIdx to compute min latency.
830 unsigned TargetInstrInfo::
831 computeOperandLatency(const InstrItineraryData *ItinData,
832 const MachineInstr *DefMI, unsigned DefIdx,
833 const MachineInstr *UseMI, unsigned UseIdx) const {
835 int DefLatency = computeDefOperandLatency(ItinData, DefMI);
839 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
843 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
845 unsigned DefClass = DefMI->getDesc().getSchedClass();
846 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
848 if (OperLatency >= 0)
851 // No operand latency was found.
852 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
854 // Expected latency is the max of the stage latency and itinerary props.
855 InstrLatency = std::max(InstrLatency,
856 defaultDefLatency(ItinData->SchedModel, DefMI));
860 bool TargetInstrInfo::getRegSequenceInputs(
861 const MachineInstr &MI, unsigned DefIdx,
862 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
863 assert((MI.isRegSequence() ||
864 MI.isRegSequenceLike()) && "Instruction do not have the proper type");
866 if (!MI.isRegSequence())
867 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
869 // We are looking at:
870 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
871 assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
872 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
874 const MachineOperand &MOReg = MI.getOperand(OpIdx);
875 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
876 assert(MOSubIdx.isImm() &&
877 "One of the subindex of the reg_sequence is not an immediate");
878 // Record Reg:SubReg, SubIdx.
879 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
880 (unsigned)MOSubIdx.getImm()));
885 bool TargetInstrInfo::getExtractSubregInputs(
886 const MachineInstr &MI, unsigned DefIdx,
887 RegSubRegPairAndIdx &InputReg) const {
888 assert((MI.isExtractSubreg() ||
889 MI.isExtractSubregLike()) && "Instruction do not have the proper type");
891 if (!MI.isExtractSubreg())
892 return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
894 // We are looking at:
895 // Def = EXTRACT_SUBREG v0.sub1, sub0.
896 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
897 const MachineOperand &MOReg = MI.getOperand(1);
898 const MachineOperand &MOSubIdx = MI.getOperand(2);
899 assert(MOSubIdx.isImm() &&
900 "The subindex of the extract_subreg is not an immediate");
902 InputReg.Reg = MOReg.getReg();
903 InputReg.SubReg = MOReg.getSubReg();
904 InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
908 bool TargetInstrInfo::getInsertSubregInputs(
909 const MachineInstr &MI, unsigned DefIdx,
910 RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
911 assert((MI.isInsertSubreg() ||
912 MI.isInsertSubregLike()) && "Instruction do not have the proper type");
914 if (!MI.isInsertSubreg())
915 return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
917 // We are looking at:
918 // Def = INSERT_SEQUENCE v0, v1, sub0.
919 assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
920 const MachineOperand &MOBaseReg = MI.getOperand(1);
921 const MachineOperand &MOInsertedReg = MI.getOperand(2);
922 const MachineOperand &MOSubIdx = MI.getOperand(3);
923 assert(MOSubIdx.isImm() &&
924 "One of the subindex of the reg_sequence is not an immediate");
925 BaseReg.Reg = MOBaseReg.getReg();
926 BaseReg.SubReg = MOBaseReg.getSubReg();
928 InsertedReg.Reg = MOInsertedReg.getReg();
929 InsertedReg.SubReg = MOInsertedReg.getSubReg();
930 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();