1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetLowering.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCInstrItineraries.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
34 static cl::opt<bool> DisableHazardRecognizer(
35 "disable-sched-hazard", cl::Hidden, cl::init(false),
36 cl::desc("Disable hazard detection during preRA scheduling"));
38 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
39 /// after it, replacing it with an unconditional branch to NewDest.
41 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
42 MachineBasicBlock *NewDest) const {
43 MachineBasicBlock *MBB = Tail->getParent();
45 // Remove all the old successors of MBB from the CFG.
46 while (!MBB->succ_empty())
47 MBB->removeSuccessor(MBB->succ_begin());
49 // Remove all the dead instructions from the end of MBB.
50 MBB->erase(Tail, MBB->end());
52 // If MBB isn't immediately before MBB, insert a branch to it.
53 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
54 InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
56 MBB->addSuccessor(NewDest);
59 // commuteInstruction - The default implementation of this method just exchanges
60 // the two operands returned by findCommutedOpIndices.
61 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
63 const MCInstrDesc &MCID = MI->getDesc();
64 bool HasDef = MCID.getNumDefs();
65 if (HasDef && !MI->getOperand(0).isReg())
66 // No idea how to commute this instruction. Target should implement its own.
69 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
71 raw_string_ostream Msg(msg);
72 Msg << "Don't know how to commute: " << *MI;
73 report_fatal_error(Msg.str());
76 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
77 "This only knows how to commute register operands so far");
78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
79 unsigned Reg1 = MI->getOperand(Idx1).getReg();
80 unsigned Reg2 = MI->getOperand(Idx2).getReg();
81 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
82 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
83 // If destination is tied to either of the commuted source register, then
84 // it must be updated.
85 if (HasDef && Reg0 == Reg1 &&
86 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
89 } else if (HasDef && Reg0 == Reg2 &&
90 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
96 // Create a new instruction.
97 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
98 MachineFunction &MF = *MI->getParent()->getParent();
100 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
101 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
102 .addReg(Reg2, getKillRegState(Reg2IsKill))
103 .addReg(Reg1, getKillRegState(Reg2IsKill));
105 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
106 .addReg(Reg2, getKillRegState(Reg2IsKill))
107 .addReg(Reg1, getKillRegState(Reg2IsKill));
111 MI->getOperand(0).setReg(Reg0);
112 MI->getOperand(Idx2).setReg(Reg1);
113 MI->getOperand(Idx1).setReg(Reg2);
114 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
115 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
119 /// findCommutedOpIndices - If specified MI is commutable, return the two
120 /// operand indices that would swap value. Return true if the instruction
121 /// is not in a form which this routine understands.
122 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
124 unsigned &SrcOpIdx2) const {
125 assert(!MI->isBundle() &&
126 "TargetInstrInfoImpl::findCommutedOpIndices() can't handle bundles");
128 const MCInstrDesc &MCID = MI->getDesc();
129 if (!MCID.isCommutable())
131 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
132 // is not true, then the target must implement this.
133 SrcOpIdx1 = MCID.getNumDefs();
134 SrcOpIdx2 = SrcOpIdx1 + 1;
135 if (!MI->getOperand(SrcOpIdx1).isReg() ||
136 !MI->getOperand(SrcOpIdx2).isReg())
144 TargetInstrInfoImpl::isUnpredicatedTerminator(const MachineInstr *MI) const {
145 if (!MI->isTerminator()) return false;
147 // Conditional branch is a special case.
148 if (MI->isBranch() && !MI->isBarrier())
150 if (!MI->isPredicable())
152 return !isPredicated(MI);
156 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
157 const SmallVectorImpl<MachineOperand> &Pred) const {
158 bool MadeChange = false;
160 assert(!MI->isBundle() &&
161 "TargetInstrInfoImpl::PredicateInstruction() can't handle bundles");
163 const MCInstrDesc &MCID = MI->getDesc();
164 if (!MI->isPredicable())
167 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 if (MCID.OpInfo[i].isPredicate()) {
169 MachineOperand &MO = MI->getOperand(i);
171 MO.setReg(Pred[j].getReg());
173 } else if (MO.isImm()) {
174 MO.setImm(Pred[j].getImm());
176 } else if (MO.isMBB()) {
177 MO.setMBB(Pred[j].getMBB());
186 bool TargetInstrInfoImpl::hasLoadFromStackSlot(const MachineInstr *MI,
187 const MachineMemOperand *&MMO,
188 int &FrameIndex) const {
189 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
190 oe = MI->memoperands_end();
193 if ((*o)->isLoad() && (*o)->getValue())
194 if (const FixedStackPseudoSourceValue *Value =
195 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
196 FrameIndex = Value->getFrameIndex();
204 bool TargetInstrInfoImpl::hasStoreToStackSlot(const MachineInstr *MI,
205 const MachineMemOperand *&MMO,
206 int &FrameIndex) const {
207 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
208 oe = MI->memoperands_end();
211 if ((*o)->isStore() && (*o)->getValue())
212 if (const FixedStackPseudoSourceValue *Value =
213 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
214 FrameIndex = Value->getFrameIndex();
222 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator I,
226 const MachineInstr *Orig,
227 const TargetRegisterInfo &TRI) const {
228 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
229 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
234 TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
235 const MachineInstr *MI1,
236 const MachineRegisterInfo *MRI) const {
237 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
240 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
241 MachineFunction &MF) const {
242 assert(!Orig->isNotDuplicable() &&
243 "Instruction cannot be duplicated");
244 return MF.CloneMachineInstr(Orig);
247 // If the COPY instruction in MI can be folded to a stack operation, return
248 // the register class to use.
249 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
251 assert(MI->isCopy() && "MI must be a COPY instruction");
252 if (MI->getNumOperands() != 2)
254 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
256 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
257 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
259 if (FoldOp.getSubReg() || LiveOp.getSubReg())
262 unsigned FoldReg = FoldOp.getReg();
263 unsigned LiveReg = LiveOp.getReg();
265 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
266 "Cannot fold physregs");
268 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
269 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
271 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
272 return RC->contains(LiveOp.getReg()) ? RC : 0;
274 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
277 // FIXME: Allow folding when register classes are memory compatible.
281 bool TargetInstrInfoImpl::
282 canFoldMemoryOperand(const MachineInstr *MI,
283 const SmallVectorImpl<unsigned> &Ops) const {
284 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
287 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
288 /// slot into the specified machine instruction for the specified operand(s).
289 /// If this is possible, a new instruction is returned with the specified
290 /// operand folded, otherwise NULL is returned. The client is responsible for
291 /// removing the old instruction and adding the new one in the instruction
294 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
295 const SmallVectorImpl<unsigned> &Ops,
298 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
299 if (MI->getOperand(Ops[i]).isDef())
300 Flags |= MachineMemOperand::MOStore;
302 Flags |= MachineMemOperand::MOLoad;
304 MachineBasicBlock *MBB = MI->getParent();
305 assert(MBB && "foldMemoryOperand needs an inserted instruction");
306 MachineFunction &MF = *MBB->getParent();
308 // Ask the target to do the actual folding.
309 if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
310 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
311 assert((!(Flags & MachineMemOperand::MOStore) ||
312 NewMI->mayStore()) &&
313 "Folded a def to a non-store!");
314 assert((!(Flags & MachineMemOperand::MOLoad) ||
316 "Folded a use to a non-load!");
317 const MachineFrameInfo &MFI = *MF.getFrameInfo();
318 assert(MFI.getObjectOffset(FI) != -1);
319 MachineMemOperand *MMO =
320 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
321 Flags, MFI.getObjectSize(FI),
322 MFI.getObjectAlignment(FI));
323 NewMI->addMemOperand(MF, MMO);
325 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
326 return MBB->insert(MI, NewMI);
329 // Straight COPY may fold as load/store.
330 if (!MI->isCopy() || Ops.size() != 1)
333 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
337 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
338 MachineBasicBlock::iterator Pos = MI;
339 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
341 if (Flags == MachineMemOperand::MOStore)
342 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
344 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
348 /// foldMemoryOperand - Same as the previous version except it allows folding
349 /// of any load and store from / to any address, not just from a specific
352 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
353 const SmallVectorImpl<unsigned> &Ops,
354 MachineInstr* LoadMI) const {
355 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
357 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
358 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
360 MachineBasicBlock &MBB = *MI->getParent();
361 MachineFunction &MF = *MBB.getParent();
363 // Ask the target to do the actual folding.
364 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
365 if (!NewMI) return 0;
367 NewMI = MBB.insert(MI, NewMI);
369 // Copy the memoperands from the load to the folded instruction.
370 NewMI->setMemRefs(LoadMI->memoperands_begin(),
371 LoadMI->memoperands_end());
376 bool TargetInstrInfo::
377 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
378 AliasAnalysis *AA) const {
379 const MachineFunction &MF = *MI->getParent()->getParent();
380 const MachineRegisterInfo &MRI = MF.getRegInfo();
381 const TargetMachine &TM = MF.getTarget();
382 const TargetInstrInfo &TII = *TM.getInstrInfo();
383 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
385 // Remat clients assume operand 0 is the defined register.
386 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
388 unsigned DefReg = MI->getOperand(0).getReg();
390 // A sub-register definition can only be rematerialized if the instruction
391 // doesn't read the other parts of the register. Otherwise it is really a
392 // read-modify-write operation on the full virtual register which cannot be
394 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
395 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
398 // A load from a fixed stack slot can be rematerialized. This may be
399 // redundant with subsequent checks, but it's target-independent,
400 // simple, and a common case.
402 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
403 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
406 // Avoid instructions obviously unsafe for remat.
407 if (MI->isNotDuplicable() || MI->mayStore() ||
408 MI->hasUnmodeledSideEffects())
411 // Don't remat inline asm. We have no idea how expensive it is
412 // even if it's side effect free.
413 if (MI->isInlineAsm())
416 // Avoid instructions which load from potentially varying memory.
417 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
420 // If any of the registers accessed are non-constant, conservatively assume
421 // the instruction is not rematerializable.
422 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
423 const MachineOperand &MO = MI->getOperand(i);
424 if (!MO.isReg()) continue;
425 unsigned Reg = MO.getReg();
429 // Check for a well-behaved physical register.
430 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
432 // If the physreg has no defs anywhere, it's just an ambient register
433 // and we can freely move its uses. Alternatively, if it's allocatable,
434 // it could get allocated to something with a def during allocation.
435 if (!MRI.def_empty(Reg))
437 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
438 if (AllocatableRegs.test(Reg))
440 // Check for a def among the register's aliases too.
441 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
442 unsigned AliasReg = *Alias;
443 if (!MRI.def_empty(AliasReg))
445 if (AllocatableRegs.test(AliasReg))
449 // A physreg def. We can't remat it.
455 // Only allow one virtual-register def. There may be multiple defs of the
456 // same virtual register, though.
457 if (MO.isDef() && Reg != DefReg)
460 // Don't allow any virtual-register uses. Rematting an instruction with
461 // virtual register uses would length the live ranges of the uses, which
462 // is not necessarily a good idea, certainly not "trivial".
467 // Everything checked out.
471 /// isSchedulingBoundary - Test if the given instruction should be
472 /// considered a scheduling boundary. This primarily includes labels
474 bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
475 const MachineBasicBlock *MBB,
476 const MachineFunction &MF) const{
477 // Terminators and labels can't be scheduled around.
478 if (MI->isTerminator() || MI->isLabel())
481 // Don't attempt to schedule around any instruction that defines
482 // a stack-oriented pointer, as it's unlikely to be profitable. This
483 // saves compile time, because it doesn't require every single
484 // stack slot reference to depend on the instruction that does the
486 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
487 if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
493 // Provide a global flag for disabling the PreRA hazard recognizer that targets
494 // may choose to honor.
495 bool TargetInstrInfoImpl::usePreRAHazardRecognizer() const {
496 return !DisableHazardRecognizer;
499 // Default implementation of CreateTargetRAHazardRecognizer.
500 ScheduleHazardRecognizer *TargetInstrInfoImpl::
501 CreateTargetHazardRecognizer(const TargetMachine *TM,
502 const ScheduleDAG *DAG) const {
503 // Dummy hazard recognizer allows all instructions to issue.
504 return new ScheduleHazardRecognizer();
507 // Default implementation of CreateTargetPostRAHazardRecognizer.
508 ScheduleHazardRecognizer *TargetInstrInfoImpl::
509 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
510 const ScheduleDAG *DAG) const {
511 return (ScheduleHazardRecognizer *)
512 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
516 TargetInstrInfoImpl::getOperandLatency(const InstrItineraryData *ItinData,
517 SDNode *DefNode, unsigned DefIdx,
518 SDNode *UseNode, unsigned UseIdx) const {
519 if (!ItinData || ItinData->isEmpty())
522 if (!DefNode->isMachineOpcode())
525 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
526 if (!UseNode->isMachineOpcode())
527 return ItinData->getOperandCycle(DefClass, DefIdx);
528 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
529 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
532 int TargetInstrInfoImpl::getInstrLatency(const InstrItineraryData *ItinData,
534 if (!ItinData || ItinData->isEmpty())
537 if (!N->isMachineOpcode())
540 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());