1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetLowering.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PostRAHazardRecognizer.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
31 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
32 /// after it, replacing it with an unconditional branch to NewDest.
34 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
35 MachineBasicBlock *NewDest) const {
36 MachineBasicBlock *MBB = Tail->getParent();
38 // Remove all the old successors of MBB from the CFG.
39 while (!MBB->succ_empty())
40 MBB->removeSuccessor(MBB->succ_begin());
42 // Remove all the dead instructions from the end of MBB.
43 MBB->erase(Tail, MBB->end());
45 // If MBB isn't immediately before MBB, insert a branch to it.
46 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
47 InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
49 MBB->addSuccessor(NewDest);
52 // commuteInstruction - The default implementation of this method just exchanges
53 // the two operands returned by findCommutedOpIndices.
54 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
56 const TargetInstrDesc &TID = MI->getDesc();
57 bool HasDef = TID.getNumDefs();
58 if (HasDef && !MI->getOperand(0).isReg())
59 // No idea how to commute this instruction. Target should implement its own.
62 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
64 raw_string_ostream Msg(msg);
65 Msg << "Don't know how to commute: " << *MI;
66 report_fatal_error(Msg.str());
69 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
70 "This only knows how to commute register operands so far");
71 unsigned Reg1 = MI->getOperand(Idx1).getReg();
72 unsigned Reg2 = MI->getOperand(Idx2).getReg();
73 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
74 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
75 bool ChangeReg0 = false;
76 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
77 // Must be two address instruction!
78 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
79 "Expecting a two-address instruction!");
85 // Create a new instruction.
86 unsigned Reg0 = HasDef
87 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
88 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
89 MachineFunction &MF = *MI->getParent()->getParent();
91 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
92 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
93 .addReg(Reg2, getKillRegState(Reg2IsKill))
94 .addReg(Reg1, getKillRegState(Reg2IsKill));
96 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
97 .addReg(Reg2, getKillRegState(Reg2IsKill))
98 .addReg(Reg1, getKillRegState(Reg2IsKill));
102 MI->getOperand(0).setReg(Reg2);
103 MI->getOperand(Idx2).setReg(Reg1);
104 MI->getOperand(Idx1).setReg(Reg2);
105 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
106 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
110 /// findCommutedOpIndices - If specified MI is commutable, return the two
111 /// operand indices that would swap value. Return true if the instruction
112 /// is not in a form which this routine understands.
113 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
115 unsigned &SrcOpIdx2) const {
116 const TargetInstrDesc &TID = MI->getDesc();
117 if (!TID.isCommutable())
119 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
120 // is not true, then the target must implement this.
121 SrcOpIdx1 = TID.getNumDefs();
122 SrcOpIdx2 = SrcOpIdx1 + 1;
123 if (!MI->getOperand(SrcOpIdx1).isReg() ||
124 !MI->getOperand(SrcOpIdx2).isReg())
131 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
132 const SmallVectorImpl<MachineOperand> &Pred) const {
133 bool MadeChange = false;
134 const TargetInstrDesc &TID = MI->getDesc();
135 if (!TID.isPredicable())
138 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
139 if (TID.OpInfo[i].isPredicate()) {
140 MachineOperand &MO = MI->getOperand(i);
142 MO.setReg(Pred[j].getReg());
144 } else if (MO.isImm()) {
145 MO.setImm(Pred[j].getImm());
147 } else if (MO.isMBB()) {
148 MO.setMBB(Pred[j].getMBB());
157 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I,
161 const MachineInstr *Orig,
162 const TargetRegisterInfo &TRI) const {
163 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
164 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
168 bool TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
169 const MachineInstr *MI1) const {
170 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
173 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
174 MachineFunction &MF) const {
175 assert(!Orig->getDesc().isNotDuplicable() &&
176 "Instruction cannot be duplicated");
177 return MF.CloneMachineInstr(Orig);
181 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
183 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
185 const MachineBasicBlock &MBB = *MBBI;
186 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
188 FnSize += GetInstSizeInBytes(I);
193 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
194 /// slot into the specified machine instruction for the specified operand(s).
195 /// If this is possible, a new instruction is returned with the specified
196 /// operand folded, otherwise NULL is returned. The client is responsible for
197 /// removing the old instruction and adding the new one in the instruction
200 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
202 const SmallVectorImpl<unsigned> &Ops,
203 int FrameIndex) const {
205 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
206 if (MI->getOperand(Ops[i]).isDef())
207 Flags |= MachineMemOperand::MOStore;
209 Flags |= MachineMemOperand::MOLoad;
211 // Ask the target to do the actual folding.
212 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
213 if (!NewMI) return 0;
215 assert((!(Flags & MachineMemOperand::MOStore) ||
216 NewMI->getDesc().mayStore()) &&
217 "Folded a def to a non-store!");
218 assert((!(Flags & MachineMemOperand::MOLoad) ||
219 NewMI->getDesc().mayLoad()) &&
220 "Folded a use to a non-load!");
221 const MachineFrameInfo &MFI = *MF.getFrameInfo();
222 assert(MFI.getObjectOffset(FrameIndex) != -1);
223 MachineMemOperand *MMO =
224 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex),
226 MFI.getObjectSize(FrameIndex),
227 MFI.getObjectAlignment(FrameIndex));
228 NewMI->addMemOperand(MF, MMO);
233 /// foldMemoryOperand - Same as the previous version except it allows folding
234 /// of any load and store from / to any address, not just from a specific
237 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
239 const SmallVectorImpl<unsigned> &Ops,
240 MachineInstr* LoadMI) const {
241 assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
243 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
244 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
247 // Ask the target to do the actual folding.
248 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
249 if (!NewMI) return 0;
251 // Copy the memoperands from the load to the folded instruction.
252 NewMI->setMemRefs(LoadMI->memoperands_begin(),
253 LoadMI->memoperands_end());
258 bool TargetInstrInfo::
259 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
260 AliasAnalysis *AA) const {
261 const MachineFunction &MF = *MI->getParent()->getParent();
262 const MachineRegisterInfo &MRI = MF.getRegInfo();
263 const TargetMachine &TM = MF.getTarget();
264 const TargetInstrInfo &TII = *TM.getInstrInfo();
265 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
267 // A load from a fixed stack slot can be rematerialized. This may be
268 // redundant with subsequent checks, but it's target-independent,
269 // simple, and a common case.
271 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
272 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
275 const TargetInstrDesc &TID = MI->getDesc();
277 // Avoid instructions obviously unsafe for remat.
278 if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable() ||
282 // Avoid instructions which load from potentially varying memory.
283 if (TID.mayLoad() && !MI->isInvariantLoad(AA))
286 // If any of the registers accessed are non-constant, conservatively assume
287 // the instruction is not rematerializable.
288 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
289 const MachineOperand &MO = MI->getOperand(i);
290 if (!MO.isReg()) continue;
291 unsigned Reg = MO.getReg();
295 // Check for a well-behaved physical register.
296 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
298 // If the physreg has no defs anywhere, it's just an ambient register
299 // and we can freely move its uses. Alternatively, if it's allocatable,
300 // it could get allocated to something with a def during allocation.
301 if (!MRI.def_empty(Reg))
303 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
304 if (AllocatableRegs.test(Reg))
306 // Check for a def among the register's aliases too.
307 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
308 unsigned AliasReg = *Alias;
309 if (!MRI.def_empty(AliasReg))
311 if (AllocatableRegs.test(AliasReg))
315 // A physreg def. We can't remat it.
321 // Only allow one virtual-register def, and that in the first operand.
322 if (MO.isDef() != (i == 0))
325 // For the def, it should be the only def of that register.
326 if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() ||
330 // Don't allow any virtual-register uses. Rematting an instruction with
331 // virtual register uses would length the live ranges of the uses, which
332 // is not necessarily a good idea, certainly not "trivial".
337 // Everything checked out.
341 /// isSchedulingBoundary - Test if the given instruction should be
342 /// considered a scheduling boundary. This primarily includes labels
344 bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
345 const MachineBasicBlock *MBB,
346 const MachineFunction &MF) const{
347 // Terminators and labels can't be scheduled around.
348 if (MI->getDesc().isTerminator() || MI->isLabel())
351 // Don't attempt to schedule around any instruction that defines
352 // a stack-oriented pointer, as it's unlikely to be profitable. This
353 // saves compile time, because it doesn't require every single
354 // stack slot reference to depend on the instruction that does the
356 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
357 if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
363 // Default implementation of CreateTargetPostRAHazardRecognizer.
364 ScheduleHazardRecognizer *TargetInstrInfoImpl::
365 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
366 return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II);