1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
25 // commuteInstruction - The default implementation of this method just exchanges
26 // the two operands returned by findCommutedOpIndices.
27 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
29 const TargetInstrDesc &TID = MI->getDesc();
30 bool HasDef = TID.getNumDefs();
31 if (HasDef && !MI->getOperand(0).isReg())
32 // No idea how to commute this instruction. Target should implement its own.
35 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
37 raw_string_ostream Msg(msg);
38 Msg << "Don't know how to commute: " << *MI;
39 llvm_report_error(Msg.str());
42 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
43 "This only knows how to commute register operands so far");
44 unsigned Reg1 = MI->getOperand(Idx1).getReg();
45 unsigned Reg2 = MI->getOperand(Idx2).getReg();
46 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
47 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
48 bool ChangeReg0 = false;
49 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
50 // Must be two address instruction!
51 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
52 "Expecting a two-address instruction!");
58 // Create a new instruction.
59 unsigned Reg0 = HasDef
60 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
61 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
62 MachineFunction &MF = *MI->getParent()->getParent();
64 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
65 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
66 .addReg(Reg2, getKillRegState(Reg2IsKill))
67 .addReg(Reg1, getKillRegState(Reg2IsKill));
69 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
70 .addReg(Reg2, getKillRegState(Reg2IsKill))
71 .addReg(Reg1, getKillRegState(Reg2IsKill));
75 MI->getOperand(0).setReg(Reg2);
76 MI->getOperand(Idx2).setReg(Reg1);
77 MI->getOperand(Idx1).setReg(Reg2);
78 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
79 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
83 /// findCommutedOpIndices - If specified MI is commutable, return the two
84 /// operand indices that would swap value. Return true if the instruction
85 /// is not in a form which this routine understands.
86 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
88 unsigned &SrcOpIdx2) const {
89 const TargetInstrDesc &TID = MI->getDesc();
90 if (!TID.isCommutable())
92 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
93 // is not true, then the target must implement this.
94 SrcOpIdx1 = TID.getNumDefs();
95 SrcOpIdx2 = SrcOpIdx1 + 1;
96 if (!MI->getOperand(SrcOpIdx1).isReg() ||
97 !MI->getOperand(SrcOpIdx2).isReg())
104 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
105 const SmallVectorImpl<MachineOperand> &Pred) const {
106 bool MadeChange = false;
107 const TargetInstrDesc &TID = MI->getDesc();
108 if (!TID.isPredicable())
111 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
112 if (TID.OpInfo[i].isPredicate()) {
113 MachineOperand &MO = MI->getOperand(i);
115 MO.setReg(Pred[j].getReg());
117 } else if (MO.isImm()) {
118 MO.setImm(Pred[j].getImm());
120 } else if (MO.isMBB()) {
121 MO.setMBB(Pred[j].getMBB());
130 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator I,
134 const MachineInstr *Orig) const {
135 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
136 MachineOperand &MO = MI->getOperand(0);
138 MO.setSubReg(SubIdx);
142 bool TargetInstrInfoImpl::isDeadInstruction(const MachineInstr *MI) const {
143 const TargetInstrDesc &TID = MI->getDesc();
144 if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
145 TID.isCall() || TID.isBarrier() || TID.isReturn() ||
146 TID.hasUnmodeledSideEffects())
148 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
149 const MachineOperand &MO = MI->getOperand(i);
150 if (!MO.isReg() || !MO.getReg())
152 if (MO.isDef() && !MO.isDead())
154 if (MO.isUse() && MO.isKill())
155 // FIXME: We can't remove kill markers or else the scavenger will assert.
156 // An alternative is to add a ADD pseudo instruction to replace kill
164 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
166 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
168 const MachineBasicBlock &MBB = *MBBI;
169 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
171 FnSize += GetInstSizeInBytes(I);
176 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
177 /// slot into the specified machine instruction for the specified operand(s).
178 /// If this is possible, a new instruction is returned with the specified
179 /// operand folded, otherwise NULL is returned. The client is responsible for
180 /// removing the old instruction and adding the new one in the instruction
183 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
185 const SmallVectorImpl<unsigned> &Ops,
186 int FrameIndex) const {
188 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
189 if (MI->getOperand(Ops[i]).isDef())
190 Flags |= MachineMemOperand::MOStore;
192 Flags |= MachineMemOperand::MOLoad;
194 // Ask the target to do the actual folding.
195 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
196 if (!NewMI) return 0;
198 assert((!(Flags & MachineMemOperand::MOStore) ||
199 NewMI->getDesc().mayStore()) &&
200 "Folded a def to a non-store!");
201 assert((!(Flags & MachineMemOperand::MOLoad) ||
202 NewMI->getDesc().mayLoad()) &&
203 "Folded a use to a non-load!");
204 const MachineFrameInfo &MFI = *MF.getFrameInfo();
205 assert(MFI.getObjectOffset(FrameIndex) != -1);
206 MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FrameIndex),
208 MFI.getObjectOffset(FrameIndex),
209 MFI.getObjectSize(FrameIndex),
210 MFI.getObjectAlignment(FrameIndex));
211 NewMI->addMemOperand(MF, MMO);
216 /// foldMemoryOperand - Same as the previous version except it allows folding
217 /// of any load and store from / to any address, not just from a specific
220 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
222 const SmallVectorImpl<unsigned> &Ops,
223 MachineInstr* LoadMI) const {
224 assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
226 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
227 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
230 // Ask the target to do the actual folding.
231 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
232 if (!NewMI) return 0;
234 // Copy the memoperands from the load to the folded instruction.
235 for (std::list<MachineMemOperand>::iterator I = LoadMI->memoperands_begin(),
236 E = LoadMI->memoperands_end(); I != E; ++I)
237 NewMI->addMemOperand(MF, *I);