1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 // commuteInstruction - The default implementation of this method just exchanges
30 // the two operands returned by findCommutedOpIndices.
31 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
33 const TargetInstrDesc &TID = MI->getDesc();
34 bool HasDef = TID.getNumDefs();
35 if (HasDef && !MI->getOperand(0).isReg())
36 // No idea how to commute this instruction. Target should implement its own.
39 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
41 raw_string_ostream Msg(msg);
42 Msg << "Don't know how to commute: " << *MI;
43 llvm_report_error(Msg.str());
46 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
47 "This only knows how to commute register operands so far");
48 unsigned Reg1 = MI->getOperand(Idx1).getReg();
49 unsigned Reg2 = MI->getOperand(Idx2).getReg();
50 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
51 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
52 bool ChangeReg0 = false;
53 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
54 // Must be two address instruction!
55 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
56 "Expecting a two-address instruction!");
62 // Create a new instruction.
63 unsigned Reg0 = HasDef
64 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
65 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
66 MachineFunction &MF = *MI->getParent()->getParent();
68 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
69 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
70 .addReg(Reg2, getKillRegState(Reg2IsKill))
71 .addReg(Reg1, getKillRegState(Reg2IsKill));
73 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
74 .addReg(Reg2, getKillRegState(Reg2IsKill))
75 .addReg(Reg1, getKillRegState(Reg2IsKill));
79 MI->getOperand(0).setReg(Reg2);
80 MI->getOperand(Idx2).setReg(Reg1);
81 MI->getOperand(Idx1).setReg(Reg2);
82 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
83 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
87 /// findCommutedOpIndices - If specified MI is commutable, return the two
88 /// operand indices that would swap value. Return true if the instruction
89 /// is not in a form which this routine understands.
90 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
92 unsigned &SrcOpIdx2) const {
93 const TargetInstrDesc &TID = MI->getDesc();
94 if (!TID.isCommutable())
96 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
97 // is not true, then the target must implement this.
98 SrcOpIdx1 = TID.getNumDefs();
99 SrcOpIdx2 = SrcOpIdx1 + 1;
100 if (!MI->getOperand(SrcOpIdx1).isReg() ||
101 !MI->getOperand(SrcOpIdx2).isReg())
108 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
109 const SmallVectorImpl<MachineOperand> &Pred) const {
110 bool MadeChange = false;
111 const TargetInstrDesc &TID = MI->getDesc();
112 if (!TID.isPredicable())
115 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
116 if (TID.OpInfo[i].isPredicate()) {
117 MachineOperand &MO = MI->getOperand(i);
119 MO.setReg(Pred[j].getReg());
121 } else if (MO.isImm()) {
122 MO.setImm(Pred[j].getImm());
124 } else if (MO.isMBB()) {
125 MO.setMBB(Pred[j].getMBB());
134 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator I,
138 const MachineInstr *Orig) const {
139 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
140 MachineOperand &MO = MI->getOperand(0);
142 MO.setSubReg(SubIdx);
147 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
149 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
151 const MachineBasicBlock &MBB = *MBBI;
152 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
154 FnSize += GetInstSizeInBytes(I);
159 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
160 /// slot into the specified machine instruction for the specified operand(s).
161 /// If this is possible, a new instruction is returned with the specified
162 /// operand folded, otherwise NULL is returned. The client is responsible for
163 /// removing the old instruction and adding the new one in the instruction
166 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
168 const SmallVectorImpl<unsigned> &Ops,
169 int FrameIndex) const {
171 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
172 if (MI->getOperand(Ops[i]).isDef())
173 Flags |= MachineMemOperand::MOStore;
175 Flags |= MachineMemOperand::MOLoad;
177 // Ask the target to do the actual folding.
178 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
179 if (!NewMI) return 0;
181 assert((!(Flags & MachineMemOperand::MOStore) ||
182 NewMI->getDesc().mayStore()) &&
183 "Folded a def to a non-store!");
184 assert((!(Flags & MachineMemOperand::MOLoad) ||
185 NewMI->getDesc().mayLoad()) &&
186 "Folded a use to a non-load!");
187 const MachineFrameInfo &MFI = *MF.getFrameInfo();
188 assert(MFI.getObjectOffset(FrameIndex) != -1);
189 MachineMemOperand *MMO =
190 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex),
192 MFI.getObjectSize(FrameIndex),
193 MFI.getObjectAlignment(FrameIndex));
194 NewMI->addMemOperand(MF, MMO);
199 /// foldMemoryOperand - Same as the previous version except it allows folding
200 /// of any load and store from / to any address, not just from a specific
203 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
205 const SmallVectorImpl<unsigned> &Ops,
206 MachineInstr* LoadMI) const {
207 assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
209 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
210 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
213 // Ask the target to do the actual folding.
214 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
215 if (!NewMI) return 0;
217 // Copy the memoperands from the load to the folded instruction.
218 NewMI->setMemRefs(LoadMI->memoperands_begin(),
219 LoadMI->memoperands_end());
225 TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(const MachineInstr *
229 const MachineFunction &MF = *MI->getParent()->getParent();
230 const MachineRegisterInfo &MRI = MF.getRegInfo();
231 const TargetMachine &TM = MF.getTarget();
232 const TargetInstrInfo &TII = *TM.getInstrInfo();
233 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
235 // A load from a fixed stack slot can be rematerialized. This may be
236 // redundant with subsequent checks, but it's target-independent,
237 // simple, and a common case.
239 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
240 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
243 const TargetInstrDesc &TID = MI->getDesc();
245 // Avoid instructions obviously unsafe for remat.
246 if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable() ||
250 // Avoid instructions which load from potentially varying memory.
251 if (TID.mayLoad() && !MI->isInvariantLoad(AA))
254 // If any of the registers accessed are non-constant, conservatively assume
255 // the instruction is not rematerializable.
256 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
257 const MachineOperand &MO = MI->getOperand(i);
258 if (!MO.isReg()) continue;
259 unsigned Reg = MO.getReg();
263 // Check for a well-behaved physical register.
264 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
266 // If the physreg has no defs anywhere, it's just an ambient register
267 // and we can freely move its uses. Alternatively, if it's allocatable,
268 // it could get allocated to something with a def during allocation.
269 if (!MRI.def_empty(Reg))
271 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
272 if (AllocatableRegs.test(Reg))
274 // Check for a def among the register's aliases too.
275 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
276 unsigned AliasReg = *Alias;
277 if (!MRI.def_empty(AliasReg))
279 if (AllocatableRegs.test(AliasReg))
283 // A physreg def. We can't remat it.
289 // Only allow one virtual-register def, and that in the first operand.
290 if (MO.isDef() != (i == 0))
293 // For the def, it should be the only def of that register.
294 if (MO.isDef() && (next(MRI.def_begin(Reg)) != MRI.def_end() ||
298 // Don't allow any virtual-register uses. Rematting an instruction with
299 // virtual register uses would length the live ranges of the uses, which
300 // is not necessarily a good idea, certainly not "trivial".
305 // Everything checked out.