1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 // commuteInstruction - The default implementation of this method just exchanges
23 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
25 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
26 "This only knows how to commute register operands so far");
27 unsigned Reg1 = MI->getOperand(1).getReg();
28 unsigned Reg2 = MI->getOperand(2).getReg();
29 bool Reg1IsKill = MI->getOperand(1).isKill();
30 bool Reg2IsKill = MI->getOperand(2).isKill();
31 bool ChangeReg0 = false;
32 if (MI->getOperand(0).getReg() == Reg1) {
33 // Must be two address instruction!
34 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
35 "Expecting a two-address instruction!");
41 // Create a new instruction.
42 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
43 bool Reg0IsDead = MI->getOperand(0).isDead();
44 MachineFunction &MF = *MI->getParent()->getParent();
45 return BuildMI(MF, MI->getDesc())
46 .addReg(Reg0, true, false, false, Reg0IsDead)
47 .addReg(Reg2, false, false, Reg2IsKill)
48 .addReg(Reg1, false, false, Reg1IsKill);
52 MI->getOperand(0).setReg(Reg2);
53 MI->getOperand(2).setReg(Reg1);
54 MI->getOperand(1).setReg(Reg2);
55 MI->getOperand(2).setIsKill(Reg1IsKill);
56 MI->getOperand(1).setIsKill(Reg2IsKill);
60 /// CommuteChangesDestination - Return true if commuting the specified
61 /// instruction will also changes the destination operand. Also return the
62 /// current operand index of the would be new destination register by
63 /// reference. This can happen when the commutable instruction is also a
64 /// two-address instruction.
65 bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
66 unsigned &OpIdx) const{
67 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
68 "This only knows how to commute register operands so far");
69 if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
70 // Must be two address instruction!
71 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
72 "Expecting a two-address instruction!");
80 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
81 const SmallVectorImpl<MachineOperand> &Pred) const {
82 bool MadeChange = false;
83 const TargetInstrDesc &TID = MI->getDesc();
84 if (!TID.isPredicable())
87 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
88 if (TID.OpInfo[i].isPredicate()) {
89 MachineOperand &MO = MI->getOperand(i);
90 if (MO.isRegister()) {
91 MO.setReg(Pred[j].getReg());
93 } else if (MO.isImmediate()) {
94 MO.setImm(Pred[j].getImm());
96 } else if (MO.isMachineBasicBlock()) {
97 MO.setMBB(Pred[j].getMBB());
106 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator I,
109 const MachineInstr *Orig) const {
110 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
111 MI->getOperand(0).setReg(DestReg);
116 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
118 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
120 const MachineBasicBlock &MBB = *MBBI;
121 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
123 FnSize += GetInstSizeInBytes(I);