1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 // commuteInstruction - The default implementation of this method just exchanges
22 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
24 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
25 "This only knows how to commute register operands so far");
26 unsigned Reg1 = MI->getOperand(1).getReg();
27 unsigned Reg2 = MI->getOperand(2).getReg();
28 bool Reg1IsKill = MI->getOperand(1).isKill();
29 bool Reg2IsKill = MI->getOperand(2).isKill();
30 bool ChangeReg0 = false;
31 if (MI->getOperand(0).getReg() == Reg1) {
32 // Must be two address instruction!
33 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
34 "Expecting a two-address instruction!");
40 // Create a new instruction.
41 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
42 bool Reg0IsDead = MI->getOperand(0).isDead();
43 return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
44 .addReg(Reg2, false, false, Reg2IsKill)
45 .addReg(Reg1, false, false, Reg1IsKill);
49 MI->getOperand(0).setReg(Reg2);
50 MI->getOperand(2).setReg(Reg1);
51 MI->getOperand(1).setReg(Reg2);
52 MI->getOperand(2).setIsKill(Reg1IsKill);
53 MI->getOperand(1).setIsKill(Reg2IsKill);
57 /// CommuteChangesDestination - Return true if commuting the specified
58 /// instruction will also changes the destination operand. Also return the
59 /// current operand index of the would be new destination register by
60 /// reference. This can happen when the commutable instruction is also a
61 /// two-address instruction.
62 bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
63 unsigned &OpIdx) const{
64 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
65 "This only knows how to commute register operands so far");
66 if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
67 // Must be two address instruction!
68 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
69 "Expecting a two-address instruction!");
77 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
78 const std::vector<MachineOperand> &Pred) const {
79 bool MadeChange = false;
80 const TargetInstrDesc &TID = MI->getDesc();
81 if (!TID.isPredicable())
84 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
85 if (TID.OpInfo[i].isPredicate()) {
86 MachineOperand &MO = MI->getOperand(i);
88 MO.setReg(Pred[j].getReg());
90 } else if (MO.isImm()) {
91 MO.setImm(Pred[j].getImm());
93 } else if (MO.isMBB()) {
94 MO.setMBB(Pred[j].getMBB());
103 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator I,
106 const MachineInstr *Orig) const {
107 MachineInstr *MI = Orig->clone();
108 MI->getOperand(0).setReg(DestReg);
113 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
115 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
117 const MachineBasicBlock &MBB = *MBBI;
118 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
119 FnSize += GetInstSizeInBytes(I);