1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
19 // commuteInstruction - The default implementation of this method just exchanges
21 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
22 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
23 "This only knows how to commute register operands so far");
24 unsigned Reg1 = MI->getOperand(1).getReg();
25 unsigned Reg2 = MI->getOperand(2).getReg();
26 bool Reg1IsKill = MI->getOperand(1).isKill();
27 bool Reg2IsKill = MI->getOperand(2).isKill();
28 if (MI->getOperand(0).getReg() == Reg1) {
29 // Must be two address instruction!
30 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
31 "Expecting a two-address instruction!");
33 MI->getOperand(0).setReg(Reg2);
35 MI->getOperand(2).setReg(Reg1);
36 MI->getOperand(1).setReg(Reg2);
37 MI->getOperand(2).setIsKill(Reg1IsKill);
38 MI->getOperand(1).setIsKill(Reg2IsKill);
42 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
43 const std::vector<MachineOperand> &Pred) const {
44 bool MadeChange = false;
45 const TargetInstrDesc &TID = MI->getDesc();
46 if (!TID.isPredicable())
49 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
50 if (TID.OpInfo[i].isPredicate()) {
51 MachineOperand &MO = MI->getOperand(i);
53 MO.setReg(Pred[j].getReg());
55 } else if (MO.isImm()) {
56 MO.setImm(Pred[j].getImm());
58 } else if (MO.isMBB()) {
59 MO.setMBB(Pred[j].getMBB());