1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
26 // commuteInstruction - The default implementation of this method just exchanges
27 // the two operands returned by findCommutedOpIndices.
28 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
30 const TargetInstrDesc &TID = MI->getDesc();
31 bool HasDef = TID.getNumDefs();
32 if (HasDef && !MI->getOperand(0).isReg())
33 // No idea how to commute this instruction. Target should implement its own.
36 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
38 raw_string_ostream Msg(msg);
39 Msg << "Don't know how to commute: " << *MI;
40 llvm_report_error(Msg.str());
43 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
44 "This only knows how to commute register operands so far");
45 unsigned Reg1 = MI->getOperand(Idx1).getReg();
46 unsigned Reg2 = MI->getOperand(Idx2).getReg();
47 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
48 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
49 bool ChangeReg0 = false;
50 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
51 // Must be two address instruction!
52 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
53 "Expecting a two-address instruction!");
59 // Create a new instruction.
60 unsigned Reg0 = HasDef
61 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
62 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
63 MachineFunction &MF = *MI->getParent()->getParent();
65 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
66 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
67 .addReg(Reg2, getKillRegState(Reg2IsKill))
68 .addReg(Reg1, getKillRegState(Reg2IsKill));
70 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
71 .addReg(Reg2, getKillRegState(Reg2IsKill))
72 .addReg(Reg1, getKillRegState(Reg2IsKill));
76 MI->getOperand(0).setReg(Reg2);
77 MI->getOperand(Idx2).setReg(Reg1);
78 MI->getOperand(Idx1).setReg(Reg2);
79 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
80 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
84 /// findCommutedOpIndices - If specified MI is commutable, return the two
85 /// operand indices that would swap value. Return true if the instruction
86 /// is not in a form which this routine understands.
87 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
89 unsigned &SrcOpIdx2) const {
90 const TargetInstrDesc &TID = MI->getDesc();
91 if (!TID.isCommutable())
93 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
94 // is not true, then the target must implement this.
95 SrcOpIdx1 = TID.getNumDefs();
96 SrcOpIdx2 = SrcOpIdx1 + 1;
97 if (!MI->getOperand(SrcOpIdx1).isReg() ||
98 !MI->getOperand(SrcOpIdx2).isReg())
105 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
106 const SmallVectorImpl<MachineOperand> &Pred) const {
107 bool MadeChange = false;
108 const TargetInstrDesc &TID = MI->getDesc();
109 if (!TID.isPredicable())
112 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
113 if (TID.OpInfo[i].isPredicate()) {
114 MachineOperand &MO = MI->getOperand(i);
116 MO.setReg(Pred[j].getReg());
118 } else if (MO.isImm()) {
119 MO.setImm(Pred[j].getImm());
121 } else if (MO.isMBB()) {
122 MO.setMBB(Pred[j].getMBB());
131 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator I,
135 const MachineInstr *Orig) const {
136 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
137 MachineOperand &MO = MI->getOperand(0);
139 MO.setSubReg(SubIdx);
143 bool TargetInstrInfoImpl::isDeadInstruction(const MachineInstr *MI) const {
144 const TargetInstrDesc &TID = MI->getDesc();
145 if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
146 TID.isCall() || TID.isBarrier() || TID.isReturn() ||
147 TID.hasUnmodeledSideEffects())
149 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
150 const MachineOperand &MO = MI->getOperand(i);
151 if (!MO.isReg() || !MO.getReg())
153 if (MO.isDef() && !MO.isDead())
155 if (MO.isUse() && MO.isKill())
156 // FIXME: We can't remove kill markers or else the scavenger will assert.
157 // An alternative is to add a ADD pseudo instruction to replace kill
165 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
167 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
169 const MachineBasicBlock &MBB = *MBBI;
170 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
172 FnSize += GetInstSizeInBytes(I);
177 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
178 /// slot into the specified machine instruction for the specified operand(s).
179 /// If this is possible, a new instruction is returned with the specified
180 /// operand folded, otherwise NULL is returned. The client is responsible for
181 /// removing the old instruction and adding the new one in the instruction
184 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
186 const SmallVectorImpl<unsigned> &Ops,
187 int FrameIndex) const {
189 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
190 if (MI->getOperand(Ops[i]).isDef())
191 Flags |= MachineMemOperand::MOStore;
193 Flags |= MachineMemOperand::MOLoad;
195 // Ask the target to do the actual folding.
196 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
197 if (!NewMI) return 0;
199 assert((!(Flags & MachineMemOperand::MOStore) ||
200 NewMI->getDesc().mayStore()) &&
201 "Folded a def to a non-store!");
202 assert((!(Flags & MachineMemOperand::MOLoad) ||
203 NewMI->getDesc().mayLoad()) &&
204 "Folded a use to a non-load!");
205 const MachineFrameInfo &MFI = *MF.getFrameInfo();
206 assert(MFI.getObjectOffset(FrameIndex) != -1);
207 MachineMemOperand *MMO =
208 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex),
210 MFI.getObjectSize(FrameIndex),
211 MFI.getObjectAlignment(FrameIndex));
212 NewMI->addMemOperand(MF, MMO);
217 /// foldMemoryOperand - Same as the previous version except it allows folding
218 /// of any load and store from / to any address, not just from a specific
221 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
223 const SmallVectorImpl<unsigned> &Ops,
224 MachineInstr* LoadMI) const {
225 assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
227 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
228 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
231 // Ask the target to do the actual folding.
232 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
233 if (!NewMI) return 0;
235 // Copy the memoperands from the load to the folded instruction.
236 NewMI->setMemRefs(LoadMI->memoperands_begin(),
237 LoadMI->memoperands_end());