1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetLowering.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
33 static cl::opt<bool> DisableHazardRecognizer(
34 "disable-sched-hazard", cl::Hidden, cl::init(false),
35 cl::desc("Disable hazard detection during preRA scheduling"));
37 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
38 /// after it, replacing it with an unconditional branch to NewDest.
40 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
41 MachineBasicBlock *NewDest) const {
42 MachineBasicBlock *MBB = Tail->getParent();
44 // Remove all the old successors of MBB from the CFG.
45 while (!MBB->succ_empty())
46 MBB->removeSuccessor(MBB->succ_begin());
48 // Remove all the dead instructions from the end of MBB.
49 MBB->erase(Tail, MBB->end());
51 // If MBB isn't immediately before MBB, insert a branch to it.
52 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
53 InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
55 MBB->addSuccessor(NewDest);
58 // commuteInstruction - The default implementation of this method just exchanges
59 // the two operands returned by findCommutedOpIndices.
60 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
62 const MCInstrDesc &MCID = MI->getDesc();
63 bool HasDef = MCID.getNumDefs();
64 if (HasDef && !MI->getOperand(0).isReg())
65 // No idea how to commute this instruction. Target should implement its own.
68 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
70 raw_string_ostream Msg(msg);
71 Msg << "Don't know how to commute: " << *MI;
72 report_fatal_error(Msg.str());
75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
76 "This only knows how to commute register operands so far");
77 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
78 unsigned Reg1 = MI->getOperand(Idx1).getReg();
79 unsigned Reg2 = MI->getOperand(Idx2).getReg();
80 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
81 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
82 // If destination is tied to either of the commuted source register, then
83 // it must be updated.
84 if (HasDef && Reg0 == Reg1 &&
85 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
88 } else if (HasDef && Reg0 == Reg2 &&
89 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
95 // Create a new instruction.
96 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
97 MachineFunction &MF = *MI->getParent()->getParent();
99 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
100 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
101 .addReg(Reg2, getKillRegState(Reg2IsKill))
102 .addReg(Reg1, getKillRegState(Reg2IsKill));
104 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
105 .addReg(Reg2, getKillRegState(Reg2IsKill))
106 .addReg(Reg1, getKillRegState(Reg2IsKill));
110 MI->getOperand(0).setReg(Reg0);
111 MI->getOperand(Idx2).setReg(Reg1);
112 MI->getOperand(Idx1).setReg(Reg2);
113 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
114 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
118 /// findCommutedOpIndices - If specified MI is commutable, return the two
119 /// operand indices that would swap value. Return true if the instruction
120 /// is not in a form which this routine understands.
121 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
123 unsigned &SrcOpIdx2) const {
124 assert(!MI->isBundle() &&
125 "TargetInstrInfoImpl::findCommutedOpIndices() can't handle bundles");
127 const MCInstrDesc &MCID = MI->getDesc();
128 if (!MCID.isCommutable())
130 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
131 // is not true, then the target must implement this.
132 SrcOpIdx1 = MCID.getNumDefs();
133 SrcOpIdx2 = SrcOpIdx1 + 1;
134 if (!MI->getOperand(SrcOpIdx1).isReg() ||
135 !MI->getOperand(SrcOpIdx2).isReg())
143 TargetInstrInfoImpl::isUnpredicatedTerminator(const MachineInstr *MI) const {
144 if (!MI->isTerminator()) return false;
146 // Conditional branch is a special case.
147 if (MI->isBranch() && !MI->isBarrier())
149 if (!MI->isPredicable())
151 return !isPredicated(MI);
155 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
156 const SmallVectorImpl<MachineOperand> &Pred) const {
157 bool MadeChange = false;
159 assert(!MI->isBundle() &&
160 "TargetInstrInfoImpl::PredicateInstruction() can't handle bundles");
162 const MCInstrDesc &MCID = MI->getDesc();
163 if (!MI->isPredicable())
166 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 if (MCID.OpInfo[i].isPredicate()) {
168 MachineOperand &MO = MI->getOperand(i);
170 MO.setReg(Pred[j].getReg());
172 } else if (MO.isImm()) {
173 MO.setImm(Pred[j].getImm());
175 } else if (MO.isMBB()) {
176 MO.setMBB(Pred[j].getMBB());
185 bool TargetInstrInfoImpl::hasLoadFromStackSlot(const MachineInstr *MI,
186 const MachineMemOperand *&MMO,
187 int &FrameIndex) const {
188 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
189 oe = MI->memoperands_end();
192 if ((*o)->isLoad() && (*o)->getValue())
193 if (const FixedStackPseudoSourceValue *Value =
194 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
195 FrameIndex = Value->getFrameIndex();
203 bool TargetInstrInfoImpl::hasStoreToStackSlot(const MachineInstr *MI,
204 const MachineMemOperand *&MMO,
205 int &FrameIndex) const {
206 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
207 oe = MI->memoperands_end();
210 if ((*o)->isStore() && (*o)->getValue())
211 if (const FixedStackPseudoSourceValue *Value =
212 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
213 FrameIndex = Value->getFrameIndex();
221 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
222 MachineBasicBlock::iterator I,
225 const MachineInstr *Orig,
226 const TargetRegisterInfo &TRI) const {
227 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
228 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
233 TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
234 const MachineInstr *MI1,
235 const MachineRegisterInfo *MRI) const {
236 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
239 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
240 MachineFunction &MF) const {
241 assert(!Orig->isNotDuplicable() &&
242 "Instruction cannot be duplicated");
243 return MF.CloneMachineInstr(Orig);
246 // If the COPY instruction in MI can be folded to a stack operation, return
247 // the register class to use.
248 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
250 assert(MI->isCopy() && "MI must be a COPY instruction");
251 if (MI->getNumOperands() != 2)
253 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
255 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
256 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
258 if (FoldOp.getSubReg() || LiveOp.getSubReg())
261 unsigned FoldReg = FoldOp.getReg();
262 unsigned LiveReg = LiveOp.getReg();
264 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
265 "Cannot fold physregs");
267 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
268 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
270 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
271 return RC->contains(LiveOp.getReg()) ? RC : 0;
273 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
276 // FIXME: Allow folding when register classes are memory compatible.
280 bool TargetInstrInfoImpl::
281 canFoldMemoryOperand(const MachineInstr *MI,
282 const SmallVectorImpl<unsigned> &Ops) const {
283 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
286 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
287 /// slot into the specified machine instruction for the specified operand(s).
288 /// If this is possible, a new instruction is returned with the specified
289 /// operand folded, otherwise NULL is returned. The client is responsible for
290 /// removing the old instruction and adding the new one in the instruction
293 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
294 const SmallVectorImpl<unsigned> &Ops,
297 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
298 if (MI->getOperand(Ops[i]).isDef())
299 Flags |= MachineMemOperand::MOStore;
301 Flags |= MachineMemOperand::MOLoad;
303 MachineBasicBlock *MBB = MI->getParent();
304 assert(MBB && "foldMemoryOperand needs an inserted instruction");
305 MachineFunction &MF = *MBB->getParent();
307 // Ask the target to do the actual folding.
308 if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
309 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
310 assert((!(Flags & MachineMemOperand::MOStore) ||
311 NewMI->mayStore()) &&
312 "Folded a def to a non-store!");
313 assert((!(Flags & MachineMemOperand::MOLoad) ||
315 "Folded a use to a non-load!");
316 const MachineFrameInfo &MFI = *MF.getFrameInfo();
317 assert(MFI.getObjectOffset(FI) != -1);
318 MachineMemOperand *MMO =
319 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
320 Flags, MFI.getObjectSize(FI),
321 MFI.getObjectAlignment(FI));
322 NewMI->addMemOperand(MF, MMO);
324 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
325 return MBB->insert(MI, NewMI);
328 // Straight COPY may fold as load/store.
329 if (!MI->isCopy() || Ops.size() != 1)
332 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
336 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
337 MachineBasicBlock::iterator Pos = MI;
338 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
340 if (Flags == MachineMemOperand::MOStore)
341 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
343 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
347 /// foldMemoryOperand - Same as the previous version except it allows folding
348 /// of any load and store from / to any address, not just from a specific
351 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
352 const SmallVectorImpl<unsigned> &Ops,
353 MachineInstr* LoadMI) const {
354 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
356 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
357 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
359 MachineBasicBlock &MBB = *MI->getParent();
360 MachineFunction &MF = *MBB.getParent();
362 // Ask the target to do the actual folding.
363 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
364 if (!NewMI) return 0;
366 NewMI = MBB.insert(MI, NewMI);
368 // Copy the memoperands from the load to the folded instruction.
369 NewMI->setMemRefs(LoadMI->memoperands_begin(),
370 LoadMI->memoperands_end());
375 bool TargetInstrInfo::
376 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
377 AliasAnalysis *AA) const {
378 const MachineFunction &MF = *MI->getParent()->getParent();
379 const MachineRegisterInfo &MRI = MF.getRegInfo();
380 const TargetMachine &TM = MF.getTarget();
381 const TargetInstrInfo &TII = *TM.getInstrInfo();
382 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
384 // Remat clients assume operand 0 is the defined register.
385 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
387 unsigned DefReg = MI->getOperand(0).getReg();
389 // A sub-register definition can only be rematerialized if the instruction
390 // doesn't read the other parts of the register. Otherwise it is really a
391 // read-modify-write operation on the full virtual register which cannot be
393 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
394 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
397 // A load from a fixed stack slot can be rematerialized. This may be
398 // redundant with subsequent checks, but it's target-independent,
399 // simple, and a common case.
401 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
402 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
405 // Avoid instructions obviously unsafe for remat.
406 if (MI->isNotDuplicable() || MI->mayStore() ||
407 MI->hasUnmodeledSideEffects())
410 // Don't remat inline asm. We have no idea how expensive it is
411 // even if it's side effect free.
412 if (MI->isInlineAsm())
415 // Avoid instructions which load from potentially varying memory.
416 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
419 // If any of the registers accessed are non-constant, conservatively assume
420 // the instruction is not rematerializable.
421 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
422 const MachineOperand &MO = MI->getOperand(i);
423 if (!MO.isReg()) continue;
424 unsigned Reg = MO.getReg();
428 // Check for a well-behaved physical register.
429 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
431 // If the physreg has no defs anywhere, it's just an ambient register
432 // and we can freely move its uses. Alternatively, if it's allocatable,
433 // it could get allocated to something with a def during allocation.
434 if (!MRI.def_empty(Reg))
436 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
437 if (AllocatableRegs.test(Reg))
439 // Check for a def among the register's aliases too.
440 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
441 unsigned AliasReg = *Alias;
442 if (!MRI.def_empty(AliasReg))
444 if (AllocatableRegs.test(AliasReg))
448 // A physreg def. We can't remat it.
454 // Only allow one virtual-register def. There may be multiple defs of the
455 // same virtual register, though.
456 if (MO.isDef() && Reg != DefReg)
459 // Don't allow any virtual-register uses. Rematting an instruction with
460 // virtual register uses would length the live ranges of the uses, which
461 // is not necessarily a good idea, certainly not "trivial".
466 // Everything checked out.
470 /// isSchedulingBoundary - Test if the given instruction should be
471 /// considered a scheduling boundary. This primarily includes labels
473 bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
474 const MachineBasicBlock *MBB,
475 const MachineFunction &MF) const{
476 // Terminators and labels can't be scheduled around.
477 if (MI->isTerminator() || MI->isLabel())
480 // Don't attempt to schedule around any instruction that defines
481 // a stack-oriented pointer, as it's unlikely to be profitable. This
482 // saves compile time, because it doesn't require every single
483 // stack slot reference to depend on the instruction that does the
485 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
486 if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
492 // Provide a global flag for disabling the PreRA hazard recognizer that targets
493 // may choose to honor.
494 bool TargetInstrInfoImpl::usePreRAHazardRecognizer() const {
495 return !DisableHazardRecognizer;
498 // Default implementation of CreateTargetRAHazardRecognizer.
499 ScheduleHazardRecognizer *TargetInstrInfoImpl::
500 CreateTargetHazardRecognizer(const TargetMachine *TM,
501 const ScheduleDAG *DAG) const {
502 // Dummy hazard recognizer allows all instructions to issue.
503 return new ScheduleHazardRecognizer();
506 // Default implementation of CreateTargetPostRAHazardRecognizer.
507 ScheduleHazardRecognizer *TargetInstrInfoImpl::
508 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
509 const ScheduleDAG *DAG) const {
510 return (ScheduleHazardRecognizer *)
511 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");