1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLoweringBase class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/IR/Mangler.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
40 /// InitLibcallNames - Set default libcall names.
42 static void InitLibcallNames(const char **Names, const Triple &TT) {
43 Names[RTLIB::SHL_I16] = "__ashlhi3";
44 Names[RTLIB::SHL_I32] = "__ashlsi3";
45 Names[RTLIB::SHL_I64] = "__ashldi3";
46 Names[RTLIB::SHL_I128] = "__ashlti3";
47 Names[RTLIB::SRL_I16] = "__lshrhi3";
48 Names[RTLIB::SRL_I32] = "__lshrsi3";
49 Names[RTLIB::SRL_I64] = "__lshrdi3";
50 Names[RTLIB::SRL_I128] = "__lshrti3";
51 Names[RTLIB::SRA_I16] = "__ashrhi3";
52 Names[RTLIB::SRA_I32] = "__ashrsi3";
53 Names[RTLIB::SRA_I64] = "__ashrdi3";
54 Names[RTLIB::SRA_I128] = "__ashrti3";
55 Names[RTLIB::MUL_I8] = "__mulqi3";
56 Names[RTLIB::MUL_I16] = "__mulhi3";
57 Names[RTLIB::MUL_I32] = "__mulsi3";
58 Names[RTLIB::MUL_I64] = "__muldi3";
59 Names[RTLIB::MUL_I128] = "__multi3";
60 Names[RTLIB::MULO_I32] = "__mulosi4";
61 Names[RTLIB::MULO_I64] = "__mulodi4";
62 Names[RTLIB::MULO_I128] = "__muloti4";
63 Names[RTLIB::SDIV_I8] = "__divqi3";
64 Names[RTLIB::SDIV_I16] = "__divhi3";
65 Names[RTLIB::SDIV_I32] = "__divsi3";
66 Names[RTLIB::SDIV_I64] = "__divdi3";
67 Names[RTLIB::SDIV_I128] = "__divti3";
68 Names[RTLIB::UDIV_I8] = "__udivqi3";
69 Names[RTLIB::UDIV_I16] = "__udivhi3";
70 Names[RTLIB::UDIV_I32] = "__udivsi3";
71 Names[RTLIB::UDIV_I64] = "__udivdi3";
72 Names[RTLIB::UDIV_I128] = "__udivti3";
73 Names[RTLIB::SREM_I8] = "__modqi3";
74 Names[RTLIB::SREM_I16] = "__modhi3";
75 Names[RTLIB::SREM_I32] = "__modsi3";
76 Names[RTLIB::SREM_I64] = "__moddi3";
77 Names[RTLIB::SREM_I128] = "__modti3";
78 Names[RTLIB::UREM_I8] = "__umodqi3";
79 Names[RTLIB::UREM_I16] = "__umodhi3";
80 Names[RTLIB::UREM_I32] = "__umodsi3";
81 Names[RTLIB::UREM_I64] = "__umoddi3";
82 Names[RTLIB::UREM_I128] = "__umodti3";
84 // These are generally not available.
85 Names[RTLIB::SDIVREM_I8] = nullptr;
86 Names[RTLIB::SDIVREM_I16] = nullptr;
87 Names[RTLIB::SDIVREM_I32] = nullptr;
88 Names[RTLIB::SDIVREM_I64] = nullptr;
89 Names[RTLIB::SDIVREM_I128] = nullptr;
90 Names[RTLIB::UDIVREM_I8] = nullptr;
91 Names[RTLIB::UDIVREM_I16] = nullptr;
92 Names[RTLIB::UDIVREM_I32] = nullptr;
93 Names[RTLIB::UDIVREM_I64] = nullptr;
94 Names[RTLIB::UDIVREM_I128] = nullptr;
96 Names[RTLIB::NEG_I32] = "__negsi2";
97 Names[RTLIB::NEG_I64] = "__negdi2";
98 Names[RTLIB::ADD_F32] = "__addsf3";
99 Names[RTLIB::ADD_F64] = "__adddf3";
100 Names[RTLIB::ADD_F80] = "__addxf3";
101 Names[RTLIB::ADD_F128] = "__addtf3";
102 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
103 Names[RTLIB::SUB_F32] = "__subsf3";
104 Names[RTLIB::SUB_F64] = "__subdf3";
105 Names[RTLIB::SUB_F80] = "__subxf3";
106 Names[RTLIB::SUB_F128] = "__subtf3";
107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
108 Names[RTLIB::MUL_F32] = "__mulsf3";
109 Names[RTLIB::MUL_F64] = "__muldf3";
110 Names[RTLIB::MUL_F80] = "__mulxf3";
111 Names[RTLIB::MUL_F128] = "__multf3";
112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
113 Names[RTLIB::DIV_F32] = "__divsf3";
114 Names[RTLIB::DIV_F64] = "__divdf3";
115 Names[RTLIB::DIV_F80] = "__divxf3";
116 Names[RTLIB::DIV_F128] = "__divtf3";
117 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
118 Names[RTLIB::REM_F32] = "fmodf";
119 Names[RTLIB::REM_F64] = "fmod";
120 Names[RTLIB::REM_F80] = "fmodl";
121 Names[RTLIB::REM_F128] = "fmodl";
122 Names[RTLIB::REM_PPCF128] = "fmodl";
123 Names[RTLIB::FMA_F32] = "fmaf";
124 Names[RTLIB::FMA_F64] = "fma";
125 Names[RTLIB::FMA_F80] = "fmal";
126 Names[RTLIB::FMA_F128] = "fmal";
127 Names[RTLIB::FMA_PPCF128] = "fmal";
128 Names[RTLIB::POWI_F32] = "__powisf2";
129 Names[RTLIB::POWI_F64] = "__powidf2";
130 Names[RTLIB::POWI_F80] = "__powixf2";
131 Names[RTLIB::POWI_F128] = "__powitf2";
132 Names[RTLIB::POWI_PPCF128] = "__powitf2";
133 Names[RTLIB::SQRT_F32] = "sqrtf";
134 Names[RTLIB::SQRT_F64] = "sqrt";
135 Names[RTLIB::SQRT_F80] = "sqrtl";
136 Names[RTLIB::SQRT_F128] = "sqrtl";
137 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
138 Names[RTLIB::LOG_F32] = "logf";
139 Names[RTLIB::LOG_F64] = "log";
140 Names[RTLIB::LOG_F80] = "logl";
141 Names[RTLIB::LOG_F128] = "logl";
142 Names[RTLIB::LOG_PPCF128] = "logl";
143 Names[RTLIB::LOG2_F32] = "log2f";
144 Names[RTLIB::LOG2_F64] = "log2";
145 Names[RTLIB::LOG2_F80] = "log2l";
146 Names[RTLIB::LOG2_F128] = "log2l";
147 Names[RTLIB::LOG2_PPCF128] = "log2l";
148 Names[RTLIB::LOG10_F32] = "log10f";
149 Names[RTLIB::LOG10_F64] = "log10";
150 Names[RTLIB::LOG10_F80] = "log10l";
151 Names[RTLIB::LOG10_F128] = "log10l";
152 Names[RTLIB::LOG10_PPCF128] = "log10l";
153 Names[RTLIB::EXP_F32] = "expf";
154 Names[RTLIB::EXP_F64] = "exp";
155 Names[RTLIB::EXP_F80] = "expl";
156 Names[RTLIB::EXP_F128] = "expl";
157 Names[RTLIB::EXP_PPCF128] = "expl";
158 Names[RTLIB::EXP2_F32] = "exp2f";
159 Names[RTLIB::EXP2_F64] = "exp2";
160 Names[RTLIB::EXP2_F80] = "exp2l";
161 Names[RTLIB::EXP2_F128] = "exp2l";
162 Names[RTLIB::EXP2_PPCF128] = "exp2l";
163 Names[RTLIB::SIN_F32] = "sinf";
164 Names[RTLIB::SIN_F64] = "sin";
165 Names[RTLIB::SIN_F80] = "sinl";
166 Names[RTLIB::SIN_F128] = "sinl";
167 Names[RTLIB::SIN_PPCF128] = "sinl";
168 Names[RTLIB::COS_F32] = "cosf";
169 Names[RTLIB::COS_F64] = "cos";
170 Names[RTLIB::COS_F80] = "cosl";
171 Names[RTLIB::COS_F128] = "cosl";
172 Names[RTLIB::COS_PPCF128] = "cosl";
173 Names[RTLIB::POW_F32] = "powf";
174 Names[RTLIB::POW_F64] = "pow";
175 Names[RTLIB::POW_F80] = "powl";
176 Names[RTLIB::POW_F128] = "powl";
177 Names[RTLIB::POW_PPCF128] = "powl";
178 Names[RTLIB::CEIL_F32] = "ceilf";
179 Names[RTLIB::CEIL_F64] = "ceil";
180 Names[RTLIB::CEIL_F80] = "ceill";
181 Names[RTLIB::CEIL_F128] = "ceill";
182 Names[RTLIB::CEIL_PPCF128] = "ceill";
183 Names[RTLIB::TRUNC_F32] = "truncf";
184 Names[RTLIB::TRUNC_F64] = "trunc";
185 Names[RTLIB::TRUNC_F80] = "truncl";
186 Names[RTLIB::TRUNC_F128] = "truncl";
187 Names[RTLIB::TRUNC_PPCF128] = "truncl";
188 Names[RTLIB::RINT_F32] = "rintf";
189 Names[RTLIB::RINT_F64] = "rint";
190 Names[RTLIB::RINT_F80] = "rintl";
191 Names[RTLIB::RINT_F128] = "rintl";
192 Names[RTLIB::RINT_PPCF128] = "rintl";
193 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
194 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
195 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
196 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
198 Names[RTLIB::ROUND_F32] = "roundf";
199 Names[RTLIB::ROUND_F64] = "round";
200 Names[RTLIB::ROUND_F80] = "roundl";
201 Names[RTLIB::ROUND_F128] = "roundl";
202 Names[RTLIB::ROUND_PPCF128] = "roundl";
203 Names[RTLIB::FLOOR_F32] = "floorf";
204 Names[RTLIB::FLOOR_F64] = "floor";
205 Names[RTLIB::FLOOR_F80] = "floorl";
206 Names[RTLIB::FLOOR_F128] = "floorl";
207 Names[RTLIB::FLOOR_PPCF128] = "floorl";
208 Names[RTLIB::ROUND_F32] = "roundf";
209 Names[RTLIB::ROUND_F64] = "round";
210 Names[RTLIB::ROUND_F80] = "roundl";
211 Names[RTLIB::ROUND_F128] = "roundl";
212 Names[RTLIB::ROUND_PPCF128] = "roundl";
213 Names[RTLIB::COPYSIGN_F32] = "copysignf";
214 Names[RTLIB::COPYSIGN_F64] = "copysign";
215 Names[RTLIB::COPYSIGN_F80] = "copysignl";
216 Names[RTLIB::COPYSIGN_F128] = "copysignl";
217 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
218 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
219 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
220 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
221 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
222 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
223 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
224 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
225 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
226 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
227 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
228 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
229 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
230 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
231 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
232 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
233 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
234 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
235 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
236 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
237 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
238 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
239 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
240 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
241 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
242 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
243 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
244 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
245 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
246 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
247 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
248 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
249 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
250 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
251 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
252 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
253 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
254 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
255 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
256 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
257 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
258 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
259 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
260 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
261 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
262 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
263 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
264 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
265 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
266 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
267 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
268 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
269 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
270 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
271 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
272 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
273 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
274 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
275 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
276 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
277 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
278 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
279 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
280 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
281 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
282 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
283 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
284 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
285 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
286 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
287 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
288 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
289 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
290 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
291 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
292 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
293 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
294 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
295 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
296 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
297 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
298 Names[RTLIB::OEQ_F32] = "__eqsf2";
299 Names[RTLIB::OEQ_F64] = "__eqdf2";
300 Names[RTLIB::OEQ_F128] = "__eqtf2";
301 Names[RTLIB::UNE_F32] = "__nesf2";
302 Names[RTLIB::UNE_F64] = "__nedf2";
303 Names[RTLIB::UNE_F128] = "__netf2";
304 Names[RTLIB::OGE_F32] = "__gesf2";
305 Names[RTLIB::OGE_F64] = "__gedf2";
306 Names[RTLIB::OGE_F128] = "__getf2";
307 Names[RTLIB::OLT_F32] = "__ltsf2";
308 Names[RTLIB::OLT_F64] = "__ltdf2";
309 Names[RTLIB::OLT_F128] = "__lttf2";
310 Names[RTLIB::OLE_F32] = "__lesf2";
311 Names[RTLIB::OLE_F64] = "__ledf2";
312 Names[RTLIB::OLE_F128] = "__letf2";
313 Names[RTLIB::OGT_F32] = "__gtsf2";
314 Names[RTLIB::OGT_F64] = "__gtdf2";
315 Names[RTLIB::OGT_F128] = "__gttf2";
316 Names[RTLIB::UO_F32] = "__unordsf2";
317 Names[RTLIB::UO_F64] = "__unorddf2";
318 Names[RTLIB::UO_F128] = "__unordtf2";
319 Names[RTLIB::O_F32] = "__unordsf2";
320 Names[RTLIB::O_F64] = "__unorddf2";
321 Names[RTLIB::O_F128] = "__unordtf2";
322 Names[RTLIB::MEMCPY] = "memcpy";
323 Names[RTLIB::MEMMOVE] = "memmove";
324 Names[RTLIB::MEMSET] = "memset";
325 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
326 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
327 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
328 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
329 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
330 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
331 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
332 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
333 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
334 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
335 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
336 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
337 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
338 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
339 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
340 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
341 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
342 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
343 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
344 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
345 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
346 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
347 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
348 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
349 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
350 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
351 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
352 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
353 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
354 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
355 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
356 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
357 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
358 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
359 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
360 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
361 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
362 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
363 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
364 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
365 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
366 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
367 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
368 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
369 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
370 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
371 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
372 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
373 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
374 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
375 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
376 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
377 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
378 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
379 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
380 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
381 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
382 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
383 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
384 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
385 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
387 if (TT.getEnvironment() == Triple::GNU) {
388 Names[RTLIB::SINCOS_F32] = "sincosf";
389 Names[RTLIB::SINCOS_F64] = "sincos";
390 Names[RTLIB::SINCOS_F80] = "sincosl";
391 Names[RTLIB::SINCOS_F128] = "sincosl";
392 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
394 // These are generally not available.
395 Names[RTLIB::SINCOS_F32] = nullptr;
396 Names[RTLIB::SINCOS_F64] = nullptr;
397 Names[RTLIB::SINCOS_F80] = nullptr;
398 Names[RTLIB::SINCOS_F128] = nullptr;
399 Names[RTLIB::SINCOS_PPCF128] = nullptr;
402 if (TT.getOS() != Triple::OpenBSD) {
403 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
405 // These are generally not available.
406 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
410 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
412 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
413 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
414 CCs[i] = CallingConv::C;
418 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
419 /// UNKNOWN_LIBCALL if there is none.
420 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
421 if (OpVT == MVT::f32) {
422 if (RetVT == MVT::f64)
423 return FPEXT_F32_F64;
424 if (RetVT == MVT::f128)
425 return FPEXT_F32_F128;
426 } else if (OpVT == MVT::f64) {
427 if (RetVT == MVT::f128)
428 return FPEXT_F64_F128;
431 return UNKNOWN_LIBCALL;
434 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
435 /// UNKNOWN_LIBCALL if there is none.
436 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
437 if (RetVT == MVT::f32) {
438 if (OpVT == MVT::f64)
439 return FPROUND_F64_F32;
440 if (OpVT == MVT::f80)
441 return FPROUND_F80_F32;
442 if (OpVT == MVT::f128)
443 return FPROUND_F128_F32;
444 if (OpVT == MVT::ppcf128)
445 return FPROUND_PPCF128_F32;
446 } else if (RetVT == MVT::f64) {
447 if (OpVT == MVT::f80)
448 return FPROUND_F80_F64;
449 if (OpVT == MVT::f128)
450 return FPROUND_F128_F64;
451 if (OpVT == MVT::ppcf128)
452 return FPROUND_PPCF128_F64;
455 return UNKNOWN_LIBCALL;
458 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
459 /// UNKNOWN_LIBCALL if there is none.
460 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
461 if (OpVT == MVT::f32) {
462 if (RetVT == MVT::i8)
463 return FPTOSINT_F32_I8;
464 if (RetVT == MVT::i16)
465 return FPTOSINT_F32_I16;
466 if (RetVT == MVT::i32)
467 return FPTOSINT_F32_I32;
468 if (RetVT == MVT::i64)
469 return FPTOSINT_F32_I64;
470 if (RetVT == MVT::i128)
471 return FPTOSINT_F32_I128;
472 } else if (OpVT == MVT::f64) {
473 if (RetVT == MVT::i8)
474 return FPTOSINT_F64_I8;
475 if (RetVT == MVT::i16)
476 return FPTOSINT_F64_I16;
477 if (RetVT == MVT::i32)
478 return FPTOSINT_F64_I32;
479 if (RetVT == MVT::i64)
480 return FPTOSINT_F64_I64;
481 if (RetVT == MVT::i128)
482 return FPTOSINT_F64_I128;
483 } else if (OpVT == MVT::f80) {
484 if (RetVT == MVT::i32)
485 return FPTOSINT_F80_I32;
486 if (RetVT == MVT::i64)
487 return FPTOSINT_F80_I64;
488 if (RetVT == MVT::i128)
489 return FPTOSINT_F80_I128;
490 } else if (OpVT == MVT::f128) {
491 if (RetVT == MVT::i32)
492 return FPTOSINT_F128_I32;
493 if (RetVT == MVT::i64)
494 return FPTOSINT_F128_I64;
495 if (RetVT == MVT::i128)
496 return FPTOSINT_F128_I128;
497 } else if (OpVT == MVT::ppcf128) {
498 if (RetVT == MVT::i32)
499 return FPTOSINT_PPCF128_I32;
500 if (RetVT == MVT::i64)
501 return FPTOSINT_PPCF128_I64;
502 if (RetVT == MVT::i128)
503 return FPTOSINT_PPCF128_I128;
505 return UNKNOWN_LIBCALL;
508 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
509 /// UNKNOWN_LIBCALL if there is none.
510 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
511 if (OpVT == MVT::f32) {
512 if (RetVT == MVT::i8)
513 return FPTOUINT_F32_I8;
514 if (RetVT == MVT::i16)
515 return FPTOUINT_F32_I16;
516 if (RetVT == MVT::i32)
517 return FPTOUINT_F32_I32;
518 if (RetVT == MVT::i64)
519 return FPTOUINT_F32_I64;
520 if (RetVT == MVT::i128)
521 return FPTOUINT_F32_I128;
522 } else if (OpVT == MVT::f64) {
523 if (RetVT == MVT::i8)
524 return FPTOUINT_F64_I8;
525 if (RetVT == MVT::i16)
526 return FPTOUINT_F64_I16;
527 if (RetVT == MVT::i32)
528 return FPTOUINT_F64_I32;
529 if (RetVT == MVT::i64)
530 return FPTOUINT_F64_I64;
531 if (RetVT == MVT::i128)
532 return FPTOUINT_F64_I128;
533 } else if (OpVT == MVT::f80) {
534 if (RetVT == MVT::i32)
535 return FPTOUINT_F80_I32;
536 if (RetVT == MVT::i64)
537 return FPTOUINT_F80_I64;
538 if (RetVT == MVT::i128)
539 return FPTOUINT_F80_I128;
540 } else if (OpVT == MVT::f128) {
541 if (RetVT == MVT::i32)
542 return FPTOUINT_F128_I32;
543 if (RetVT == MVT::i64)
544 return FPTOUINT_F128_I64;
545 if (RetVT == MVT::i128)
546 return FPTOUINT_F128_I128;
547 } else if (OpVT == MVT::ppcf128) {
548 if (RetVT == MVT::i32)
549 return FPTOUINT_PPCF128_I32;
550 if (RetVT == MVT::i64)
551 return FPTOUINT_PPCF128_I64;
552 if (RetVT == MVT::i128)
553 return FPTOUINT_PPCF128_I128;
555 return UNKNOWN_LIBCALL;
558 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
559 /// UNKNOWN_LIBCALL if there is none.
560 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
561 if (OpVT == MVT::i32) {
562 if (RetVT == MVT::f32)
563 return SINTTOFP_I32_F32;
564 if (RetVT == MVT::f64)
565 return SINTTOFP_I32_F64;
566 if (RetVT == MVT::f80)
567 return SINTTOFP_I32_F80;
568 if (RetVT == MVT::f128)
569 return SINTTOFP_I32_F128;
570 if (RetVT == MVT::ppcf128)
571 return SINTTOFP_I32_PPCF128;
572 } else if (OpVT == MVT::i64) {
573 if (RetVT == MVT::f32)
574 return SINTTOFP_I64_F32;
575 if (RetVT == MVT::f64)
576 return SINTTOFP_I64_F64;
577 if (RetVT == MVT::f80)
578 return SINTTOFP_I64_F80;
579 if (RetVT == MVT::f128)
580 return SINTTOFP_I64_F128;
581 if (RetVT == MVT::ppcf128)
582 return SINTTOFP_I64_PPCF128;
583 } else if (OpVT == MVT::i128) {
584 if (RetVT == MVT::f32)
585 return SINTTOFP_I128_F32;
586 if (RetVT == MVT::f64)
587 return SINTTOFP_I128_F64;
588 if (RetVT == MVT::f80)
589 return SINTTOFP_I128_F80;
590 if (RetVT == MVT::f128)
591 return SINTTOFP_I128_F128;
592 if (RetVT == MVT::ppcf128)
593 return SINTTOFP_I128_PPCF128;
595 return UNKNOWN_LIBCALL;
598 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
599 /// UNKNOWN_LIBCALL if there is none.
600 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
601 if (OpVT == MVT::i32) {
602 if (RetVT == MVT::f32)
603 return UINTTOFP_I32_F32;
604 if (RetVT == MVT::f64)
605 return UINTTOFP_I32_F64;
606 if (RetVT == MVT::f80)
607 return UINTTOFP_I32_F80;
608 if (RetVT == MVT::f128)
609 return UINTTOFP_I32_F128;
610 if (RetVT == MVT::ppcf128)
611 return UINTTOFP_I32_PPCF128;
612 } else if (OpVT == MVT::i64) {
613 if (RetVT == MVT::f32)
614 return UINTTOFP_I64_F32;
615 if (RetVT == MVT::f64)
616 return UINTTOFP_I64_F64;
617 if (RetVT == MVT::f80)
618 return UINTTOFP_I64_F80;
619 if (RetVT == MVT::f128)
620 return UINTTOFP_I64_F128;
621 if (RetVT == MVT::ppcf128)
622 return UINTTOFP_I64_PPCF128;
623 } else if (OpVT == MVT::i128) {
624 if (RetVT == MVT::f32)
625 return UINTTOFP_I128_F32;
626 if (RetVT == MVT::f64)
627 return UINTTOFP_I128_F64;
628 if (RetVT == MVT::f80)
629 return UINTTOFP_I128_F80;
630 if (RetVT == MVT::f128)
631 return UINTTOFP_I128_F128;
632 if (RetVT == MVT::ppcf128)
633 return UINTTOFP_I128_PPCF128;
635 return UNKNOWN_LIBCALL;
638 /// InitCmpLibcallCCs - Set default comparison libcall CC.
640 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
641 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
642 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
643 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
644 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
645 CCs[RTLIB::UNE_F32] = ISD::SETNE;
646 CCs[RTLIB::UNE_F64] = ISD::SETNE;
647 CCs[RTLIB::UNE_F128] = ISD::SETNE;
648 CCs[RTLIB::OGE_F32] = ISD::SETGE;
649 CCs[RTLIB::OGE_F64] = ISD::SETGE;
650 CCs[RTLIB::OGE_F128] = ISD::SETGE;
651 CCs[RTLIB::OLT_F32] = ISD::SETLT;
652 CCs[RTLIB::OLT_F64] = ISD::SETLT;
653 CCs[RTLIB::OLT_F128] = ISD::SETLT;
654 CCs[RTLIB::OLE_F32] = ISD::SETLE;
655 CCs[RTLIB::OLE_F64] = ISD::SETLE;
656 CCs[RTLIB::OLE_F128] = ISD::SETLE;
657 CCs[RTLIB::OGT_F32] = ISD::SETGT;
658 CCs[RTLIB::OGT_F64] = ISD::SETGT;
659 CCs[RTLIB::OGT_F128] = ISD::SETGT;
660 CCs[RTLIB::UO_F32] = ISD::SETNE;
661 CCs[RTLIB::UO_F64] = ISD::SETNE;
662 CCs[RTLIB::UO_F128] = ISD::SETNE;
663 CCs[RTLIB::O_F32] = ISD::SETEQ;
664 CCs[RTLIB::O_F64] = ISD::SETEQ;
665 CCs[RTLIB::O_F128] = ISD::SETEQ;
668 /// NOTE: The constructor takes ownership of TLOF.
669 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
670 const TargetLoweringObjectFile *tlof)
671 : TM(tm), DL(TM.getDataLayout()), TLOF(*tlof) {
674 // Perform these initializations only once.
675 IsLittleEndian = DL->isLittleEndian();
676 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
677 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
678 = MaxStoresPerMemmoveOptSize = 4;
679 UseUnderscoreSetJmp = false;
680 UseUnderscoreLongJmp = false;
681 SelectIsExpensive = false;
682 HasMultipleConditionRegisters = false;
683 HasExtractBitsInsn = false;
684 IntDivIsCheap = false;
685 Pow2DivIsCheap = false;
686 JumpIsExpensive = false;
687 PredictableSelectIsExpensive = false;
688 MaskAndBranchFoldingIsLegal = false;
689 StackPointerRegisterToSaveRestore = 0;
690 ExceptionPointerRegister = 0;
691 ExceptionSelectorRegister = 0;
692 BooleanContents = UndefinedBooleanContent;
693 BooleanVectorContents = UndefinedBooleanContent;
694 SchedPreferenceInfo = Sched::ILP;
696 JumpBufAlignment = 0;
697 MinFunctionAlignment = 0;
698 PrefFunctionAlignment = 0;
699 PrefLoopAlignment = 0;
700 MinStackArgumentAlignment = 1;
701 InsertFencesForAtomic = false;
702 SupportJumpTables = true;
703 MinimumJumpTableEntries = 4;
705 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple()));
706 InitCmpLibcallCCs(CmpLibcallCCs);
707 InitLibcallCallingConvs(LibcallCallingConvs);
710 TargetLoweringBase::~TargetLoweringBase() {
714 void TargetLoweringBase::initActions() {
715 // All operations default to being supported.
716 memset(OpActions, 0, sizeof(OpActions));
717 memset(LoadExtActions, 0, sizeof(LoadExtActions));
718 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
719 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
720 memset(CondCodeActions, 0, sizeof(CondCodeActions));
721 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
722 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
724 // Set default actions for various operations.
725 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
726 // Default all indexed load / store to expand.
727 for (unsigned IM = (unsigned)ISD::PRE_INC;
728 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
729 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
730 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
733 // These operations default to expand.
734 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
737 // These library functions default to expand.
738 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
740 // These operations default to expand for vector types.
741 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
742 VT <= MVT::LAST_VECTOR_VALUETYPE)
743 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
746 // Most targets ignore the @llvm.prefetch intrinsic.
747 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
749 // ConstantFP nodes default to expand. Targets can either change this to
750 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
751 // to optimize expansions for certain constants.
752 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
753 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
754 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
755 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
756 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
758 // These library functions default to expand.
759 setOperationAction(ISD::FLOG , MVT::f16, Expand);
760 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
761 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
762 setOperationAction(ISD::FEXP , MVT::f16, Expand);
763 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
764 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
765 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
766 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
767 setOperationAction(ISD::FRINT, MVT::f16, Expand);
768 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
769 setOperationAction(ISD::FROUND, MVT::f16, Expand);
770 setOperationAction(ISD::FLOG , MVT::f32, Expand);
771 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
772 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
773 setOperationAction(ISD::FEXP , MVT::f32, Expand);
774 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
775 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
777 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
778 setOperationAction(ISD::FRINT, MVT::f32, Expand);
779 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
780 setOperationAction(ISD::FROUND, MVT::f32, Expand);
781 setOperationAction(ISD::FLOG , MVT::f64, Expand);
782 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
783 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
784 setOperationAction(ISD::FEXP , MVT::f64, Expand);
785 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
786 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
788 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
789 setOperationAction(ISD::FRINT, MVT::f64, Expand);
790 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
791 setOperationAction(ISD::FROUND, MVT::f64, Expand);
792 setOperationAction(ISD::FLOG , MVT::f128, Expand);
793 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
794 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
795 setOperationAction(ISD::FEXP , MVT::f128, Expand);
796 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
797 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
798 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
799 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
800 setOperationAction(ISD::FRINT, MVT::f128, Expand);
801 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
802 setOperationAction(ISD::FROUND, MVT::f128, Expand);
804 // Default ISD::TRAP to expand (which turns it into abort).
805 setOperationAction(ISD::TRAP, MVT::Other, Expand);
807 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
808 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
810 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
813 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
814 return MVT::getIntegerVT(getPointerSizeInBits(AS));
817 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
818 return DL->getPointerSizeInBits(AS);
821 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
822 assert(Ty->isPointerTy());
823 return getPointerSizeInBits(Ty->getPointerAddressSpace());
826 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
827 return MVT::getIntegerVT(8*DL->getPointerSize(0));
830 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
831 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
832 if (LHSTy.isVector())
834 return getScalarShiftAmountTy(LHSTy);
837 /// canOpTrap - Returns true if the operation can trap for the value type.
838 /// VT must be a legal type.
839 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
840 assert(isTypeLegal(VT));
855 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
856 unsigned &NumIntermediates,
858 TargetLoweringBase *TLI) {
859 // Figure out the right, legal destination reg to copy into.
860 unsigned NumElts = VT.getVectorNumElements();
861 MVT EltTy = VT.getVectorElementType();
863 unsigned NumVectorRegs = 1;
865 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
866 // could break down into LHS/RHS like LegalizeDAG does.
867 if (!isPowerOf2_32(NumElts)) {
868 NumVectorRegs = NumElts;
872 // Divide the input until we get to a supported size. This will always
873 // end with a scalar if the target doesn't support vectors.
874 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
879 NumIntermediates = NumVectorRegs;
881 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
882 if (!TLI->isTypeLegal(NewVT))
884 IntermediateVT = NewVT;
886 unsigned NewVTSize = NewVT.getSizeInBits();
888 // Convert sizes such as i33 to i64.
889 if (!isPowerOf2_32(NewVTSize))
890 NewVTSize = NextPowerOf2(NewVTSize);
892 MVT DestVT = TLI->getRegisterType(NewVT);
894 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
895 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
897 // Otherwise, promotion or legal types use the same number of registers as
898 // the vector decimated to the appropriate level.
899 return NumVectorRegs;
902 /// isLegalRC - Return true if the value types that can be represented by the
903 /// specified register class are all legal.
904 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
905 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
913 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
914 /// sequence of memory operands that is recognized by PrologEpilogInserter.
916 TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
917 MachineBasicBlock *MBB) const {
918 MachineFunction &MF = *MI->getParent()->getParent();
920 // MI changes inside this loop as we grow operands.
921 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
922 MachineOperand &MO = MI->getOperand(OperIdx);
926 // foldMemoryOperand builds a new MI after replacing a single FI operand
927 // with the canonical set of five x86 addressing-mode operands.
928 int FI = MO.getIndex();
929 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
931 // Copy operands before the frame-index.
932 for (unsigned i = 0; i < OperIdx; ++i)
933 MIB.addOperand(MI->getOperand(i));
934 // Add frame index operands: direct-mem-ref tag, #FI, offset.
935 MIB.addImm(StackMaps::DirectMemRefOp);
936 MIB.addOperand(MI->getOperand(OperIdx));
938 // Copy the operands after the frame index.
939 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
940 MIB.addOperand(MI->getOperand(i));
942 // Inherit previous memory operands.
943 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
944 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
946 // Add a new memory operand for this FI.
947 const MachineFrameInfo &MFI = *MF.getFrameInfo();
948 assert(MFI.getObjectOffset(FI) != -1);
949 MachineMemOperand *MMO =
950 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
951 MachineMemOperand::MOLoad,
952 TM.getDataLayout()->getPointerSize(),
953 MFI.getObjectAlignment(FI));
954 MIB->addMemOperand(MF, MMO);
956 // Replace the instruction and update the operand index.
957 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
958 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
959 MI->eraseFromParent();
965 /// findRepresentativeClass - Return the largest legal super-reg register class
966 /// of the register class for the specified type and its associated "cost".
967 std::pair<const TargetRegisterClass*, uint8_t>
968 TargetLoweringBase::findRepresentativeClass(MVT VT) const {
969 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
970 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
972 return std::make_pair(RC, 0);
974 // Compute the set of all super-register classes.
975 BitVector SuperRegRC(TRI->getNumRegClasses());
976 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
977 SuperRegRC.setBitsInMask(RCI.getMask());
979 // Find the first legal register class with the largest spill size.
980 const TargetRegisterClass *BestRC = RC;
981 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
982 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
983 // We want the largest possible spill size.
984 if (SuperRC->getSize() <= BestRC->getSize())
986 if (!isLegalRC(SuperRC))
990 return std::make_pair(BestRC, 1);
993 /// computeRegisterProperties - Once all of the register classes are added,
994 /// this allows us to compute derived properties we expose.
995 void TargetLoweringBase::computeRegisterProperties() {
996 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
997 "Too many value types for ValueTypeActions to hold!");
999 // Everything defaults to needing one register.
1000 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1001 NumRegistersForVT[i] = 1;
1002 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1004 // ...except isVoid, which doesn't need any registers.
1005 NumRegistersForVT[MVT::isVoid] = 0;
1007 // Find the largest integer register class.
1008 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1009 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1010 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1012 // Every integer value type larger than this largest register takes twice as
1013 // many registers to represent as the previous ValueType.
1014 for (unsigned ExpandedReg = LargestIntReg + 1;
1015 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1016 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1017 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1018 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1019 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1023 // Inspect all of the ValueType's smaller than the largest integer
1024 // register to see which ones need promotion.
1025 unsigned LegalIntReg = LargestIntReg;
1026 for (unsigned IntReg = LargestIntReg - 1;
1027 IntReg >= (unsigned)MVT::i1; --IntReg) {
1028 MVT IVT = (MVT::SimpleValueType)IntReg;
1029 if (isTypeLegal(IVT)) {
1030 LegalIntReg = IntReg;
1032 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1033 (const MVT::SimpleValueType)LegalIntReg;
1034 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1038 // ppcf128 type is really two f64's.
1039 if (!isTypeLegal(MVT::ppcf128)) {
1040 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1041 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1042 TransformToType[MVT::ppcf128] = MVT::f64;
1043 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1046 // Decide how to handle f128. If the target does not have native f128 support,
1047 // expand it to i128 and we will be generating soft float library calls.
1048 if (!isTypeLegal(MVT::f128)) {
1049 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1050 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1051 TransformToType[MVT::f128] = MVT::i128;
1052 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1055 // Decide how to handle f64. If the target does not have native f64 support,
1056 // expand it to i64 and we will be generating soft float library calls.
1057 if (!isTypeLegal(MVT::f64)) {
1058 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1059 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1060 TransformToType[MVT::f64] = MVT::i64;
1061 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1064 // Decide how to handle f32. If the target does not have native support for
1065 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1066 if (!isTypeLegal(MVT::f32)) {
1067 if (isTypeLegal(MVT::f64)) {
1068 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1069 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1070 TransformToType[MVT::f32] = MVT::f64;
1071 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1073 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1074 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1075 TransformToType[MVT::f32] = MVT::i32;
1076 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1080 // Loop over all of the vector value types to see which need transformations.
1081 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1082 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1083 MVT VT = (MVT::SimpleValueType)i;
1084 if (isTypeLegal(VT)) continue;
1086 // Determine if there is a legal wider type. If so, we should promote to
1087 // that wider vector type.
1088 MVT EltVT = VT.getVectorElementType();
1089 unsigned NElts = VT.getVectorNumElements();
1090 if (NElts != 1 && !shouldSplitVectorType(VT)) {
1091 bool IsLegalWiderType = false;
1092 // First try to promote the elements of integer vectors. If no legal
1093 // promotion was found, fallback to the widen-vector method.
1094 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1095 MVT SVT = (MVT::SimpleValueType)nVT;
1096 // Promote vectors of integers to vectors with the same number
1097 // of elements, with a wider element type.
1098 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1099 && SVT.getVectorNumElements() == NElts &&
1100 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
1101 TransformToType[i] = SVT;
1102 RegisterTypeForVT[i] = SVT;
1103 NumRegistersForVT[i] = 1;
1104 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1105 IsLegalWiderType = true;
1110 if (IsLegalWiderType) continue;
1112 // Try to widen the vector.
1113 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1114 MVT SVT = (MVT::SimpleValueType)nVT;
1115 if (SVT.getVectorElementType() == EltVT &&
1116 SVT.getVectorNumElements() > NElts &&
1118 TransformToType[i] = SVT;
1119 RegisterTypeForVT[i] = SVT;
1120 NumRegistersForVT[i] = 1;
1121 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1122 IsLegalWiderType = true;
1126 if (IsLegalWiderType) continue;
1131 unsigned NumIntermediates;
1132 NumRegistersForVT[i] =
1133 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
1135 RegisterTypeForVT[i] = RegisterVT;
1137 MVT NVT = VT.getPow2VectorType();
1139 // Type is already a power of 2. The default action is to split.
1140 TransformToType[i] = MVT::Other;
1141 unsigned NumElts = VT.getVectorNumElements();
1142 ValueTypeActions.setTypeAction(VT,
1143 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
1145 TransformToType[i] = NVT;
1146 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1150 // Determine the 'representative' register class for each value type.
1151 // An representative register class is the largest (meaning one which is
1152 // not a sub-register class / subreg register class) legal register class for
1153 // a group of value types. For example, on i386, i8, i16, and i32
1154 // representative would be GR32; while on x86_64 it's GR64.
1155 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1156 const TargetRegisterClass* RRC;
1158 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1159 RepRegClassForVT[i] = RRC;
1160 RepRegClassCostForVT[i] = Cost;
1164 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
1165 assert(!VT.isVector() && "No default SetCC type for vectors!");
1166 return getPointerTy(0).SimpleTy;
1169 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1170 return MVT::i32; // return the default value
1173 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1174 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1175 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1176 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1178 /// This method returns the number of registers needed, and the VT for each
1179 /// register. It also returns the VT and quantity of the intermediate values
1180 /// before they are promoted/expanded.
1182 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1183 EVT &IntermediateVT,
1184 unsigned &NumIntermediates,
1185 MVT &RegisterVT) const {
1186 unsigned NumElts = VT.getVectorNumElements();
1188 // If there is a wider vector type with the same element type as this one,
1189 // or a promoted vector type that has the same number of elements which
1190 // are wider, then we should convert to that legal vector type.
1191 // This handles things like <2 x float> -> <4 x float> and
1192 // <4 x i1> -> <4 x i32>.
1193 LegalizeTypeAction TA = getTypeAction(Context, VT);
1194 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1195 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1196 if (isTypeLegal(RegisterEVT)) {
1197 IntermediateVT = RegisterEVT;
1198 RegisterVT = RegisterEVT.getSimpleVT();
1199 NumIntermediates = 1;
1204 // Figure out the right, legal destination reg to copy into.
1205 EVT EltTy = VT.getVectorElementType();
1207 unsigned NumVectorRegs = 1;
1209 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1210 // could break down into LHS/RHS like LegalizeDAG does.
1211 if (!isPowerOf2_32(NumElts)) {
1212 NumVectorRegs = NumElts;
1216 // Divide the input until we get to a supported size. This will always
1217 // end with a scalar if the target doesn't support vectors.
1218 while (NumElts > 1 && !isTypeLegal(
1219 EVT::getVectorVT(Context, EltTy, NumElts))) {
1221 NumVectorRegs <<= 1;
1224 NumIntermediates = NumVectorRegs;
1226 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1227 if (!isTypeLegal(NewVT))
1229 IntermediateVT = NewVT;
1231 MVT DestVT = getRegisterType(Context, NewVT);
1232 RegisterVT = DestVT;
1233 unsigned NewVTSize = NewVT.getSizeInBits();
1235 // Convert sizes such as i33 to i64.
1236 if (!isPowerOf2_32(NewVTSize))
1237 NewVTSize = NextPowerOf2(NewVTSize);
1239 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1240 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1242 // Otherwise, promotion or legal types use the same number of registers as
1243 // the vector decimated to the appropriate level.
1244 return NumVectorRegs;
1247 /// Get the EVTs and ArgFlags collections that represent the legalized return
1248 /// type of the given function. This does not require a DAG or a return value,
1249 /// and is suitable for use before any DAGs for the function are constructed.
1250 /// TODO: Move this out of TargetLowering.cpp.
1251 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1252 SmallVectorImpl<ISD::OutputArg> &Outs,
1253 const TargetLowering &TLI) {
1254 SmallVector<EVT, 4> ValueVTs;
1255 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1256 unsigned NumValues = ValueVTs.size();
1257 if (NumValues == 0) return;
1259 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1260 EVT VT = ValueVTs[j];
1261 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1263 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1264 ExtendKind = ISD::SIGN_EXTEND;
1265 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1266 ExtendKind = ISD::ZERO_EXTEND;
1268 // FIXME: C calling convention requires the return type to be promoted to
1269 // at least 32-bit. But this is not necessary for non-C calling
1270 // conventions. The frontend should mark functions whose return values
1271 // require promoting with signext or zeroext attributes.
1272 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1273 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1274 if (VT.bitsLT(MinVT))
1278 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1279 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1281 // 'inreg' on function refers to return value
1282 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1283 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1286 // Propagate extension type if any
1287 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1289 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1292 for (unsigned i = 0; i < NumParts; ++i)
1293 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1297 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1298 /// function arguments in the caller parameter area. This is the actual
1299 /// alignment, not its logarithm.
1300 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
1301 return DL->getABITypeAlignment(Ty);
1304 //===----------------------------------------------------------------------===//
1305 // TargetTransformInfo Helpers
1306 //===----------------------------------------------------------------------===//
1308 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1309 enum InstructionOpcodes {
1310 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1311 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1312 #include "llvm/IR/Instruction.def"
1314 switch (static_cast<InstructionOpcodes>(Opcode)) {
1317 case Switch: return 0;
1318 case IndirectBr: return 0;
1319 case Invoke: return 0;
1320 case Resume: return 0;
1321 case Unreachable: return 0;
1322 case Add: return ISD::ADD;
1323 case FAdd: return ISD::FADD;
1324 case Sub: return ISD::SUB;
1325 case FSub: return ISD::FSUB;
1326 case Mul: return ISD::MUL;
1327 case FMul: return ISD::FMUL;
1328 case UDiv: return ISD::UDIV;
1329 case SDiv: return ISD::SDIV;
1330 case FDiv: return ISD::FDIV;
1331 case URem: return ISD::UREM;
1332 case SRem: return ISD::SREM;
1333 case FRem: return ISD::FREM;
1334 case Shl: return ISD::SHL;
1335 case LShr: return ISD::SRL;
1336 case AShr: return ISD::SRA;
1337 case And: return ISD::AND;
1338 case Or: return ISD::OR;
1339 case Xor: return ISD::XOR;
1340 case Alloca: return 0;
1341 case Load: return ISD::LOAD;
1342 case Store: return ISD::STORE;
1343 case GetElementPtr: return 0;
1344 case Fence: return 0;
1345 case AtomicCmpXchg: return 0;
1346 case AtomicRMW: return 0;
1347 case Trunc: return ISD::TRUNCATE;
1348 case ZExt: return ISD::ZERO_EXTEND;
1349 case SExt: return ISD::SIGN_EXTEND;
1350 case FPToUI: return ISD::FP_TO_UINT;
1351 case FPToSI: return ISD::FP_TO_SINT;
1352 case UIToFP: return ISD::UINT_TO_FP;
1353 case SIToFP: return ISD::SINT_TO_FP;
1354 case FPTrunc: return ISD::FP_ROUND;
1355 case FPExt: return ISD::FP_EXTEND;
1356 case PtrToInt: return ISD::BITCAST;
1357 case IntToPtr: return ISD::BITCAST;
1358 case BitCast: return ISD::BITCAST;
1359 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1360 case ICmp: return ISD::SETCC;
1361 case FCmp: return ISD::SETCC;
1363 case Call: return 0;
1364 case Select: return ISD::SELECT;
1365 case UserOp1: return 0;
1366 case UserOp2: return 0;
1367 case VAArg: return 0;
1368 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1369 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1370 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1371 case ExtractValue: return ISD::MERGE_VALUES;
1372 case InsertValue: return ISD::MERGE_VALUES;
1373 case LandingPad: return 0;
1376 llvm_unreachable("Unknown instruction type encountered!");
1379 std::pair<unsigned, MVT>
1380 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1381 LLVMContext &C = Ty->getContext();
1382 EVT MTy = getValueType(Ty);
1385 // We keep legalizing the type until we find a legal kind. We assume that
1386 // the only operation that costs anything is the split. After splitting
1387 // we need to handle two types.
1389 LegalizeKind LK = getTypeConversion(C, MTy);
1391 if (LK.first == TypeLegal)
1392 return std::make_pair(Cost, MTy.getSimpleVT());
1394 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1397 // Keep legalizing the type.
1402 //===----------------------------------------------------------------------===//
1403 // Loop Strength Reduction hooks
1404 //===----------------------------------------------------------------------===//
1406 /// isLegalAddressingMode - Return true if the addressing mode represented
1407 /// by AM is legal for this target, for a load/store of the specified type.
1408 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1410 // The default implementation of this implements a conservative RISCy, r+r and
1413 // Allows a sign-extended 16-bit immediate field.
1414 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1417 // No global is ever allowed as a base.
1421 // Only support r+r,
1423 case 0: // "r+i" or just "i", depending on HasBaseReg.
1426 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1428 // Otherwise we have r+r or r+i.
1431 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1433 // Allow 2*r as r+r.
1435 default: // Don't allow n * r