1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLoweringBase class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
38 /// InitLibcallNames - Set default libcall names.
40 static void InitLibcallNames(const char **Names, const TargetMachine &TM) {
41 Names[RTLIB::SHL_I16] = "__ashlhi3";
42 Names[RTLIB::SHL_I32] = "__ashlsi3";
43 Names[RTLIB::SHL_I64] = "__ashldi3";
44 Names[RTLIB::SHL_I128] = "__ashlti3";
45 Names[RTLIB::SRL_I16] = "__lshrhi3";
46 Names[RTLIB::SRL_I32] = "__lshrsi3";
47 Names[RTLIB::SRL_I64] = "__lshrdi3";
48 Names[RTLIB::SRL_I128] = "__lshrti3";
49 Names[RTLIB::SRA_I16] = "__ashrhi3";
50 Names[RTLIB::SRA_I32] = "__ashrsi3";
51 Names[RTLIB::SRA_I64] = "__ashrdi3";
52 Names[RTLIB::SRA_I128] = "__ashrti3";
53 Names[RTLIB::MUL_I8] = "__mulqi3";
54 Names[RTLIB::MUL_I16] = "__mulhi3";
55 Names[RTLIB::MUL_I32] = "__mulsi3";
56 Names[RTLIB::MUL_I64] = "__muldi3";
57 Names[RTLIB::MUL_I128] = "__multi3";
58 Names[RTLIB::MULO_I32] = "__mulosi4";
59 Names[RTLIB::MULO_I64] = "__mulodi4";
60 Names[RTLIB::MULO_I128] = "__muloti4";
61 Names[RTLIB::SDIV_I8] = "__divqi3";
62 Names[RTLIB::SDIV_I16] = "__divhi3";
63 Names[RTLIB::SDIV_I32] = "__divsi3";
64 Names[RTLIB::SDIV_I64] = "__divdi3";
65 Names[RTLIB::SDIV_I128] = "__divti3";
66 Names[RTLIB::UDIV_I8] = "__udivqi3";
67 Names[RTLIB::UDIV_I16] = "__udivhi3";
68 Names[RTLIB::UDIV_I32] = "__udivsi3";
69 Names[RTLIB::UDIV_I64] = "__udivdi3";
70 Names[RTLIB::UDIV_I128] = "__udivti3";
71 Names[RTLIB::SREM_I8] = "__modqi3";
72 Names[RTLIB::SREM_I16] = "__modhi3";
73 Names[RTLIB::SREM_I32] = "__modsi3";
74 Names[RTLIB::SREM_I64] = "__moddi3";
75 Names[RTLIB::SREM_I128] = "__modti3";
76 Names[RTLIB::UREM_I8] = "__umodqi3";
77 Names[RTLIB::UREM_I16] = "__umodhi3";
78 Names[RTLIB::UREM_I32] = "__umodsi3";
79 Names[RTLIB::UREM_I64] = "__umoddi3";
80 Names[RTLIB::UREM_I128] = "__umodti3";
82 // These are generally not available.
83 Names[RTLIB::SDIVREM_I8] = 0;
84 Names[RTLIB::SDIVREM_I16] = 0;
85 Names[RTLIB::SDIVREM_I32] = 0;
86 Names[RTLIB::SDIVREM_I64] = 0;
87 Names[RTLIB::SDIVREM_I128] = 0;
88 Names[RTLIB::UDIVREM_I8] = 0;
89 Names[RTLIB::UDIVREM_I16] = 0;
90 Names[RTLIB::UDIVREM_I32] = 0;
91 Names[RTLIB::UDIVREM_I64] = 0;
92 Names[RTLIB::UDIVREM_I128] = 0;
94 Names[RTLIB::NEG_I32] = "__negsi2";
95 Names[RTLIB::NEG_I64] = "__negdi2";
96 Names[RTLIB::ADD_F32] = "__addsf3";
97 Names[RTLIB::ADD_F64] = "__adddf3";
98 Names[RTLIB::ADD_F80] = "__addxf3";
99 Names[RTLIB::ADD_F128] = "__addtf3";
100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
103 Names[RTLIB::SUB_F80] = "__subxf3";
104 Names[RTLIB::SUB_F128] = "__subtf3";
105 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
106 Names[RTLIB::MUL_F32] = "__mulsf3";
107 Names[RTLIB::MUL_F64] = "__muldf3";
108 Names[RTLIB::MUL_F80] = "__mulxf3";
109 Names[RTLIB::MUL_F128] = "__multf3";
110 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
111 Names[RTLIB::DIV_F32] = "__divsf3";
112 Names[RTLIB::DIV_F64] = "__divdf3";
113 Names[RTLIB::DIV_F80] = "__divxf3";
114 Names[RTLIB::DIV_F128] = "__divtf3";
115 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
116 Names[RTLIB::REM_F32] = "fmodf";
117 Names[RTLIB::REM_F64] = "fmod";
118 Names[RTLIB::REM_F80] = "fmodl";
119 Names[RTLIB::REM_F128] = "fmodl";
120 Names[RTLIB::REM_PPCF128] = "fmodl";
121 Names[RTLIB::FMA_F32] = "fmaf";
122 Names[RTLIB::FMA_F64] = "fma";
123 Names[RTLIB::FMA_F80] = "fmal";
124 Names[RTLIB::FMA_F128] = "fmal";
125 Names[RTLIB::FMA_PPCF128] = "fmal";
126 Names[RTLIB::POWI_F32] = "__powisf2";
127 Names[RTLIB::POWI_F64] = "__powidf2";
128 Names[RTLIB::POWI_F80] = "__powixf2";
129 Names[RTLIB::POWI_F128] = "__powitf2";
130 Names[RTLIB::POWI_PPCF128] = "__powitf2";
131 Names[RTLIB::SQRT_F32] = "sqrtf";
132 Names[RTLIB::SQRT_F64] = "sqrt";
133 Names[RTLIB::SQRT_F80] = "sqrtl";
134 Names[RTLIB::SQRT_F128] = "sqrtl";
135 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
136 Names[RTLIB::LOG_F32] = "logf";
137 Names[RTLIB::LOG_F64] = "log";
138 Names[RTLIB::LOG_F80] = "logl";
139 Names[RTLIB::LOG_F128] = "logl";
140 Names[RTLIB::LOG_PPCF128] = "logl";
141 Names[RTLIB::LOG2_F32] = "log2f";
142 Names[RTLIB::LOG2_F64] = "log2";
143 Names[RTLIB::LOG2_F80] = "log2l";
144 Names[RTLIB::LOG2_F128] = "log2l";
145 Names[RTLIB::LOG2_PPCF128] = "log2l";
146 Names[RTLIB::LOG10_F32] = "log10f";
147 Names[RTLIB::LOG10_F64] = "log10";
148 Names[RTLIB::LOG10_F80] = "log10l";
149 Names[RTLIB::LOG10_F128] = "log10l";
150 Names[RTLIB::LOG10_PPCF128] = "log10l";
151 Names[RTLIB::EXP_F32] = "expf";
152 Names[RTLIB::EXP_F64] = "exp";
153 Names[RTLIB::EXP_F80] = "expl";
154 Names[RTLIB::EXP_F128] = "expl";
155 Names[RTLIB::EXP_PPCF128] = "expl";
156 Names[RTLIB::EXP2_F32] = "exp2f";
157 Names[RTLIB::EXP2_F64] = "exp2";
158 Names[RTLIB::EXP2_F80] = "exp2l";
159 Names[RTLIB::EXP2_F128] = "exp2l";
160 Names[RTLIB::EXP2_PPCF128] = "exp2l";
161 Names[RTLIB::SIN_F32] = "sinf";
162 Names[RTLIB::SIN_F64] = "sin";
163 Names[RTLIB::SIN_F80] = "sinl";
164 Names[RTLIB::SIN_F128] = "sinl";
165 Names[RTLIB::SIN_PPCF128] = "sinl";
166 Names[RTLIB::COS_F32] = "cosf";
167 Names[RTLIB::COS_F64] = "cos";
168 Names[RTLIB::COS_F80] = "cosl";
169 Names[RTLIB::COS_F128] = "cosl";
170 Names[RTLIB::COS_PPCF128] = "cosl";
171 Names[RTLIB::POW_F32] = "powf";
172 Names[RTLIB::POW_F64] = "pow";
173 Names[RTLIB::POW_F80] = "powl";
174 Names[RTLIB::POW_F128] = "powl";
175 Names[RTLIB::POW_PPCF128] = "powl";
176 Names[RTLIB::CEIL_F32] = "ceilf";
177 Names[RTLIB::CEIL_F64] = "ceil";
178 Names[RTLIB::CEIL_F80] = "ceill";
179 Names[RTLIB::CEIL_F128] = "ceill";
180 Names[RTLIB::CEIL_PPCF128] = "ceill";
181 Names[RTLIB::TRUNC_F32] = "truncf";
182 Names[RTLIB::TRUNC_F64] = "trunc";
183 Names[RTLIB::TRUNC_F80] = "truncl";
184 Names[RTLIB::TRUNC_F128] = "truncl";
185 Names[RTLIB::TRUNC_PPCF128] = "truncl";
186 Names[RTLIB::RINT_F32] = "rintf";
187 Names[RTLIB::RINT_F64] = "rint";
188 Names[RTLIB::RINT_F80] = "rintl";
189 Names[RTLIB::RINT_F128] = "rintl";
190 Names[RTLIB::RINT_PPCF128] = "rintl";
191 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
192 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
193 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
194 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
195 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
196 Names[RTLIB::ROUND_F32] = "roundf";
197 Names[RTLIB::ROUND_F64] = "round";
198 Names[RTLIB::ROUND_F80] = "roundl";
199 Names[RTLIB::ROUND_F128] = "roundl";
200 Names[RTLIB::ROUND_PPCF128] = "roundl";
201 Names[RTLIB::FLOOR_F32] = "floorf";
202 Names[RTLIB::FLOOR_F64] = "floor";
203 Names[RTLIB::FLOOR_F80] = "floorl";
204 Names[RTLIB::FLOOR_F128] = "floorl";
205 Names[RTLIB::FLOOR_PPCF128] = "floorl";
206 Names[RTLIB::COPYSIGN_F32] = "copysignf";
207 Names[RTLIB::COPYSIGN_F64] = "copysign";
208 Names[RTLIB::COPYSIGN_F80] = "copysignl";
209 Names[RTLIB::COPYSIGN_F128] = "copysignl";
210 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
211 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
212 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
213 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
214 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
215 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
216 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
217 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
218 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
219 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
220 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
221 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
222 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
223 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
224 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
225 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
226 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
227 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
228 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
229 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
230 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
231 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
232 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
233 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
234 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
235 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
236 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
237 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
238 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
239 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
240 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
241 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
242 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
243 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
244 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
245 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
246 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
247 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
248 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
249 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
250 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
251 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
252 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
253 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
254 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
255 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
256 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
257 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
258 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
259 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
260 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
261 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
262 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
263 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
264 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
265 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
266 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
267 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
268 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
269 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
270 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
271 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
272 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
273 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
274 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
275 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
276 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
277 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
278 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
279 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
280 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
281 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
282 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
283 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
284 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
285 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
286 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
287 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
288 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
289 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
290 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
291 Names[RTLIB::OEQ_F32] = "__eqsf2";
292 Names[RTLIB::OEQ_F64] = "__eqdf2";
293 Names[RTLIB::OEQ_F128] = "__eqtf2";
294 Names[RTLIB::UNE_F32] = "__nesf2";
295 Names[RTLIB::UNE_F64] = "__nedf2";
296 Names[RTLIB::UNE_F128] = "__netf2";
297 Names[RTLIB::OGE_F32] = "__gesf2";
298 Names[RTLIB::OGE_F64] = "__gedf2";
299 Names[RTLIB::OGE_F128] = "__getf2";
300 Names[RTLIB::OLT_F32] = "__ltsf2";
301 Names[RTLIB::OLT_F64] = "__ltdf2";
302 Names[RTLIB::OLT_F128] = "__lttf2";
303 Names[RTLIB::OLE_F32] = "__lesf2";
304 Names[RTLIB::OLE_F64] = "__ledf2";
305 Names[RTLIB::OLE_F128] = "__letf2";
306 Names[RTLIB::OGT_F32] = "__gtsf2";
307 Names[RTLIB::OGT_F64] = "__gtdf2";
308 Names[RTLIB::OGT_F128] = "__gttf2";
309 Names[RTLIB::UO_F32] = "__unordsf2";
310 Names[RTLIB::UO_F64] = "__unorddf2";
311 Names[RTLIB::UO_F128] = "__unordtf2";
312 Names[RTLIB::O_F32] = "__unordsf2";
313 Names[RTLIB::O_F64] = "__unorddf2";
314 Names[RTLIB::O_F128] = "__unordtf2";
315 Names[RTLIB::MEMCPY] = "memcpy";
316 Names[RTLIB::MEMMOVE] = "memmove";
317 Names[RTLIB::MEMSET] = "memset";
318 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
319 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
320 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
321 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
322 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
323 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
324 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
325 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
326 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
327 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
328 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
329 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
330 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
331 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
332 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
333 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
334 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
335 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
336 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
337 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
338 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
339 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
340 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
341 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
342 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
343 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
344 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
345 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
346 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
347 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
348 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
349 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
350 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
351 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
352 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
353 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
354 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
355 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
356 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
357 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
358 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
359 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
360 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
361 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
362 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
363 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
364 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
365 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
366 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
367 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
368 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
369 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
370 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
371 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
372 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
373 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
374 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
375 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
376 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
377 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
378 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
380 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) {
381 Names[RTLIB::SINCOS_F32] = "sincosf";
382 Names[RTLIB::SINCOS_F64] = "sincos";
383 Names[RTLIB::SINCOS_F80] = "sincosl";
384 Names[RTLIB::SINCOS_F128] = "sincosl";
385 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
387 // These are generally not available.
388 Names[RTLIB::SINCOS_F32] = 0;
389 Names[RTLIB::SINCOS_F64] = 0;
390 Names[RTLIB::SINCOS_F80] = 0;
391 Names[RTLIB::SINCOS_F128] = 0;
392 Names[RTLIB::SINCOS_PPCF128] = 0;
395 if (Triple(TM.getTargetTriple()).getOS() != Triple::OpenBSD) {
396 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
398 // These are generally not available.
399 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = 0;
403 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
405 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
406 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
407 CCs[i] = CallingConv::C;
411 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
412 /// UNKNOWN_LIBCALL if there is none.
413 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
414 if (OpVT == MVT::f32) {
415 if (RetVT == MVT::f64)
416 return FPEXT_F32_F64;
417 if (RetVT == MVT::f128)
418 return FPEXT_F32_F128;
419 } else if (OpVT == MVT::f64) {
420 if (RetVT == MVT::f128)
421 return FPEXT_F64_F128;
424 return UNKNOWN_LIBCALL;
427 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
428 /// UNKNOWN_LIBCALL if there is none.
429 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
430 if (RetVT == MVT::f32) {
431 if (OpVT == MVT::f64)
432 return FPROUND_F64_F32;
433 if (OpVT == MVT::f80)
434 return FPROUND_F80_F32;
435 if (OpVT == MVT::f128)
436 return FPROUND_F128_F32;
437 if (OpVT == MVT::ppcf128)
438 return FPROUND_PPCF128_F32;
439 } else if (RetVT == MVT::f64) {
440 if (OpVT == MVT::f80)
441 return FPROUND_F80_F64;
442 if (OpVT == MVT::f128)
443 return FPROUND_F128_F64;
444 if (OpVT == MVT::ppcf128)
445 return FPROUND_PPCF128_F64;
448 return UNKNOWN_LIBCALL;
451 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
452 /// UNKNOWN_LIBCALL if there is none.
453 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
454 if (OpVT == MVT::f32) {
455 if (RetVT == MVT::i8)
456 return FPTOSINT_F32_I8;
457 if (RetVT == MVT::i16)
458 return FPTOSINT_F32_I16;
459 if (RetVT == MVT::i32)
460 return FPTOSINT_F32_I32;
461 if (RetVT == MVT::i64)
462 return FPTOSINT_F32_I64;
463 if (RetVT == MVT::i128)
464 return FPTOSINT_F32_I128;
465 } else if (OpVT == MVT::f64) {
466 if (RetVT == MVT::i8)
467 return FPTOSINT_F64_I8;
468 if (RetVT == MVT::i16)
469 return FPTOSINT_F64_I16;
470 if (RetVT == MVT::i32)
471 return FPTOSINT_F64_I32;
472 if (RetVT == MVT::i64)
473 return FPTOSINT_F64_I64;
474 if (RetVT == MVT::i128)
475 return FPTOSINT_F64_I128;
476 } else if (OpVT == MVT::f80) {
477 if (RetVT == MVT::i32)
478 return FPTOSINT_F80_I32;
479 if (RetVT == MVT::i64)
480 return FPTOSINT_F80_I64;
481 if (RetVT == MVT::i128)
482 return FPTOSINT_F80_I128;
483 } else if (OpVT == MVT::f128) {
484 if (RetVT == MVT::i32)
485 return FPTOSINT_F128_I32;
486 if (RetVT == MVT::i64)
487 return FPTOSINT_F128_I64;
488 if (RetVT == MVT::i128)
489 return FPTOSINT_F128_I128;
490 } else if (OpVT == MVT::ppcf128) {
491 if (RetVT == MVT::i32)
492 return FPTOSINT_PPCF128_I32;
493 if (RetVT == MVT::i64)
494 return FPTOSINT_PPCF128_I64;
495 if (RetVT == MVT::i128)
496 return FPTOSINT_PPCF128_I128;
498 return UNKNOWN_LIBCALL;
501 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
502 /// UNKNOWN_LIBCALL if there is none.
503 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
504 if (OpVT == MVT::f32) {
505 if (RetVT == MVT::i8)
506 return FPTOUINT_F32_I8;
507 if (RetVT == MVT::i16)
508 return FPTOUINT_F32_I16;
509 if (RetVT == MVT::i32)
510 return FPTOUINT_F32_I32;
511 if (RetVT == MVT::i64)
512 return FPTOUINT_F32_I64;
513 if (RetVT == MVT::i128)
514 return FPTOUINT_F32_I128;
515 } else if (OpVT == MVT::f64) {
516 if (RetVT == MVT::i8)
517 return FPTOUINT_F64_I8;
518 if (RetVT == MVT::i16)
519 return FPTOUINT_F64_I16;
520 if (RetVT == MVT::i32)
521 return FPTOUINT_F64_I32;
522 if (RetVT == MVT::i64)
523 return FPTOUINT_F64_I64;
524 if (RetVT == MVT::i128)
525 return FPTOUINT_F64_I128;
526 } else if (OpVT == MVT::f80) {
527 if (RetVT == MVT::i32)
528 return FPTOUINT_F80_I32;
529 if (RetVT == MVT::i64)
530 return FPTOUINT_F80_I64;
531 if (RetVT == MVT::i128)
532 return FPTOUINT_F80_I128;
533 } else if (OpVT == MVT::f128) {
534 if (RetVT == MVT::i32)
535 return FPTOUINT_F128_I32;
536 if (RetVT == MVT::i64)
537 return FPTOUINT_F128_I64;
538 if (RetVT == MVT::i128)
539 return FPTOUINT_F128_I128;
540 } else if (OpVT == MVT::ppcf128) {
541 if (RetVT == MVT::i32)
542 return FPTOUINT_PPCF128_I32;
543 if (RetVT == MVT::i64)
544 return FPTOUINT_PPCF128_I64;
545 if (RetVT == MVT::i128)
546 return FPTOUINT_PPCF128_I128;
548 return UNKNOWN_LIBCALL;
551 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
552 /// UNKNOWN_LIBCALL if there is none.
553 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
554 if (OpVT == MVT::i32) {
555 if (RetVT == MVT::f32)
556 return SINTTOFP_I32_F32;
557 if (RetVT == MVT::f64)
558 return SINTTOFP_I32_F64;
559 if (RetVT == MVT::f80)
560 return SINTTOFP_I32_F80;
561 if (RetVT == MVT::f128)
562 return SINTTOFP_I32_F128;
563 if (RetVT == MVT::ppcf128)
564 return SINTTOFP_I32_PPCF128;
565 } else if (OpVT == MVT::i64) {
566 if (RetVT == MVT::f32)
567 return SINTTOFP_I64_F32;
568 if (RetVT == MVT::f64)
569 return SINTTOFP_I64_F64;
570 if (RetVT == MVT::f80)
571 return SINTTOFP_I64_F80;
572 if (RetVT == MVT::f128)
573 return SINTTOFP_I64_F128;
574 if (RetVT == MVT::ppcf128)
575 return SINTTOFP_I64_PPCF128;
576 } else if (OpVT == MVT::i128) {
577 if (RetVT == MVT::f32)
578 return SINTTOFP_I128_F32;
579 if (RetVT == MVT::f64)
580 return SINTTOFP_I128_F64;
581 if (RetVT == MVT::f80)
582 return SINTTOFP_I128_F80;
583 if (RetVT == MVT::f128)
584 return SINTTOFP_I128_F128;
585 if (RetVT == MVT::ppcf128)
586 return SINTTOFP_I128_PPCF128;
588 return UNKNOWN_LIBCALL;
591 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
592 /// UNKNOWN_LIBCALL if there is none.
593 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
594 if (OpVT == MVT::i32) {
595 if (RetVT == MVT::f32)
596 return UINTTOFP_I32_F32;
597 if (RetVT == MVT::f64)
598 return UINTTOFP_I32_F64;
599 if (RetVT == MVT::f80)
600 return UINTTOFP_I32_F80;
601 if (RetVT == MVT::f128)
602 return UINTTOFP_I32_F128;
603 if (RetVT == MVT::ppcf128)
604 return UINTTOFP_I32_PPCF128;
605 } else if (OpVT == MVT::i64) {
606 if (RetVT == MVT::f32)
607 return UINTTOFP_I64_F32;
608 if (RetVT == MVT::f64)
609 return UINTTOFP_I64_F64;
610 if (RetVT == MVT::f80)
611 return UINTTOFP_I64_F80;
612 if (RetVT == MVT::f128)
613 return UINTTOFP_I64_F128;
614 if (RetVT == MVT::ppcf128)
615 return UINTTOFP_I64_PPCF128;
616 } else if (OpVT == MVT::i128) {
617 if (RetVT == MVT::f32)
618 return UINTTOFP_I128_F32;
619 if (RetVT == MVT::f64)
620 return UINTTOFP_I128_F64;
621 if (RetVT == MVT::f80)
622 return UINTTOFP_I128_F80;
623 if (RetVT == MVT::f128)
624 return UINTTOFP_I128_F128;
625 if (RetVT == MVT::ppcf128)
626 return UINTTOFP_I128_PPCF128;
628 return UNKNOWN_LIBCALL;
631 /// InitCmpLibcallCCs - Set default comparison libcall CC.
633 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
634 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
635 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
636 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
637 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
638 CCs[RTLIB::UNE_F32] = ISD::SETNE;
639 CCs[RTLIB::UNE_F64] = ISD::SETNE;
640 CCs[RTLIB::UNE_F128] = ISD::SETNE;
641 CCs[RTLIB::OGE_F32] = ISD::SETGE;
642 CCs[RTLIB::OGE_F64] = ISD::SETGE;
643 CCs[RTLIB::OGE_F128] = ISD::SETGE;
644 CCs[RTLIB::OLT_F32] = ISD::SETLT;
645 CCs[RTLIB::OLT_F64] = ISD::SETLT;
646 CCs[RTLIB::OLT_F128] = ISD::SETLT;
647 CCs[RTLIB::OLE_F32] = ISD::SETLE;
648 CCs[RTLIB::OLE_F64] = ISD::SETLE;
649 CCs[RTLIB::OLE_F128] = ISD::SETLE;
650 CCs[RTLIB::OGT_F32] = ISD::SETGT;
651 CCs[RTLIB::OGT_F64] = ISD::SETGT;
652 CCs[RTLIB::OGT_F128] = ISD::SETGT;
653 CCs[RTLIB::UO_F32] = ISD::SETNE;
654 CCs[RTLIB::UO_F64] = ISD::SETNE;
655 CCs[RTLIB::UO_F128] = ISD::SETNE;
656 CCs[RTLIB::O_F32] = ISD::SETEQ;
657 CCs[RTLIB::O_F64] = ISD::SETEQ;
658 CCs[RTLIB::O_F128] = ISD::SETEQ;
661 /// NOTE: The constructor takes ownership of TLOF.
662 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
663 const TargetLoweringObjectFile *tlof)
664 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
667 // Perform these initializations only once.
668 IsLittleEndian = TD->isLittleEndian();
669 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
670 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
671 = MaxStoresPerMemmoveOptSize = 4;
672 UseUnderscoreSetJmp = false;
673 UseUnderscoreLongJmp = false;
674 SelectIsExpensive = false;
675 HasMultipleConditionRegisters = false;
676 IntDivIsCheap = false;
677 Pow2DivIsCheap = false;
678 JumpIsExpensive = false;
679 PredictableSelectIsExpensive = false;
680 StackPointerRegisterToSaveRestore = 0;
681 ExceptionPointerRegister = 0;
682 ExceptionSelectorRegister = 0;
683 BooleanContents = UndefinedBooleanContent;
684 BooleanVectorContents = UndefinedBooleanContent;
685 SchedPreferenceInfo = Sched::ILP;
687 JumpBufAlignment = 0;
688 MinFunctionAlignment = 0;
689 PrefFunctionAlignment = 0;
690 PrefLoopAlignment = 0;
691 MinStackArgumentAlignment = 1;
692 InsertFencesForAtomic = false;
693 SupportJumpTables = true;
694 MinimumJumpTableEntries = 4;
696 InitLibcallNames(LibcallRoutineNames, TM);
697 InitCmpLibcallCCs(CmpLibcallCCs);
698 InitLibcallCallingConvs(LibcallCallingConvs);
701 TargetLoweringBase::~TargetLoweringBase() {
705 void TargetLoweringBase::initActions() {
706 // All operations default to being supported.
707 memset(OpActions, 0, sizeof(OpActions));
708 memset(LoadExtActions, 0, sizeof(LoadExtActions));
709 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
710 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
711 memset(CondCodeActions, 0, sizeof(CondCodeActions));
712 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
713 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
715 // Set default actions for various operations.
716 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
717 // Default all indexed load / store to expand.
718 for (unsigned IM = (unsigned)ISD::PRE_INC;
719 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
720 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
721 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
724 // These operations default to expand.
725 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
728 // These library functions default to expand.
729 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
731 // These operations default to expand for vector types.
732 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
733 VT <= MVT::LAST_VECTOR_VALUETYPE)
734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
737 // Most targets ignore the @llvm.prefetch intrinsic.
738 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
740 // ConstantFP nodes default to expand. Targets can either change this to
741 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
742 // to optimize expansions for certain constants.
743 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
744 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
745 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
746 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
747 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
749 // These library functions default to expand.
750 setOperationAction(ISD::FLOG , MVT::f16, Expand);
751 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
752 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
753 setOperationAction(ISD::FEXP , MVT::f16, Expand);
754 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
755 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
756 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
757 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
758 setOperationAction(ISD::FRINT, MVT::f16, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
760 setOperationAction(ISD::FLOG , MVT::f32, Expand);
761 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
762 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
763 setOperationAction(ISD::FEXP , MVT::f32, Expand);
764 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
765 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
766 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
767 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
768 setOperationAction(ISD::FRINT, MVT::f32, Expand);
769 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
770 setOperationAction(ISD::FLOG , MVT::f64, Expand);
771 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
772 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
773 setOperationAction(ISD::FEXP , MVT::f64, Expand);
774 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
775 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
777 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
778 setOperationAction(ISD::FRINT, MVT::f64, Expand);
779 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
780 setOperationAction(ISD::FLOG , MVT::f128, Expand);
781 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
782 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
783 setOperationAction(ISD::FEXP , MVT::f128, Expand);
784 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
785 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
786 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
787 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
788 setOperationAction(ISD::FRINT, MVT::f128, Expand);
789 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
791 // Default ISD::TRAP to expand (which turns it into abort).
792 setOperationAction(ISD::TRAP, MVT::Other, Expand);
794 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
795 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
797 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
800 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
801 return MVT::getIntegerVT(getPointerSizeInBits(AS));
804 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
805 return TD->getPointerSizeInBits(AS);
808 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
809 assert(Ty->isPointerTy());
810 return getPointerSizeInBits(Ty->getPointerAddressSpace());
813 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
814 return MVT::getIntegerVT(8*TD->getPointerSize(0));
817 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
818 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
819 if (LHSTy.isVector())
821 return getScalarShiftAmountTy(LHSTy);
824 /// canOpTrap - Returns true if the operation can trap for the value type.
825 /// VT must be a legal type.
826 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
827 assert(isTypeLegal(VT));
842 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
843 unsigned &NumIntermediates,
845 TargetLoweringBase *TLI) {
846 // Figure out the right, legal destination reg to copy into.
847 unsigned NumElts = VT.getVectorNumElements();
848 MVT EltTy = VT.getVectorElementType();
850 unsigned NumVectorRegs = 1;
852 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
853 // could break down into LHS/RHS like LegalizeDAG does.
854 if (!isPowerOf2_32(NumElts)) {
855 NumVectorRegs = NumElts;
859 // Divide the input until we get to a supported size. This will always
860 // end with a scalar if the target doesn't support vectors.
861 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
866 NumIntermediates = NumVectorRegs;
868 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
869 if (!TLI->isTypeLegal(NewVT))
871 IntermediateVT = NewVT;
873 unsigned NewVTSize = NewVT.getSizeInBits();
875 // Convert sizes such as i33 to i64.
876 if (!isPowerOf2_32(NewVTSize))
877 NewVTSize = NextPowerOf2(NewVTSize);
879 MVT DestVT = TLI->getRegisterType(NewVT);
881 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
882 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
884 // Otherwise, promotion or legal types use the same number of registers as
885 // the vector decimated to the appropriate level.
886 return NumVectorRegs;
889 /// isLegalRC - Return true if the value types that can be represented by the
890 /// specified register class are all legal.
891 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
892 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
900 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
901 /// sequence of memory operands that is recognized by PrologEpilogInserter.
903 TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
904 MachineBasicBlock *MBB) const {
905 const TargetMachine &TM = getTargetMachine();
906 MachineFunction &MF = *MI->getParent()->getParent();
908 // MI changes inside this loop as we grow operands.
909 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
910 MachineOperand &MO = MI->getOperand(OperIdx);
914 // foldMemoryOperand builds a new MI after replacing a single FI operand
915 // with the canonical set of five x86 addressing-mode operands.
916 int FI = MO.getIndex();
917 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
919 // Copy operands before the frame-index.
920 for (unsigned i = 0; i < OperIdx; ++i)
921 MIB.addOperand(MI->getOperand(i));
922 // Add frame index operands: direct-mem-ref tag, #FI, offset.
923 MIB.addImm(StackMaps::DirectMemRefOp);
924 MIB.addOperand(MI->getOperand(OperIdx));
926 // Copy the operands after the frame index.
927 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
928 MIB.addOperand(MI->getOperand(i));
930 // Inherit previous memory operands.
931 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
932 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
934 // Add a new memory operand for this FI.
935 const MachineFrameInfo &MFI = *MF.getFrameInfo();
936 assert(MFI.getObjectOffset(FI) != -1);
937 MachineMemOperand *MMO =
938 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
939 MachineMemOperand::MOLoad,
940 TM.getDataLayout()->getPointerSize(),
941 MFI.getObjectAlignment(FI));
942 MIB->addMemOperand(MF, MMO);
944 // Replace the instruction and update the operand index.
945 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
946 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
947 MI->eraseFromParent();
953 /// findRepresentativeClass - Return the largest legal super-reg register class
954 /// of the register class for the specified type and its associated "cost".
955 std::pair<const TargetRegisterClass*, uint8_t>
956 TargetLoweringBase::findRepresentativeClass(MVT VT) const {
957 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
958 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
960 return std::make_pair(RC, 0);
962 // Compute the set of all super-register classes.
963 BitVector SuperRegRC(TRI->getNumRegClasses());
964 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
965 SuperRegRC.setBitsInMask(RCI.getMask());
967 // Find the first legal register class with the largest spill size.
968 const TargetRegisterClass *BestRC = RC;
969 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
970 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
971 // We want the largest possible spill size.
972 if (SuperRC->getSize() <= BestRC->getSize())
974 if (!isLegalRC(SuperRC))
978 return std::make_pair(BestRC, 1);
981 /// computeRegisterProperties - Once all of the register classes are added,
982 /// this allows us to compute derived properties we expose.
983 void TargetLoweringBase::computeRegisterProperties() {
984 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
985 "Too many value types for ValueTypeActions to hold!");
987 // Everything defaults to needing one register.
988 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
989 NumRegistersForVT[i] = 1;
990 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
992 // ...except isVoid, which doesn't need any registers.
993 NumRegistersForVT[MVT::isVoid] = 0;
995 // Find the largest integer register class.
996 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
997 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
998 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1000 // Every integer value type larger than this largest register takes twice as
1001 // many registers to represent as the previous ValueType.
1002 for (unsigned ExpandedReg = LargestIntReg + 1;
1003 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1004 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1005 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1006 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1007 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1011 // Inspect all of the ValueType's smaller than the largest integer
1012 // register to see which ones need promotion.
1013 unsigned LegalIntReg = LargestIntReg;
1014 for (unsigned IntReg = LargestIntReg - 1;
1015 IntReg >= (unsigned)MVT::i1; --IntReg) {
1016 MVT IVT = (MVT::SimpleValueType)IntReg;
1017 if (isTypeLegal(IVT)) {
1018 LegalIntReg = IntReg;
1020 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1021 (const MVT::SimpleValueType)LegalIntReg;
1022 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1026 // ppcf128 type is really two f64's.
1027 if (!isTypeLegal(MVT::ppcf128)) {
1028 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1029 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1030 TransformToType[MVT::ppcf128] = MVT::f64;
1031 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1034 // Decide how to handle f128. If the target does not have native f128 support,
1035 // expand it to i128 and we will be generating soft float library calls.
1036 if (!isTypeLegal(MVT::f128)) {
1037 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1038 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1039 TransformToType[MVT::f128] = MVT::i128;
1040 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1043 // Decide how to handle f64. If the target does not have native f64 support,
1044 // expand it to i64 and we will be generating soft float library calls.
1045 if (!isTypeLegal(MVT::f64)) {
1046 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1047 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1048 TransformToType[MVT::f64] = MVT::i64;
1049 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1052 // Decide how to handle f32. If the target does not have native support for
1053 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1054 if (!isTypeLegal(MVT::f32)) {
1055 if (isTypeLegal(MVT::f64)) {
1056 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1057 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1058 TransformToType[MVT::f32] = MVT::f64;
1059 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1061 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1062 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1063 TransformToType[MVT::f32] = MVT::i32;
1064 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1068 // Loop over all of the vector value types to see which need transformations.
1069 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1070 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1071 MVT VT = (MVT::SimpleValueType)i;
1072 if (isTypeLegal(VT)) continue;
1074 // Determine if there is a legal wider type. If so, we should promote to
1075 // that wider vector type.
1076 MVT EltVT = VT.getVectorElementType();
1077 unsigned NElts = VT.getVectorNumElements();
1078 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
1079 bool IsLegalWiderType = false;
1080 // First try to promote the elements of integer vectors. If no legal
1081 // promotion was found, fallback to the widen-vector method.
1082 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1083 MVT SVT = (MVT::SimpleValueType)nVT;
1084 // Promote vectors of integers to vectors with the same number
1085 // of elements, with a wider element type.
1086 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1087 && SVT.getVectorNumElements() == NElts &&
1088 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
1089 TransformToType[i] = SVT;
1090 RegisterTypeForVT[i] = SVT;
1091 NumRegistersForVT[i] = 1;
1092 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1093 IsLegalWiderType = true;
1098 if (IsLegalWiderType) continue;
1100 // Try to widen the vector.
1101 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1102 MVT SVT = (MVT::SimpleValueType)nVT;
1103 if (SVT.getVectorElementType() == EltVT &&
1104 SVT.getVectorNumElements() > NElts &&
1106 TransformToType[i] = SVT;
1107 RegisterTypeForVT[i] = SVT;
1108 NumRegistersForVT[i] = 1;
1109 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1110 IsLegalWiderType = true;
1114 if (IsLegalWiderType) continue;
1119 unsigned NumIntermediates;
1120 NumRegistersForVT[i] =
1121 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
1123 RegisterTypeForVT[i] = RegisterVT;
1125 MVT NVT = VT.getPow2VectorType();
1127 // Type is already a power of 2. The default action is to split.
1128 TransformToType[i] = MVT::Other;
1129 unsigned NumElts = VT.getVectorNumElements();
1130 ValueTypeActions.setTypeAction(VT,
1131 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
1133 TransformToType[i] = NVT;
1134 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1138 // Determine the 'representative' register class for each value type.
1139 // An representative register class is the largest (meaning one which is
1140 // not a sub-register class / subreg register class) legal register class for
1141 // a group of value types. For example, on i386, i8, i16, and i32
1142 // representative would be GR32; while on x86_64 it's GR64.
1143 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1144 const TargetRegisterClass* RRC;
1146 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1147 RepRegClassForVT[i] = RRC;
1148 RepRegClassCostForVT[i] = Cost;
1152 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
1153 assert(!VT.isVector() && "No default SetCC type for vectors!");
1154 return getPointerTy(0).SimpleTy;
1157 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1158 return MVT::i32; // return the default value
1161 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1162 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1163 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1164 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1166 /// This method returns the number of registers needed, and the VT for each
1167 /// register. It also returns the VT and quantity of the intermediate values
1168 /// before they are promoted/expanded.
1170 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1171 EVT &IntermediateVT,
1172 unsigned &NumIntermediates,
1173 MVT &RegisterVT) const {
1174 unsigned NumElts = VT.getVectorNumElements();
1176 // If there is a wider vector type with the same element type as this one,
1177 // or a promoted vector type that has the same number of elements which
1178 // are wider, then we should convert to that legal vector type.
1179 // This handles things like <2 x float> -> <4 x float> and
1180 // <4 x i1> -> <4 x i32>.
1181 LegalizeTypeAction TA = getTypeAction(Context, VT);
1182 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1183 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1184 if (isTypeLegal(RegisterEVT)) {
1185 IntermediateVT = RegisterEVT;
1186 RegisterVT = RegisterEVT.getSimpleVT();
1187 NumIntermediates = 1;
1192 // Figure out the right, legal destination reg to copy into.
1193 EVT EltTy = VT.getVectorElementType();
1195 unsigned NumVectorRegs = 1;
1197 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1198 // could break down into LHS/RHS like LegalizeDAG does.
1199 if (!isPowerOf2_32(NumElts)) {
1200 NumVectorRegs = NumElts;
1204 // Divide the input until we get to a supported size. This will always
1205 // end with a scalar if the target doesn't support vectors.
1206 while (NumElts > 1 && !isTypeLegal(
1207 EVT::getVectorVT(Context, EltTy, NumElts))) {
1209 NumVectorRegs <<= 1;
1212 NumIntermediates = NumVectorRegs;
1214 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1215 if (!isTypeLegal(NewVT))
1217 IntermediateVT = NewVT;
1219 MVT DestVT = getRegisterType(Context, NewVT);
1220 RegisterVT = DestVT;
1221 unsigned NewVTSize = NewVT.getSizeInBits();
1223 // Convert sizes such as i33 to i64.
1224 if (!isPowerOf2_32(NewVTSize))
1225 NewVTSize = NextPowerOf2(NewVTSize);
1227 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1228 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1230 // Otherwise, promotion or legal types use the same number of registers as
1231 // the vector decimated to the appropriate level.
1232 return NumVectorRegs;
1235 /// Get the EVTs and ArgFlags collections that represent the legalized return
1236 /// type of the given function. This does not require a DAG or a return value,
1237 /// and is suitable for use before any DAGs for the function are constructed.
1238 /// TODO: Move this out of TargetLowering.cpp.
1239 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1240 SmallVectorImpl<ISD::OutputArg> &Outs,
1241 const TargetLowering &TLI) {
1242 SmallVector<EVT, 4> ValueVTs;
1243 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1244 unsigned NumValues = ValueVTs.size();
1245 if (NumValues == 0) return;
1247 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1248 EVT VT = ValueVTs[j];
1249 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1251 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1252 ExtendKind = ISD::SIGN_EXTEND;
1253 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1254 ExtendKind = ISD::ZERO_EXTEND;
1256 // FIXME: C calling convention requires the return type to be promoted to
1257 // at least 32-bit. But this is not necessary for non-C calling
1258 // conventions. The frontend should mark functions whose return values
1259 // require promoting with signext or zeroext attributes.
1260 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1261 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1262 if (VT.bitsLT(MinVT))
1266 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1267 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1269 // 'inreg' on function refers to return value
1270 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1271 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1274 // Propagate extension type if any
1275 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1277 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1280 for (unsigned i = 0; i < NumParts; ++i)
1281 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1285 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1286 /// function arguments in the caller parameter area. This is the actual
1287 /// alignment, not its logarithm.
1288 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
1289 return TD->getABITypeAlignment(Ty);
1292 //===----------------------------------------------------------------------===//
1293 // TargetTransformInfo Helpers
1294 //===----------------------------------------------------------------------===//
1296 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1297 enum InstructionOpcodes {
1298 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1299 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1300 #include "llvm/IR/Instruction.def"
1302 switch (static_cast<InstructionOpcodes>(Opcode)) {
1305 case Switch: return 0;
1306 case IndirectBr: return 0;
1307 case Invoke: return 0;
1308 case Resume: return 0;
1309 case Unreachable: return 0;
1310 case Add: return ISD::ADD;
1311 case FAdd: return ISD::FADD;
1312 case Sub: return ISD::SUB;
1313 case FSub: return ISD::FSUB;
1314 case Mul: return ISD::MUL;
1315 case FMul: return ISD::FMUL;
1316 case UDiv: return ISD::UDIV;
1317 case SDiv: return ISD::UDIV;
1318 case FDiv: return ISD::FDIV;
1319 case URem: return ISD::UREM;
1320 case SRem: return ISD::SREM;
1321 case FRem: return ISD::FREM;
1322 case Shl: return ISD::SHL;
1323 case LShr: return ISD::SRL;
1324 case AShr: return ISD::SRA;
1325 case And: return ISD::AND;
1326 case Or: return ISD::OR;
1327 case Xor: return ISD::XOR;
1328 case Alloca: return 0;
1329 case Load: return ISD::LOAD;
1330 case Store: return ISD::STORE;
1331 case GetElementPtr: return 0;
1332 case Fence: return 0;
1333 case AtomicCmpXchg: return 0;
1334 case AtomicRMW: return 0;
1335 case Trunc: return ISD::TRUNCATE;
1336 case ZExt: return ISD::ZERO_EXTEND;
1337 case SExt: return ISD::SIGN_EXTEND;
1338 case FPToUI: return ISD::FP_TO_UINT;
1339 case FPToSI: return ISD::FP_TO_SINT;
1340 case UIToFP: return ISD::UINT_TO_FP;
1341 case SIToFP: return ISD::SINT_TO_FP;
1342 case FPTrunc: return ISD::FP_ROUND;
1343 case FPExt: return ISD::FP_EXTEND;
1344 case PtrToInt: return ISD::BITCAST;
1345 case IntToPtr: return ISD::BITCAST;
1346 case BitCast: return ISD::BITCAST;
1347 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1348 case ICmp: return ISD::SETCC;
1349 case FCmp: return ISD::SETCC;
1351 case Call: return 0;
1352 case Select: return ISD::SELECT;
1353 case UserOp1: return 0;
1354 case UserOp2: return 0;
1355 case VAArg: return 0;
1356 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1357 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1358 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1359 case ExtractValue: return ISD::MERGE_VALUES;
1360 case InsertValue: return ISD::MERGE_VALUES;
1361 case LandingPad: return 0;
1364 llvm_unreachable("Unknown instruction type encountered!");
1367 std::pair<unsigned, MVT>
1368 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1369 LLVMContext &C = Ty->getContext();
1370 EVT MTy = getValueType(Ty);
1373 // We keep legalizing the type until we find a legal kind. We assume that
1374 // the only operation that costs anything is the split. After splitting
1375 // we need to handle two types.
1377 LegalizeKind LK = getTypeConversion(C, MTy);
1379 if (LK.first == TypeLegal)
1380 return std::make_pair(Cost, MTy.getSimpleVT());
1382 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1385 // Keep legalizing the type.
1390 //===----------------------------------------------------------------------===//
1391 // Loop Strength Reduction hooks
1392 //===----------------------------------------------------------------------===//
1394 /// isLegalAddressingMode - Return true if the addressing mode represented
1395 /// by AM is legal for this target, for a load/store of the specified type.
1396 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1398 // The default implementation of this implements a conservative RISCy, r+r and
1401 // Allows a sign-extended 16-bit immediate field.
1402 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1405 // No global is ever allowed as a base.
1409 // Only support r+r,
1411 case 0: // "r+i" or just "i", depending on HasBaseReg.
1414 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1416 // Otherwise we have r+r or r+i.
1419 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1421 // Allow 2*r as r+r.