1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLoweringBase class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/IR/Mangler.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
40 /// InitLibcallNames - Set default libcall names.
42 static void InitLibcallNames(const char **Names, const TargetMachine &TM) {
43 Names[RTLIB::SHL_I16] = "__ashlhi3";
44 Names[RTLIB::SHL_I32] = "__ashlsi3";
45 Names[RTLIB::SHL_I64] = "__ashldi3";
46 Names[RTLIB::SHL_I128] = "__ashlti3";
47 Names[RTLIB::SRL_I16] = "__lshrhi3";
48 Names[RTLIB::SRL_I32] = "__lshrsi3";
49 Names[RTLIB::SRL_I64] = "__lshrdi3";
50 Names[RTLIB::SRL_I128] = "__lshrti3";
51 Names[RTLIB::SRA_I16] = "__ashrhi3";
52 Names[RTLIB::SRA_I32] = "__ashrsi3";
53 Names[RTLIB::SRA_I64] = "__ashrdi3";
54 Names[RTLIB::SRA_I128] = "__ashrti3";
55 Names[RTLIB::MUL_I8] = "__mulqi3";
56 Names[RTLIB::MUL_I16] = "__mulhi3";
57 Names[RTLIB::MUL_I32] = "__mulsi3";
58 Names[RTLIB::MUL_I64] = "__muldi3";
59 Names[RTLIB::MUL_I128] = "__multi3";
60 Names[RTLIB::MULO_I32] = "__mulosi4";
61 Names[RTLIB::MULO_I64] = "__mulodi4";
62 Names[RTLIB::MULO_I128] = "__muloti4";
63 Names[RTLIB::SDIV_I8] = "__divqi3";
64 Names[RTLIB::SDIV_I16] = "__divhi3";
65 Names[RTLIB::SDIV_I32] = "__divsi3";
66 Names[RTLIB::SDIV_I64] = "__divdi3";
67 Names[RTLIB::SDIV_I128] = "__divti3";
68 Names[RTLIB::UDIV_I8] = "__udivqi3";
69 Names[RTLIB::UDIV_I16] = "__udivhi3";
70 Names[RTLIB::UDIV_I32] = "__udivsi3";
71 Names[RTLIB::UDIV_I64] = "__udivdi3";
72 Names[RTLIB::UDIV_I128] = "__udivti3";
73 Names[RTLIB::SREM_I8] = "__modqi3";
74 Names[RTLIB::SREM_I16] = "__modhi3";
75 Names[RTLIB::SREM_I32] = "__modsi3";
76 Names[RTLIB::SREM_I64] = "__moddi3";
77 Names[RTLIB::SREM_I128] = "__modti3";
78 Names[RTLIB::UREM_I8] = "__umodqi3";
79 Names[RTLIB::UREM_I16] = "__umodhi3";
80 Names[RTLIB::UREM_I32] = "__umodsi3";
81 Names[RTLIB::UREM_I64] = "__umoddi3";
82 Names[RTLIB::UREM_I128] = "__umodti3";
84 // These are generally not available.
85 Names[RTLIB::SDIVREM_I8] = 0;
86 Names[RTLIB::SDIVREM_I16] = 0;
87 Names[RTLIB::SDIVREM_I32] = 0;
88 Names[RTLIB::SDIVREM_I64] = 0;
89 Names[RTLIB::SDIVREM_I128] = 0;
90 Names[RTLIB::UDIVREM_I8] = 0;
91 Names[RTLIB::UDIVREM_I16] = 0;
92 Names[RTLIB::UDIVREM_I32] = 0;
93 Names[RTLIB::UDIVREM_I64] = 0;
94 Names[RTLIB::UDIVREM_I128] = 0;
96 Names[RTLIB::NEG_I32] = "__negsi2";
97 Names[RTLIB::NEG_I64] = "__negdi2";
98 Names[RTLIB::ADD_F32] = "__addsf3";
99 Names[RTLIB::ADD_F64] = "__adddf3";
100 Names[RTLIB::ADD_F80] = "__addxf3";
101 Names[RTLIB::ADD_F128] = "__addtf3";
102 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
103 Names[RTLIB::SUB_F32] = "__subsf3";
104 Names[RTLIB::SUB_F64] = "__subdf3";
105 Names[RTLIB::SUB_F80] = "__subxf3";
106 Names[RTLIB::SUB_F128] = "__subtf3";
107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
108 Names[RTLIB::MUL_F32] = "__mulsf3";
109 Names[RTLIB::MUL_F64] = "__muldf3";
110 Names[RTLIB::MUL_F80] = "__mulxf3";
111 Names[RTLIB::MUL_F128] = "__multf3";
112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
113 Names[RTLIB::DIV_F32] = "__divsf3";
114 Names[RTLIB::DIV_F64] = "__divdf3";
115 Names[RTLIB::DIV_F80] = "__divxf3";
116 Names[RTLIB::DIV_F128] = "__divtf3";
117 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
118 Names[RTLIB::REM_F32] = "fmodf";
119 Names[RTLIB::REM_F64] = "fmod";
120 Names[RTLIB::REM_F80] = "fmodl";
121 Names[RTLIB::REM_F128] = "fmodl";
122 Names[RTLIB::REM_PPCF128] = "fmodl";
123 Names[RTLIB::FMA_F32] = "fmaf";
124 Names[RTLIB::FMA_F64] = "fma";
125 Names[RTLIB::FMA_F80] = "fmal";
126 Names[RTLIB::FMA_F128] = "fmal";
127 Names[RTLIB::FMA_PPCF128] = "fmal";
128 Names[RTLIB::POWI_F32] = "__powisf2";
129 Names[RTLIB::POWI_F64] = "__powidf2";
130 Names[RTLIB::POWI_F80] = "__powixf2";
131 Names[RTLIB::POWI_F128] = "__powitf2";
132 Names[RTLIB::POWI_PPCF128] = "__powitf2";
133 Names[RTLIB::SQRT_F32] = "sqrtf";
134 Names[RTLIB::SQRT_F64] = "sqrt";
135 Names[RTLIB::SQRT_F80] = "sqrtl";
136 Names[RTLIB::SQRT_F128] = "sqrtl";
137 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
138 Names[RTLIB::LOG_F32] = "logf";
139 Names[RTLIB::LOG_F64] = "log";
140 Names[RTLIB::LOG_F80] = "logl";
141 Names[RTLIB::LOG_F128] = "logl";
142 Names[RTLIB::LOG_PPCF128] = "logl";
143 Names[RTLIB::LOG2_F32] = "log2f";
144 Names[RTLIB::LOG2_F64] = "log2";
145 Names[RTLIB::LOG2_F80] = "log2l";
146 Names[RTLIB::LOG2_F128] = "log2l";
147 Names[RTLIB::LOG2_PPCF128] = "log2l";
148 Names[RTLIB::LOG10_F32] = "log10f";
149 Names[RTLIB::LOG10_F64] = "log10";
150 Names[RTLIB::LOG10_F80] = "log10l";
151 Names[RTLIB::LOG10_F128] = "log10l";
152 Names[RTLIB::LOG10_PPCF128] = "log10l";
153 Names[RTLIB::EXP_F32] = "expf";
154 Names[RTLIB::EXP_F64] = "exp";
155 Names[RTLIB::EXP_F80] = "expl";
156 Names[RTLIB::EXP_F128] = "expl";
157 Names[RTLIB::EXP_PPCF128] = "expl";
158 Names[RTLIB::EXP2_F32] = "exp2f";
159 Names[RTLIB::EXP2_F64] = "exp2";
160 Names[RTLIB::EXP2_F80] = "exp2l";
161 Names[RTLIB::EXP2_F128] = "exp2l";
162 Names[RTLIB::EXP2_PPCF128] = "exp2l";
163 Names[RTLIB::SIN_F32] = "sinf";
164 Names[RTLIB::SIN_F64] = "sin";
165 Names[RTLIB::SIN_F80] = "sinl";
166 Names[RTLIB::SIN_F128] = "sinl";
167 Names[RTLIB::SIN_PPCF128] = "sinl";
168 Names[RTLIB::COS_F32] = "cosf";
169 Names[RTLIB::COS_F64] = "cos";
170 Names[RTLIB::COS_F80] = "cosl";
171 Names[RTLIB::COS_F128] = "cosl";
172 Names[RTLIB::COS_PPCF128] = "cosl";
173 Names[RTLIB::POW_F32] = "powf";
174 Names[RTLIB::POW_F64] = "pow";
175 Names[RTLIB::POW_F80] = "powl";
176 Names[RTLIB::POW_F128] = "powl";
177 Names[RTLIB::POW_PPCF128] = "powl";
178 Names[RTLIB::CEIL_F32] = "ceilf";
179 Names[RTLIB::CEIL_F64] = "ceil";
180 Names[RTLIB::CEIL_F80] = "ceill";
181 Names[RTLIB::CEIL_F128] = "ceill";
182 Names[RTLIB::CEIL_PPCF128] = "ceill";
183 Names[RTLIB::TRUNC_F32] = "truncf";
184 Names[RTLIB::TRUNC_F64] = "trunc";
185 Names[RTLIB::TRUNC_F80] = "truncl";
186 Names[RTLIB::TRUNC_F128] = "truncl";
187 Names[RTLIB::TRUNC_PPCF128] = "truncl";
188 Names[RTLIB::RINT_F32] = "rintf";
189 Names[RTLIB::RINT_F64] = "rint";
190 Names[RTLIB::RINT_F80] = "rintl";
191 Names[RTLIB::RINT_F128] = "rintl";
192 Names[RTLIB::RINT_PPCF128] = "rintl";
193 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
194 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
195 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
196 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
198 Names[RTLIB::ROUND_F32] = "roundf";
199 Names[RTLIB::ROUND_F64] = "round";
200 Names[RTLIB::ROUND_F80] = "roundl";
201 Names[RTLIB::ROUND_F128] = "roundl";
202 Names[RTLIB::ROUND_PPCF128] = "roundl";
203 Names[RTLIB::FLOOR_F32] = "floorf";
204 Names[RTLIB::FLOOR_F64] = "floor";
205 Names[RTLIB::FLOOR_F80] = "floorl";
206 Names[RTLIB::FLOOR_F128] = "floorl";
207 Names[RTLIB::FLOOR_PPCF128] = "floorl";
208 Names[RTLIB::COPYSIGN_F32] = "copysignf";
209 Names[RTLIB::COPYSIGN_F64] = "copysign";
210 Names[RTLIB::COPYSIGN_F80] = "copysignl";
211 Names[RTLIB::COPYSIGN_F128] = "copysignl";
212 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
213 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
214 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
215 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
216 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
217 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
218 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
219 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
220 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
221 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
222 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
223 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
224 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
225 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
226 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
227 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
228 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
229 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
230 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
231 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
232 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
233 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
234 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
235 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
236 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
237 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
238 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
239 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
240 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
241 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
242 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
243 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
244 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
245 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
246 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
247 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
248 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
249 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
250 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
251 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
252 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
253 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
254 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
255 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
256 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
257 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
258 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
259 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
260 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
261 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
262 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
263 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
264 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
265 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
266 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
267 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
268 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
269 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
270 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
271 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
272 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
273 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
274 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
275 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
276 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
277 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
278 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
279 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
280 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
281 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
282 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
283 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
284 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
285 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
286 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
287 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
288 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
289 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
290 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
291 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
292 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
293 Names[RTLIB::OEQ_F32] = "__eqsf2";
294 Names[RTLIB::OEQ_F64] = "__eqdf2";
295 Names[RTLIB::OEQ_F128] = "__eqtf2";
296 Names[RTLIB::UNE_F32] = "__nesf2";
297 Names[RTLIB::UNE_F64] = "__nedf2";
298 Names[RTLIB::UNE_F128] = "__netf2";
299 Names[RTLIB::OGE_F32] = "__gesf2";
300 Names[RTLIB::OGE_F64] = "__gedf2";
301 Names[RTLIB::OGE_F128] = "__getf2";
302 Names[RTLIB::OLT_F32] = "__ltsf2";
303 Names[RTLIB::OLT_F64] = "__ltdf2";
304 Names[RTLIB::OLT_F128] = "__lttf2";
305 Names[RTLIB::OLE_F32] = "__lesf2";
306 Names[RTLIB::OLE_F64] = "__ledf2";
307 Names[RTLIB::OLE_F128] = "__letf2";
308 Names[RTLIB::OGT_F32] = "__gtsf2";
309 Names[RTLIB::OGT_F64] = "__gtdf2";
310 Names[RTLIB::OGT_F128] = "__gttf2";
311 Names[RTLIB::UO_F32] = "__unordsf2";
312 Names[RTLIB::UO_F64] = "__unorddf2";
313 Names[RTLIB::UO_F128] = "__unordtf2";
314 Names[RTLIB::O_F32] = "__unordsf2";
315 Names[RTLIB::O_F64] = "__unorddf2";
316 Names[RTLIB::O_F128] = "__unordtf2";
317 Names[RTLIB::MEMCPY] = "memcpy";
318 Names[RTLIB::MEMMOVE] = "memmove";
319 Names[RTLIB::MEMSET] = "memset";
320 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
321 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
322 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
323 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
324 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
325 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
326 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
327 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
328 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
329 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
330 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
331 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
332 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
333 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
334 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
335 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
336 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
337 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
338 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
339 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
340 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
341 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
342 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
343 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
344 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
345 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
346 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
347 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
348 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
349 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
350 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
351 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
352 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
353 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
354 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
355 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
356 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
357 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
358 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
359 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
360 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
361 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
362 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
363 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
364 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
365 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
366 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
367 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
368 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
369 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
370 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
371 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
372 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
373 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
374 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
375 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
376 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
377 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
378 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
379 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
380 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
382 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) {
383 Names[RTLIB::SINCOS_F32] = "sincosf";
384 Names[RTLIB::SINCOS_F64] = "sincos";
385 Names[RTLIB::SINCOS_F80] = "sincosl";
386 Names[RTLIB::SINCOS_F128] = "sincosl";
387 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
389 // These are generally not available.
390 Names[RTLIB::SINCOS_F32] = 0;
391 Names[RTLIB::SINCOS_F64] = 0;
392 Names[RTLIB::SINCOS_F80] = 0;
393 Names[RTLIB::SINCOS_F128] = 0;
394 Names[RTLIB::SINCOS_PPCF128] = 0;
397 if (Triple(TM.getTargetTriple()).getOS() != Triple::OpenBSD) {
398 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
400 // These are generally not available.
401 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = 0;
405 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
407 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
408 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
409 CCs[i] = CallingConv::C;
413 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
414 /// UNKNOWN_LIBCALL if there is none.
415 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
416 if (OpVT == MVT::f32) {
417 if (RetVT == MVT::f64)
418 return FPEXT_F32_F64;
419 if (RetVT == MVT::f128)
420 return FPEXT_F32_F128;
421 } else if (OpVT == MVT::f64) {
422 if (RetVT == MVT::f128)
423 return FPEXT_F64_F128;
426 return UNKNOWN_LIBCALL;
429 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
430 /// UNKNOWN_LIBCALL if there is none.
431 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
432 if (RetVT == MVT::f32) {
433 if (OpVT == MVT::f64)
434 return FPROUND_F64_F32;
435 if (OpVT == MVT::f80)
436 return FPROUND_F80_F32;
437 if (OpVT == MVT::f128)
438 return FPROUND_F128_F32;
439 if (OpVT == MVT::ppcf128)
440 return FPROUND_PPCF128_F32;
441 } else if (RetVT == MVT::f64) {
442 if (OpVT == MVT::f80)
443 return FPROUND_F80_F64;
444 if (OpVT == MVT::f128)
445 return FPROUND_F128_F64;
446 if (OpVT == MVT::ppcf128)
447 return FPROUND_PPCF128_F64;
450 return UNKNOWN_LIBCALL;
453 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
454 /// UNKNOWN_LIBCALL if there is none.
455 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
456 if (OpVT == MVT::f32) {
457 if (RetVT == MVT::i8)
458 return FPTOSINT_F32_I8;
459 if (RetVT == MVT::i16)
460 return FPTOSINT_F32_I16;
461 if (RetVT == MVT::i32)
462 return FPTOSINT_F32_I32;
463 if (RetVT == MVT::i64)
464 return FPTOSINT_F32_I64;
465 if (RetVT == MVT::i128)
466 return FPTOSINT_F32_I128;
467 } else if (OpVT == MVT::f64) {
468 if (RetVT == MVT::i8)
469 return FPTOSINT_F64_I8;
470 if (RetVT == MVT::i16)
471 return FPTOSINT_F64_I16;
472 if (RetVT == MVT::i32)
473 return FPTOSINT_F64_I32;
474 if (RetVT == MVT::i64)
475 return FPTOSINT_F64_I64;
476 if (RetVT == MVT::i128)
477 return FPTOSINT_F64_I128;
478 } else if (OpVT == MVT::f80) {
479 if (RetVT == MVT::i32)
480 return FPTOSINT_F80_I32;
481 if (RetVT == MVT::i64)
482 return FPTOSINT_F80_I64;
483 if (RetVT == MVT::i128)
484 return FPTOSINT_F80_I128;
485 } else if (OpVT == MVT::f128) {
486 if (RetVT == MVT::i32)
487 return FPTOSINT_F128_I32;
488 if (RetVT == MVT::i64)
489 return FPTOSINT_F128_I64;
490 if (RetVT == MVT::i128)
491 return FPTOSINT_F128_I128;
492 } else if (OpVT == MVT::ppcf128) {
493 if (RetVT == MVT::i32)
494 return FPTOSINT_PPCF128_I32;
495 if (RetVT == MVT::i64)
496 return FPTOSINT_PPCF128_I64;
497 if (RetVT == MVT::i128)
498 return FPTOSINT_PPCF128_I128;
500 return UNKNOWN_LIBCALL;
503 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
504 /// UNKNOWN_LIBCALL if there is none.
505 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
506 if (OpVT == MVT::f32) {
507 if (RetVT == MVT::i8)
508 return FPTOUINT_F32_I8;
509 if (RetVT == MVT::i16)
510 return FPTOUINT_F32_I16;
511 if (RetVT == MVT::i32)
512 return FPTOUINT_F32_I32;
513 if (RetVT == MVT::i64)
514 return FPTOUINT_F32_I64;
515 if (RetVT == MVT::i128)
516 return FPTOUINT_F32_I128;
517 } else if (OpVT == MVT::f64) {
518 if (RetVT == MVT::i8)
519 return FPTOUINT_F64_I8;
520 if (RetVT == MVT::i16)
521 return FPTOUINT_F64_I16;
522 if (RetVT == MVT::i32)
523 return FPTOUINT_F64_I32;
524 if (RetVT == MVT::i64)
525 return FPTOUINT_F64_I64;
526 if (RetVT == MVT::i128)
527 return FPTOUINT_F64_I128;
528 } else if (OpVT == MVT::f80) {
529 if (RetVT == MVT::i32)
530 return FPTOUINT_F80_I32;
531 if (RetVT == MVT::i64)
532 return FPTOUINT_F80_I64;
533 if (RetVT == MVT::i128)
534 return FPTOUINT_F80_I128;
535 } else if (OpVT == MVT::f128) {
536 if (RetVT == MVT::i32)
537 return FPTOUINT_F128_I32;
538 if (RetVT == MVT::i64)
539 return FPTOUINT_F128_I64;
540 if (RetVT == MVT::i128)
541 return FPTOUINT_F128_I128;
542 } else if (OpVT == MVT::ppcf128) {
543 if (RetVT == MVT::i32)
544 return FPTOUINT_PPCF128_I32;
545 if (RetVT == MVT::i64)
546 return FPTOUINT_PPCF128_I64;
547 if (RetVT == MVT::i128)
548 return FPTOUINT_PPCF128_I128;
550 return UNKNOWN_LIBCALL;
553 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
554 /// UNKNOWN_LIBCALL if there is none.
555 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
556 if (OpVT == MVT::i32) {
557 if (RetVT == MVT::f32)
558 return SINTTOFP_I32_F32;
559 if (RetVT == MVT::f64)
560 return SINTTOFP_I32_F64;
561 if (RetVT == MVT::f80)
562 return SINTTOFP_I32_F80;
563 if (RetVT == MVT::f128)
564 return SINTTOFP_I32_F128;
565 if (RetVT == MVT::ppcf128)
566 return SINTTOFP_I32_PPCF128;
567 } else if (OpVT == MVT::i64) {
568 if (RetVT == MVT::f32)
569 return SINTTOFP_I64_F32;
570 if (RetVT == MVT::f64)
571 return SINTTOFP_I64_F64;
572 if (RetVT == MVT::f80)
573 return SINTTOFP_I64_F80;
574 if (RetVT == MVT::f128)
575 return SINTTOFP_I64_F128;
576 if (RetVT == MVT::ppcf128)
577 return SINTTOFP_I64_PPCF128;
578 } else if (OpVT == MVT::i128) {
579 if (RetVT == MVT::f32)
580 return SINTTOFP_I128_F32;
581 if (RetVT == MVT::f64)
582 return SINTTOFP_I128_F64;
583 if (RetVT == MVT::f80)
584 return SINTTOFP_I128_F80;
585 if (RetVT == MVT::f128)
586 return SINTTOFP_I128_F128;
587 if (RetVT == MVT::ppcf128)
588 return SINTTOFP_I128_PPCF128;
590 return UNKNOWN_LIBCALL;
593 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
594 /// UNKNOWN_LIBCALL if there is none.
595 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
596 if (OpVT == MVT::i32) {
597 if (RetVT == MVT::f32)
598 return UINTTOFP_I32_F32;
599 if (RetVT == MVT::f64)
600 return UINTTOFP_I32_F64;
601 if (RetVT == MVT::f80)
602 return UINTTOFP_I32_F80;
603 if (RetVT == MVT::f128)
604 return UINTTOFP_I32_F128;
605 if (RetVT == MVT::ppcf128)
606 return UINTTOFP_I32_PPCF128;
607 } else if (OpVT == MVT::i64) {
608 if (RetVT == MVT::f32)
609 return UINTTOFP_I64_F32;
610 if (RetVT == MVT::f64)
611 return UINTTOFP_I64_F64;
612 if (RetVT == MVT::f80)
613 return UINTTOFP_I64_F80;
614 if (RetVT == MVT::f128)
615 return UINTTOFP_I64_F128;
616 if (RetVT == MVT::ppcf128)
617 return UINTTOFP_I64_PPCF128;
618 } else if (OpVT == MVT::i128) {
619 if (RetVT == MVT::f32)
620 return UINTTOFP_I128_F32;
621 if (RetVT == MVT::f64)
622 return UINTTOFP_I128_F64;
623 if (RetVT == MVT::f80)
624 return UINTTOFP_I128_F80;
625 if (RetVT == MVT::f128)
626 return UINTTOFP_I128_F128;
627 if (RetVT == MVT::ppcf128)
628 return UINTTOFP_I128_PPCF128;
630 return UNKNOWN_LIBCALL;
633 /// InitCmpLibcallCCs - Set default comparison libcall CC.
635 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
636 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
637 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
638 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
639 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
640 CCs[RTLIB::UNE_F32] = ISD::SETNE;
641 CCs[RTLIB::UNE_F64] = ISD::SETNE;
642 CCs[RTLIB::UNE_F128] = ISD::SETNE;
643 CCs[RTLIB::OGE_F32] = ISD::SETGE;
644 CCs[RTLIB::OGE_F64] = ISD::SETGE;
645 CCs[RTLIB::OGE_F128] = ISD::SETGE;
646 CCs[RTLIB::OLT_F32] = ISD::SETLT;
647 CCs[RTLIB::OLT_F64] = ISD::SETLT;
648 CCs[RTLIB::OLT_F128] = ISD::SETLT;
649 CCs[RTLIB::OLE_F32] = ISD::SETLE;
650 CCs[RTLIB::OLE_F64] = ISD::SETLE;
651 CCs[RTLIB::OLE_F128] = ISD::SETLE;
652 CCs[RTLIB::OGT_F32] = ISD::SETGT;
653 CCs[RTLIB::OGT_F64] = ISD::SETGT;
654 CCs[RTLIB::OGT_F128] = ISD::SETGT;
655 CCs[RTLIB::UO_F32] = ISD::SETNE;
656 CCs[RTLIB::UO_F64] = ISD::SETNE;
657 CCs[RTLIB::UO_F128] = ISD::SETNE;
658 CCs[RTLIB::O_F32] = ISD::SETEQ;
659 CCs[RTLIB::O_F64] = ISD::SETEQ;
660 CCs[RTLIB::O_F128] = ISD::SETEQ;
663 /// NOTE: The constructor takes ownership of TLOF.
664 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
665 const TargetLoweringObjectFile *tlof)
666 : TM(tm), DL(TM.getDataLayout()), TLOF(*tlof) {
669 // Perform these initializations only once.
670 IsLittleEndian = DL->isLittleEndian();
671 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
672 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
673 = MaxStoresPerMemmoveOptSize = 4;
674 UseUnderscoreSetJmp = false;
675 UseUnderscoreLongJmp = false;
676 SelectIsExpensive = false;
677 HasMultipleConditionRegisters = false;
678 IntDivIsCheap = false;
679 Pow2DivIsCheap = false;
680 JumpIsExpensive = false;
681 PredictableSelectIsExpensive = false;
682 MaskAndBranchFoldingIsLegal = false;
683 StackPointerRegisterToSaveRestore = 0;
684 ExceptionPointerRegister = 0;
685 ExceptionSelectorRegister = 0;
686 BooleanContents = UndefinedBooleanContent;
687 BooleanVectorContents = UndefinedBooleanContent;
688 SchedPreferenceInfo = Sched::ILP;
690 JumpBufAlignment = 0;
691 MinFunctionAlignment = 0;
692 PrefFunctionAlignment = 0;
693 PrefLoopAlignment = 0;
694 MinStackArgumentAlignment = 1;
695 InsertFencesForAtomic = false;
696 SupportJumpTables = true;
697 MinimumJumpTableEntries = 4;
699 InitLibcallNames(LibcallRoutineNames, TM);
700 InitCmpLibcallCCs(CmpLibcallCCs);
701 InitLibcallCallingConvs(LibcallCallingConvs);
704 TargetLoweringBase::~TargetLoweringBase() {
708 void TargetLoweringBase::initActions() {
709 // All operations default to being supported.
710 memset(OpActions, 0, sizeof(OpActions));
711 memset(LoadExtActions, 0, sizeof(LoadExtActions));
712 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
713 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
714 memset(CondCodeActions, 0, sizeof(CondCodeActions));
715 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
716 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
718 // Set default actions for various operations.
719 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
720 // Default all indexed load / store to expand.
721 for (unsigned IM = (unsigned)ISD::PRE_INC;
722 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
723 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
724 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
727 // These operations default to expand.
728 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
731 // These library functions default to expand.
732 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
734 // These operations default to expand for vector types.
735 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
736 VT <= MVT::LAST_VECTOR_VALUETYPE)
737 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
740 // Most targets ignore the @llvm.prefetch intrinsic.
741 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
743 // ConstantFP nodes default to expand. Targets can either change this to
744 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
745 // to optimize expansions for certain constants.
746 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
747 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
748 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
749 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
750 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
752 // These library functions default to expand.
753 setOperationAction(ISD::FLOG , MVT::f16, Expand);
754 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
755 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
756 setOperationAction(ISD::FEXP , MVT::f16, Expand);
757 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
758 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
759 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
760 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
761 setOperationAction(ISD::FRINT, MVT::f16, Expand);
762 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
763 setOperationAction(ISD::FLOG , MVT::f32, Expand);
764 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
765 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
766 setOperationAction(ISD::FEXP , MVT::f32, Expand);
767 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
768 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
769 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
770 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
771 setOperationAction(ISD::FRINT, MVT::f32, Expand);
772 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
773 setOperationAction(ISD::FLOG , MVT::f64, Expand);
774 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
775 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
776 setOperationAction(ISD::FEXP , MVT::f64, Expand);
777 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
778 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
779 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
780 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
781 setOperationAction(ISD::FRINT, MVT::f64, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
783 setOperationAction(ISD::FLOG , MVT::f128, Expand);
784 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
785 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
786 setOperationAction(ISD::FEXP , MVT::f128, Expand);
787 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
788 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
790 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
791 setOperationAction(ISD::FRINT, MVT::f128, Expand);
792 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
794 // Default ISD::TRAP to expand (which turns it into abort).
795 setOperationAction(ISD::TRAP, MVT::Other, Expand);
797 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
798 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
800 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
803 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
804 return MVT::getIntegerVT(getPointerSizeInBits(AS));
807 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
808 return DL->getPointerSizeInBits(AS);
811 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
812 assert(Ty->isPointerTy());
813 return getPointerSizeInBits(Ty->getPointerAddressSpace());
816 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
817 return MVT::getIntegerVT(8*DL->getPointerSize(0));
820 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
821 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
822 if (LHSTy.isVector())
824 return getScalarShiftAmountTy(LHSTy);
827 /// canOpTrap - Returns true if the operation can trap for the value type.
828 /// VT must be a legal type.
829 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
830 assert(isTypeLegal(VT));
845 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
846 unsigned &NumIntermediates,
848 TargetLoweringBase *TLI) {
849 // Figure out the right, legal destination reg to copy into.
850 unsigned NumElts = VT.getVectorNumElements();
851 MVT EltTy = VT.getVectorElementType();
853 unsigned NumVectorRegs = 1;
855 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
856 // could break down into LHS/RHS like LegalizeDAG does.
857 if (!isPowerOf2_32(NumElts)) {
858 NumVectorRegs = NumElts;
862 // Divide the input until we get to a supported size. This will always
863 // end with a scalar if the target doesn't support vectors.
864 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
869 NumIntermediates = NumVectorRegs;
871 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
872 if (!TLI->isTypeLegal(NewVT))
874 IntermediateVT = NewVT;
876 unsigned NewVTSize = NewVT.getSizeInBits();
878 // Convert sizes such as i33 to i64.
879 if (!isPowerOf2_32(NewVTSize))
880 NewVTSize = NextPowerOf2(NewVTSize);
882 MVT DestVT = TLI->getRegisterType(NewVT);
884 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
885 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
887 // Otherwise, promotion or legal types use the same number of registers as
888 // the vector decimated to the appropriate level.
889 return NumVectorRegs;
892 /// isLegalRC - Return true if the value types that can be represented by the
893 /// specified register class are all legal.
894 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
895 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
903 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
904 /// sequence of memory operands that is recognized by PrologEpilogInserter.
906 TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
907 MachineBasicBlock *MBB) const {
908 const TargetMachine &TM = getTargetMachine();
909 MachineFunction &MF = *MI->getParent()->getParent();
911 // MI changes inside this loop as we grow operands.
912 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
913 MachineOperand &MO = MI->getOperand(OperIdx);
917 // foldMemoryOperand builds a new MI after replacing a single FI operand
918 // with the canonical set of five x86 addressing-mode operands.
919 int FI = MO.getIndex();
920 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
922 // Copy operands before the frame-index.
923 for (unsigned i = 0; i < OperIdx; ++i)
924 MIB.addOperand(MI->getOperand(i));
925 // Add frame index operands: direct-mem-ref tag, #FI, offset.
926 MIB.addImm(StackMaps::DirectMemRefOp);
927 MIB.addOperand(MI->getOperand(OperIdx));
929 // Copy the operands after the frame index.
930 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
931 MIB.addOperand(MI->getOperand(i));
933 // Inherit previous memory operands.
934 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
935 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
937 // Add a new memory operand for this FI.
938 const MachineFrameInfo &MFI = *MF.getFrameInfo();
939 assert(MFI.getObjectOffset(FI) != -1);
940 MachineMemOperand *MMO =
941 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
942 MachineMemOperand::MOLoad,
943 TM.getDataLayout()->getPointerSize(),
944 MFI.getObjectAlignment(FI));
945 MIB->addMemOperand(MF, MMO);
947 // Replace the instruction and update the operand index.
948 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
949 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
950 MI->eraseFromParent();
956 /// findRepresentativeClass - Return the largest legal super-reg register class
957 /// of the register class for the specified type and its associated "cost".
958 std::pair<const TargetRegisterClass*, uint8_t>
959 TargetLoweringBase::findRepresentativeClass(MVT VT) const {
960 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
961 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
963 return std::make_pair(RC, 0);
965 // Compute the set of all super-register classes.
966 BitVector SuperRegRC(TRI->getNumRegClasses());
967 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
968 SuperRegRC.setBitsInMask(RCI.getMask());
970 // Find the first legal register class with the largest spill size.
971 const TargetRegisterClass *BestRC = RC;
972 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
973 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
974 // We want the largest possible spill size.
975 if (SuperRC->getSize() <= BestRC->getSize())
977 if (!isLegalRC(SuperRC))
981 return std::make_pair(BestRC, 1);
984 /// computeRegisterProperties - Once all of the register classes are added,
985 /// this allows us to compute derived properties we expose.
986 void TargetLoweringBase::computeRegisterProperties() {
987 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
988 "Too many value types for ValueTypeActions to hold!");
990 // Everything defaults to needing one register.
991 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
992 NumRegistersForVT[i] = 1;
993 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
995 // ...except isVoid, which doesn't need any registers.
996 NumRegistersForVT[MVT::isVoid] = 0;
998 // Find the largest integer register class.
999 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1000 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
1001 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1003 // Every integer value type larger than this largest register takes twice as
1004 // many registers to represent as the previous ValueType.
1005 for (unsigned ExpandedReg = LargestIntReg + 1;
1006 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1007 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1008 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1009 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1010 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1014 // Inspect all of the ValueType's smaller than the largest integer
1015 // register to see which ones need promotion.
1016 unsigned LegalIntReg = LargestIntReg;
1017 for (unsigned IntReg = LargestIntReg - 1;
1018 IntReg >= (unsigned)MVT::i1; --IntReg) {
1019 MVT IVT = (MVT::SimpleValueType)IntReg;
1020 if (isTypeLegal(IVT)) {
1021 LegalIntReg = IntReg;
1023 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1024 (const MVT::SimpleValueType)LegalIntReg;
1025 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1029 // ppcf128 type is really two f64's.
1030 if (!isTypeLegal(MVT::ppcf128)) {
1031 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1032 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1033 TransformToType[MVT::ppcf128] = MVT::f64;
1034 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1037 // Decide how to handle f128. If the target does not have native f128 support,
1038 // expand it to i128 and we will be generating soft float library calls.
1039 if (!isTypeLegal(MVT::f128)) {
1040 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1041 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1042 TransformToType[MVT::f128] = MVT::i128;
1043 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1046 // Decide how to handle f64. If the target does not have native f64 support,
1047 // expand it to i64 and we will be generating soft float library calls.
1048 if (!isTypeLegal(MVT::f64)) {
1049 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1050 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1051 TransformToType[MVT::f64] = MVT::i64;
1052 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1055 // Decide how to handle f32. If the target does not have native support for
1056 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1057 if (!isTypeLegal(MVT::f32)) {
1058 if (isTypeLegal(MVT::f64)) {
1059 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1060 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1061 TransformToType[MVT::f32] = MVT::f64;
1062 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1064 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1065 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1066 TransformToType[MVT::f32] = MVT::i32;
1067 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1071 // Loop over all of the vector value types to see which need transformations.
1072 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1073 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1074 MVT VT = (MVT::SimpleValueType)i;
1075 if (isTypeLegal(VT)) continue;
1077 // Determine if there is a legal wider type. If so, we should promote to
1078 // that wider vector type.
1079 MVT EltVT = VT.getVectorElementType();
1080 unsigned NElts = VT.getVectorNumElements();
1081 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
1082 bool IsLegalWiderType = false;
1083 // First try to promote the elements of integer vectors. If no legal
1084 // promotion was found, fallback to the widen-vector method.
1085 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1086 MVT SVT = (MVT::SimpleValueType)nVT;
1087 // Promote vectors of integers to vectors with the same number
1088 // of elements, with a wider element type.
1089 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1090 && SVT.getVectorNumElements() == NElts &&
1091 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
1092 TransformToType[i] = SVT;
1093 RegisterTypeForVT[i] = SVT;
1094 NumRegistersForVT[i] = 1;
1095 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1096 IsLegalWiderType = true;
1101 if (IsLegalWiderType) continue;
1103 // Try to widen the vector.
1104 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1105 MVT SVT = (MVT::SimpleValueType)nVT;
1106 if (SVT.getVectorElementType() == EltVT &&
1107 SVT.getVectorNumElements() > NElts &&
1109 TransformToType[i] = SVT;
1110 RegisterTypeForVT[i] = SVT;
1111 NumRegistersForVT[i] = 1;
1112 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1113 IsLegalWiderType = true;
1117 if (IsLegalWiderType) continue;
1122 unsigned NumIntermediates;
1123 NumRegistersForVT[i] =
1124 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
1126 RegisterTypeForVT[i] = RegisterVT;
1128 MVT NVT = VT.getPow2VectorType();
1130 // Type is already a power of 2. The default action is to split.
1131 TransformToType[i] = MVT::Other;
1132 unsigned NumElts = VT.getVectorNumElements();
1133 ValueTypeActions.setTypeAction(VT,
1134 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
1136 TransformToType[i] = NVT;
1137 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1141 // Determine the 'representative' register class for each value type.
1142 // An representative register class is the largest (meaning one which is
1143 // not a sub-register class / subreg register class) legal register class for
1144 // a group of value types. For example, on i386, i8, i16, and i32
1145 // representative would be GR32; while on x86_64 it's GR64.
1146 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1147 const TargetRegisterClass* RRC;
1149 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1150 RepRegClassForVT[i] = RRC;
1151 RepRegClassCostForVT[i] = Cost;
1155 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
1156 assert(!VT.isVector() && "No default SetCC type for vectors!");
1157 return getPointerTy(0).SimpleTy;
1160 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1161 return MVT::i32; // return the default value
1164 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1165 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1166 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1167 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1169 /// This method returns the number of registers needed, and the VT for each
1170 /// register. It also returns the VT and quantity of the intermediate values
1171 /// before they are promoted/expanded.
1173 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1174 EVT &IntermediateVT,
1175 unsigned &NumIntermediates,
1176 MVT &RegisterVT) const {
1177 unsigned NumElts = VT.getVectorNumElements();
1179 // If there is a wider vector type with the same element type as this one,
1180 // or a promoted vector type that has the same number of elements which
1181 // are wider, then we should convert to that legal vector type.
1182 // This handles things like <2 x float> -> <4 x float> and
1183 // <4 x i1> -> <4 x i32>.
1184 LegalizeTypeAction TA = getTypeAction(Context, VT);
1185 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1186 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1187 if (isTypeLegal(RegisterEVT)) {
1188 IntermediateVT = RegisterEVT;
1189 RegisterVT = RegisterEVT.getSimpleVT();
1190 NumIntermediates = 1;
1195 // Figure out the right, legal destination reg to copy into.
1196 EVT EltTy = VT.getVectorElementType();
1198 unsigned NumVectorRegs = 1;
1200 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1201 // could break down into LHS/RHS like LegalizeDAG does.
1202 if (!isPowerOf2_32(NumElts)) {
1203 NumVectorRegs = NumElts;
1207 // Divide the input until we get to a supported size. This will always
1208 // end with a scalar if the target doesn't support vectors.
1209 while (NumElts > 1 && !isTypeLegal(
1210 EVT::getVectorVT(Context, EltTy, NumElts))) {
1212 NumVectorRegs <<= 1;
1215 NumIntermediates = NumVectorRegs;
1217 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1218 if (!isTypeLegal(NewVT))
1220 IntermediateVT = NewVT;
1222 MVT DestVT = getRegisterType(Context, NewVT);
1223 RegisterVT = DestVT;
1224 unsigned NewVTSize = NewVT.getSizeInBits();
1226 // Convert sizes such as i33 to i64.
1227 if (!isPowerOf2_32(NewVTSize))
1228 NewVTSize = NextPowerOf2(NewVTSize);
1230 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1231 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1233 // Otherwise, promotion or legal types use the same number of registers as
1234 // the vector decimated to the appropriate level.
1235 return NumVectorRegs;
1238 /// Get the EVTs and ArgFlags collections that represent the legalized return
1239 /// type of the given function. This does not require a DAG or a return value,
1240 /// and is suitable for use before any DAGs for the function are constructed.
1241 /// TODO: Move this out of TargetLowering.cpp.
1242 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1243 SmallVectorImpl<ISD::OutputArg> &Outs,
1244 const TargetLowering &TLI) {
1245 SmallVector<EVT, 4> ValueVTs;
1246 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1247 unsigned NumValues = ValueVTs.size();
1248 if (NumValues == 0) return;
1250 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1251 EVT VT = ValueVTs[j];
1252 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1254 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1255 ExtendKind = ISD::SIGN_EXTEND;
1256 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1257 ExtendKind = ISD::ZERO_EXTEND;
1259 // FIXME: C calling convention requires the return type to be promoted to
1260 // at least 32-bit. But this is not necessary for non-C calling
1261 // conventions. The frontend should mark functions whose return values
1262 // require promoting with signext or zeroext attributes.
1263 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1264 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1265 if (VT.bitsLT(MinVT))
1269 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1270 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1272 // 'inreg' on function refers to return value
1273 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1274 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1277 // Propagate extension type if any
1278 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1280 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1283 for (unsigned i = 0; i < NumParts; ++i)
1284 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1288 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1289 /// function arguments in the caller parameter area. This is the actual
1290 /// alignment, not its logarithm.
1291 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
1292 return DL->getABITypeAlignment(Ty);
1295 //===----------------------------------------------------------------------===//
1296 // TargetTransformInfo Helpers
1297 //===----------------------------------------------------------------------===//
1299 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1300 enum InstructionOpcodes {
1301 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1302 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1303 #include "llvm/IR/Instruction.def"
1305 switch (static_cast<InstructionOpcodes>(Opcode)) {
1308 case Switch: return 0;
1309 case IndirectBr: return 0;
1310 case Invoke: return 0;
1311 case Resume: return 0;
1312 case Unreachable: return 0;
1313 case Add: return ISD::ADD;
1314 case FAdd: return ISD::FADD;
1315 case Sub: return ISD::SUB;
1316 case FSub: return ISD::FSUB;
1317 case Mul: return ISD::MUL;
1318 case FMul: return ISD::FMUL;
1319 case UDiv: return ISD::UDIV;
1320 case SDiv: return ISD::UDIV;
1321 case FDiv: return ISD::FDIV;
1322 case URem: return ISD::UREM;
1323 case SRem: return ISD::SREM;
1324 case FRem: return ISD::FREM;
1325 case Shl: return ISD::SHL;
1326 case LShr: return ISD::SRL;
1327 case AShr: return ISD::SRA;
1328 case And: return ISD::AND;
1329 case Or: return ISD::OR;
1330 case Xor: return ISD::XOR;
1331 case Alloca: return 0;
1332 case Load: return ISD::LOAD;
1333 case Store: return ISD::STORE;
1334 case GetElementPtr: return 0;
1335 case Fence: return 0;
1336 case AtomicCmpXchg: return 0;
1337 case AtomicRMW: return 0;
1338 case Trunc: return ISD::TRUNCATE;
1339 case ZExt: return ISD::ZERO_EXTEND;
1340 case SExt: return ISD::SIGN_EXTEND;
1341 case FPToUI: return ISD::FP_TO_UINT;
1342 case FPToSI: return ISD::FP_TO_SINT;
1343 case UIToFP: return ISD::UINT_TO_FP;
1344 case SIToFP: return ISD::SINT_TO_FP;
1345 case FPTrunc: return ISD::FP_ROUND;
1346 case FPExt: return ISD::FP_EXTEND;
1347 case PtrToInt: return ISD::BITCAST;
1348 case IntToPtr: return ISD::BITCAST;
1349 case BitCast: return ISD::BITCAST;
1350 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1351 case ICmp: return ISD::SETCC;
1352 case FCmp: return ISD::SETCC;
1354 case Call: return 0;
1355 case Select: return ISD::SELECT;
1356 case UserOp1: return 0;
1357 case UserOp2: return 0;
1358 case VAArg: return 0;
1359 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1360 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1361 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1362 case ExtractValue: return ISD::MERGE_VALUES;
1363 case InsertValue: return ISD::MERGE_VALUES;
1364 case LandingPad: return 0;
1367 llvm_unreachable("Unknown instruction type encountered!");
1370 std::pair<unsigned, MVT>
1371 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1372 LLVMContext &C = Ty->getContext();
1373 EVT MTy = getValueType(Ty);
1376 // We keep legalizing the type until we find a legal kind. We assume that
1377 // the only operation that costs anything is the split. After splitting
1378 // we need to handle two types.
1380 LegalizeKind LK = getTypeConversion(C, MTy);
1382 if (LK.first == TypeLegal)
1383 return std::make_pair(Cost, MTy.getSimpleVT());
1385 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1388 // Keep legalizing the type.
1393 //===----------------------------------------------------------------------===//
1394 // Loop Strength Reduction hooks
1395 //===----------------------------------------------------------------------===//
1397 /// isLegalAddressingMode - Return true if the addressing mode represented
1398 /// by AM is legal for this target, for a load/store of the specified type.
1399 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1401 // The default implementation of this implements a conservative RISCy, r+r and
1404 // Allows a sign-extended 16-bit immediate field.
1405 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1408 // No global is ever allowed as a base.
1412 // Only support r+r,
1414 case 0: // "r+i" or just "i", depending on HasBaseReg.
1417 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1419 // Otherwise we have r+r or r+i.
1422 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1424 // Allow 2*r as r+r.
1426 default: // Don't allow n * r