1 //===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/TargetSchedule.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/Support/CommandLine.h"
23 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
24 cl::desc("Use TargetSchedModel for latency lookup"));
26 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
27 cl::desc("Use InstrItineraryData for latency lookup"));
29 void TargetSchedModel::init(const MCSchedModel &sm,
30 const TargetSubtargetInfo *sti,
31 const TargetInstrInfo *tii) {
35 STI->initInstrItins(InstrItins);
38 /// If we can determine the operand latency from the def only, without machine
39 /// model or itinerary lookup, do so. Otherwise return -1.
40 int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
43 // Return a latency based on the itinerary properties and defining instruction
44 // if possible. Some common subtargets don't require per-operand latency,
45 // especially for minimum latencies.
47 // If MinLatency is invalid, then use the itinerary for MinLatency. If no
48 // itinerary exists either, then use single cycle latency.
49 if (SchedModel.MinLatency < 0
50 && !(EnableSchedItins && hasInstrItineraries())) {
53 return SchedModel.MinLatency;
55 else if (!(EnableSchedModel && hasInstrSchedModel())
56 && !(EnableSchedItins && hasInstrItineraries())) {
57 return TII->defaultDefLatency(&SchedModel, DefMI);
59 // ...operand lookup required
63 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
64 /// evaluation of predicates that depend on instruction operands or flags.
65 const MCSchedClassDesc *TargetSchedModel::
66 resolveSchedClass(const MachineInstr *MI) const {
68 // Get the definition's scheduling class descriptor from this machine model.
69 unsigned SchedClass = MI->getDesc().getSchedClass();
70 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
75 while (SCDesc->isVariant()) {
76 assert(++NIter < 6 && "Variants are nested deeper than the magic number");
78 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
79 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
84 /// Find the def index of this operand. This index maps to the machine model and
85 /// is independent of use operands. Def operands may be reordered with uses or
86 /// merged with uses without affecting the def index (e.g. before/after
87 /// regalloc). However, an instruction's def operands must never be reordered
88 /// with respect to each other.
89 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
91 for (unsigned i = 0; i != DefOperIdx; ++i) {
92 const MachineOperand &MO = MI->getOperand(i);
93 if (MO.isReg() && MO.isDef())
99 /// Find the use index of this operand. This is independent of the instruction's
101 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
103 for (unsigned i = 0; i != UseOperIdx; ++i) {
104 const MachineOperand &MO = MI->getOperand(i);
105 if (MO.isReg() && MO.isUse())
111 // Top-level API for clients that know the operand indices.
112 unsigned TargetSchedModel::computeOperandLatency(
113 const MachineInstr *DefMI, unsigned DefOperIdx,
114 const MachineInstr *UseMI, unsigned UseOperIdx,
115 bool FindMin) const {
117 int DefLatency = getDefLatency(DefMI, FindMin);
121 if (!FindMin && EnableSchedModel && hasInstrSchedModel()) {
122 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
123 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
124 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
126 // Lookup the definition's write latency in SubtargetInfo.
127 const MCWriteLatencyEntry *WLEntry =
128 STI->getWriteLatencyEntry(SCDesc, DefIdx);
129 unsigned WriteID = WLEntry->WriteResourceID;
130 unsigned Latency = WLEntry->Cycles;
134 // Lookup the use's latency adjustment in SubtargetInfo.
135 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
136 if (UseDesc->NumReadAdvanceEntries == 0)
138 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
139 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
141 // If DefIdx does not exist in the model (e.g. implicit defs), then return
142 // unit latency (defaultDefLatency may be too conservative).
143 // TODO: For unknown defs, we may want to use the subtarget's model
144 // for WAW latency here instead of 1 cycle.
145 assert((!SCDesc->isValid() || DefMI->getOperand(DefOperIdx).isImplicit()) &&
146 "DefIdx exceeds machine model def operand list");
149 assert(EnableSchedItins && hasInstrItineraries() &&
150 "operand latency requires itinerary");
155 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
158 unsigned DefClass = DefMI->getDesc().getSchedClass();
159 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
161 if (OperLatency >= 0)
164 // No operand latency was found.
165 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
167 // Expected latency is the max of the stage latency and itinerary props.
169 InstrLatency = std::max(InstrLatency,
170 TII->defaultDefLatency(&SchedModel, DefMI));