1 //===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/TargetSchedule.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/raw_ostream.h"
25 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
26 cl::desc("Use TargetSchedModel for latency lookup"));
28 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
29 cl::desc("Use InstrItineraryData for latency lookup"));
31 bool TargetSchedModel::hasInstrSchedModel() const {
32 return EnableSchedModel && SchedModel.hasInstrSchedModel();
35 bool TargetSchedModel::hasInstrItineraries() const {
36 return EnableSchedItins && !InstrItins.isEmpty();
39 void TargetSchedModel::init(const MCSchedModel &sm,
40 const TargetSubtargetInfo *sti,
41 const TargetInstrInfo *tii) {
45 STI->initInstrItins(InstrItins);
48 unsigned TargetSchedModel::getNumMicroOps(MachineInstr *MI) const {
49 if (hasInstrItineraries()) {
50 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
51 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
53 if (hasInstrSchedModel()) {
54 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
55 if (SCDesc->isValid())
56 return SCDesc->NumMicroOps;
58 return MI->isTransient() ? 0 : 1;
61 /// If we can determine the operand latency from the def only, without machine
62 /// model or itinerary lookup, do so. Otherwise return -1.
63 int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
66 // Return a latency based on the itinerary properties and defining instruction
67 // if possible. Some common subtargets don't require per-operand latency,
68 // especially for minimum latencies.
70 // If MinLatency is invalid, then use the itinerary for MinLatency. If no
71 // itinerary exists either, then use single cycle latency.
72 if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
75 return SchedModel.MinLatency;
77 else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
78 return TII->defaultDefLatency(&SchedModel, DefMI);
80 // ...operand lookup required
84 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
85 /// evaluation of predicates that depend on instruction operands or flags.
86 const MCSchedClassDesc *TargetSchedModel::
87 resolveSchedClass(const MachineInstr *MI) const {
89 // Get the definition's scheduling class descriptor from this machine model.
90 unsigned SchedClass = MI->getDesc().getSchedClass();
91 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
96 while (SCDesc->isVariant()) {
97 assert(++NIter < 6 && "Variants are nested deeper than the magic number");
99 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
100 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
105 /// Find the def index of this operand. This index maps to the machine model and
106 /// is independent of use operands. Def operands may be reordered with uses or
107 /// merged with uses without affecting the def index (e.g. before/after
108 /// regalloc). However, an instruction's def operands must never be reordered
109 /// with respect to each other.
110 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
112 for (unsigned i = 0; i != DefOperIdx; ++i) {
113 const MachineOperand &MO = MI->getOperand(i);
114 if (MO.isReg() && MO.isDef())
120 /// Find the use index of this operand. This is independent of the instruction's
123 /// Note that uses are not determined by the operand's isUse property, which
124 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
125 /// a "use". The machine model allows an operand to be both a Def and Use.
126 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
128 for (unsigned i = 0; i != UseOperIdx; ++i) {
129 const MachineOperand &MO = MI->getOperand(i);
130 if (MO.isReg() && MO.readsReg())
136 // Top-level API for clients that know the operand indices.
137 unsigned TargetSchedModel::computeOperandLatency(
138 const MachineInstr *DefMI, unsigned DefOperIdx,
139 const MachineInstr *UseMI, unsigned UseOperIdx,
140 bool FindMin) const {
142 int DefLatency = getDefLatency(DefMI, FindMin);
146 if (hasInstrItineraries()) {
150 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
153 unsigned DefClass = DefMI->getDesc().getSchedClass();
154 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
156 if (OperLatency >= 0)
159 // No operand latency was found.
160 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
162 // Expected latency is the max of the stage latency and itinerary props.
163 // Rather than directly querying InstrItins stage latency, we call a TII
164 // hook to allow subtargets to specialize latency. This hook is only
165 // applicable to the InstrItins model. InstrSchedModel should model all
166 // special cases without TII hooks.
168 InstrLatency = std::max(InstrLatency,
169 TII->defaultDefLatency(&SchedModel, DefMI));
172 assert(!FindMin && hasInstrSchedModel() &&
173 "Expected a SchedModel for this cpu");
174 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
175 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
176 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
177 // Lookup the definition's write latency in SubtargetInfo.
178 const MCWriteLatencyEntry *WLEntry =
179 STI->getWriteLatencyEntry(SCDesc, DefIdx);
180 unsigned WriteID = WLEntry->WriteResourceID;
181 unsigned Latency = WLEntry->Cycles;
185 // Lookup the use's latency adjustment in SubtargetInfo.
186 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
187 if (UseDesc->NumReadAdvanceEntries == 0)
189 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
190 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
192 // If DefIdx does not exist in the model (e.g. implicit defs), then return
193 // unit latency (defaultDefLatency may be too conservative).
195 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
196 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
198 raw_string_ostream ss(Err);
199 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
201 report_fatal_error(ss.str());
204 return DefMI->isTransient() ? 0 : 1;
207 unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
208 // For the itinerary model, fall back to the old subtarget hook.
209 // Allow subtargets to compute Bundle latencies outside the machine model.
210 if (hasInstrItineraries() || MI->isBundle())
211 return TII->getInstrLatency(&InstrItins, MI);
213 if (hasInstrSchedModel()) {
214 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
215 if (SCDesc->isValid()) {
216 unsigned Latency = 0;
217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
218 DefIdx != DefEnd; ++DefIdx) {
219 // Lookup the definition's write latency in SubtargetInfo.
220 const MCWriteLatencyEntry *WLEntry =
221 STI->getWriteLatencyEntry(SCDesc, DefIdx);
222 Latency = std::max(Latency, WLEntry->Cycles);
227 return TII->defaultDefLatency(&SchedModel, MI);
230 unsigned TargetSchedModel::
231 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
232 const MachineInstr *DepMI) const {
233 // MinLatency == -1 is for in-order processors that always have unit
234 // MinLatency. MinLatency > 0 is for in-order processors with varying min
235 // latencies, but since this is not a RAW dep, we always use unit latency.
236 if (SchedModel.MinLatency != 0)
239 // MinLatency == 0 indicates an out-of-order processor that can dispatch
240 // WAW dependencies in the same cycle.
242 // Treat predication as a data dependency for out-of-order cpus. In-order
243 // cpus do not need to treat predicated writes specially.
245 // TODO: The following hack exists because predication passes do not
246 // correctly append imp-use operands, and readsReg() strangely returns false
247 // for predicated defs.
248 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
249 const MachineFunction &MF = *DefMI->getParent()->getParent();
250 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
251 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
252 return computeInstrLatency(DefMI);
254 // If we have a per operand scheduling model, check if this def is writing
255 // an unbuffered resource. If so, it treated like an in-order cpu.
256 if (hasInstrSchedModel()) {
257 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
258 if (SCDesc->isValid()) {
259 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
260 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
261 if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)