1 //===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/TargetSchedule.h"
16 #include "llvm/Support/CommandLine.h"
17 #include "llvm/Support/raw_ostream.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
25 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
26 cl::desc("Use TargetSchedModel for latency lookup"));
28 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
29 cl::desc("Use InstrItineraryData for latency lookup"));
31 bool TargetSchedModel::hasInstrSchedModel() const {
32 return EnableSchedModel && SchedModel.hasInstrSchedModel();
35 bool TargetSchedModel::hasInstrItineraries() const {
36 return EnableSchedItins && !InstrItins.isEmpty();
39 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
40 // Dividend and Divisor will be naturally swapped as needed.
42 unsigned Rem = Dividend % Divisor;
48 static unsigned lcm(unsigned A, unsigned B) {
49 unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
50 assert((LCM >= A && LCM >= B) && "LCM overflow");
54 void TargetSchedModel::init(const MCSchedModel &sm,
55 const TargetSubtargetInfo *sti,
56 const TargetInstrInfo *tii) {
60 STI->initInstrItins(InstrItins);
62 unsigned NumRes = SchedModel.getNumProcResourceKinds();
63 ResourceFactors.resize(NumRes);
64 ResourceLCM = SchedModel.IssueWidth;
65 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
66 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
68 ResourceLCM = lcm(ResourceLCM, NumUnits);
70 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
71 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
72 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
73 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
77 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
78 const MCSchedClassDesc *SC) const {
79 if (hasInstrItineraries()) {
80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
83 if (hasInstrSchedModel()) {
85 SC = resolveSchedClass(MI);
87 return SC->NumMicroOps;
89 return MI->isTransient() ? 0 : 1;
92 // The machine model may explicitly specify an invalid latency, which
93 // effectively means infinite latency. Since users of the TargetSchedule API
94 // don't know how to handle this, we convert it to a very large latency that is
95 // easy to distinguish when debugging the DAG but won't induce overflow.
96 static unsigned convertLatency(int Cycles) {
97 return Cycles >= 0 ? Cycles : 1000;
100 /// If we can determine the operand latency from the def only, without machine
101 /// model or itinerary lookup, do so. Otherwise return -1.
102 int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
103 bool FindMin) const {
105 // Return a latency based on the itinerary properties and defining instruction
106 // if possible. Some common subtargets don't require per-operand latency,
107 // especially for minimum latencies.
109 // If MinLatency is invalid, then use the itinerary for MinLatency. If no
110 // itinerary exists either, then use single cycle latency.
111 if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
114 return SchedModel.MinLatency;
116 else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
117 return TII->defaultDefLatency(&SchedModel, DefMI);
119 // ...operand lookup required
123 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
124 /// evaluation of predicates that depend on instruction operands or flags.
125 const MCSchedClassDesc *TargetSchedModel::
126 resolveSchedClass(const MachineInstr *MI) const {
128 // Get the definition's scheduling class descriptor from this machine model.
129 unsigned SchedClass = MI->getDesc().getSchedClass();
130 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
135 while (SCDesc->isVariant()) {
136 assert(++NIter < 6 && "Variants are nested deeper than the magic number");
138 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
139 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
144 /// Find the def index of this operand. This index maps to the machine model and
145 /// is independent of use operands. Def operands may be reordered with uses or
146 /// merged with uses without affecting the def index (e.g. before/after
147 /// regalloc). However, an instruction's def operands must never be reordered
148 /// with respect to each other.
149 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
151 for (unsigned i = 0; i != DefOperIdx; ++i) {
152 const MachineOperand &MO = MI->getOperand(i);
153 if (MO.isReg() && MO.isDef())
159 /// Find the use index of this operand. This is independent of the instruction's
162 /// Note that uses are not determined by the operand's isUse property, which
163 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
164 /// a "use". The machine model allows an operand to be both a Def and Use.
165 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
167 for (unsigned i = 0; i != UseOperIdx; ++i) {
168 const MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.readsReg())
175 // Top-level API for clients that know the operand indices.
176 unsigned TargetSchedModel::computeOperandLatency(
177 const MachineInstr *DefMI, unsigned DefOperIdx,
178 const MachineInstr *UseMI, unsigned UseOperIdx,
179 bool FindMin) const {
181 int DefLatency = getDefLatency(DefMI, FindMin);
185 if (hasInstrItineraries()) {
189 TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
192 unsigned DefClass = DefMI->getDesc().getSchedClass();
193 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
195 if (OperLatency >= 0)
198 // No operand latency was found.
199 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
201 // Expected latency is the max of the stage latency and itinerary props.
202 // Rather than directly querying InstrItins stage latency, we call a TII
203 // hook to allow subtargets to specialize latency. This hook is only
204 // applicable to the InstrItins model. InstrSchedModel should model all
205 // special cases without TII hooks.
207 InstrLatency = std::max(InstrLatency,
208 TII->defaultDefLatency(&SchedModel, DefMI));
211 assert(!FindMin && hasInstrSchedModel() &&
212 "Expected a SchedModel for this cpu");
213 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
214 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
215 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
216 // Lookup the definition's write latency in SubtargetInfo.
217 const MCWriteLatencyEntry *WLEntry =
218 STI->getWriteLatencyEntry(SCDesc, DefIdx);
219 unsigned WriteID = WLEntry->WriteResourceID;
220 unsigned Latency = convertLatency(WLEntry->Cycles);
224 // Lookup the use's latency adjustment in SubtargetInfo.
225 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
226 if (UseDesc->NumReadAdvanceEntries == 0)
228 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
231 // If DefIdx does not exist in the model (e.g. implicit defs), then return
232 // unit latency (defaultDefLatency may be too conservative).
234 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
235 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
237 raw_string_ostream ss(Err);
238 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
240 report_fatal_error(ss.str());
243 return DefMI->isTransient() ? 0 : 1;
246 unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
247 // For the itinerary model, fall back to the old subtarget hook.
248 // Allow subtargets to compute Bundle latencies outside the machine model.
249 if (hasInstrItineraries() || MI->isBundle())
250 return TII->getInstrLatency(&InstrItins, MI);
252 if (hasInstrSchedModel()) {
253 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
254 if (SCDesc->isValid()) {
255 unsigned Latency = 0;
256 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
257 DefIdx != DefEnd; ++DefIdx) {
258 // Lookup the definition's write latency in SubtargetInfo.
259 const MCWriteLatencyEntry *WLEntry =
260 STI->getWriteLatencyEntry(SCDesc, DefIdx);
261 Latency = std::max(Latency, convertLatency(WLEntry->Cycles));
266 return TII->defaultDefLatency(&SchedModel, MI);
269 unsigned TargetSchedModel::
270 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
271 const MachineInstr *DepMI) const {
272 // MinLatency == -1 is for in-order processors that always have unit
273 // MinLatency. MinLatency > 0 is for in-order processors with varying min
274 // latencies, but since this is not a RAW dep, we always use unit latency.
275 if (SchedModel.MinLatency != 0)
278 // MinLatency == 0 indicates an out-of-order processor that can dispatch
279 // WAW dependencies in the same cycle.
281 // Treat predication as a data dependency for out-of-order cpus. In-order
282 // cpus do not need to treat predicated writes specially.
284 // TODO: The following hack exists because predication passes do not
285 // correctly append imp-use operands, and readsReg() strangely returns false
286 // for predicated defs.
287 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
288 const MachineFunction &MF = *DefMI->getParent()->getParent();
289 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
290 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
291 return computeInstrLatency(DefMI);
293 // If we have a per operand scheduling model, check if this def is writing
294 // an unbuffered resource. If so, it treated like an in-order cpu.
295 if (hasInstrSchedModel()) {
296 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
297 if (SCDesc->isValid()) {
298 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
299 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
300 if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)