1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "Support/Debug.h"
41 #include "Support/Statistic.h"
42 #include "Support/STLExtras.h"
46 Statistic<> numTwoAddressInstrs("twoaddressinstruction",
47 "Number of two-address instructions");
49 struct TwoAddressInstructionPass : public MachineFunctionPass {
50 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
52 /// runOnMachineFunction - pass entry point
53 bool runOnMachineFunction(MachineFunction&);
56 RegisterPass<TwoAddressInstructionPass>
57 X("twoaddressinstruction", "Two-Address instruction pass");
60 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
62 void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addPreserved<LiveVariables>();
64 AU.addPreservedID(PHIEliminationID);
65 MachineFunctionPass::getAnalysisUsage(AU);
68 /// runOnMachineFunction - Reduce two-address instructions to two
71 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
72 DEBUG(std::cerr << "Machine Function\n");
73 const TargetMachine &TM = MF.getTarget();
74 const MRegisterInfo &MRI = *TM.getRegisterInfo();
75 const TargetInstrInfo &TII = *TM.getInstrInfo();
76 LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
78 bool MadeChange = false;
80 DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
81 DEBUG(std::cerr << "********** Function: "
82 << MF.getFunction()->getName() << '\n');
84 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
85 mbbi != mbbe; ++mbbi) {
86 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
88 unsigned opcode = mi->getOpcode();
90 // ignore if it is not a two-address instruction
91 if (!TII.isTwoAddrInstr(opcode))
94 ++numTwoAddressInstrs;
95 DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
96 assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
97 mi->getOperand(1).isUse() && "two address instruction invalid");
99 // if the two operands are the same we just remove the use
100 // and mark the def as def&use, otherwise we have to insert a copy.
101 if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
107 unsigned regA = mi->getOperand(0).getReg();
108 unsigned regB = mi->getOperand(1).getReg();
110 assert(MRegisterInfo::isVirtualRegister(regA) &&
111 MRegisterInfo::isVirtualRegister(regB) &&
112 "cannot update physical register live information");
114 // first make sure we do not have a use of a in the
115 // instruction (a = b + a for example) because our
116 // transformation will not work. This should never occur
117 // because we are in SSA form.
119 for (unsigned i = 1; i != mi->getNumOperands(); ++i)
120 assert(!mi->getOperand(i).isRegister() ||
121 mi->getOperand(i).getReg() != regA);
124 const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
125 MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
127 MachineBasicBlock::iterator prevMi = prior(mi);
128 DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
131 // update live variables for regA
132 LiveVariables::VarInfo& varInfo = LV->getVarInfo(regA);
133 varInfo.DefInst = prevMi;
135 // update live variables for regB
136 if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
137 LV->addVirtualRegisterKilled(regB, prevMi);
139 if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
140 LV->addVirtualRegisterDead(regB, prevMi);
143 // replace all occurences of regB with regA
144 for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
145 if (mi->getOperand(i).isRegister() &&
146 mi->getOperand(i).getReg() == regB)
147 mi->SetMachineOperandReg(i, regA);
151 assert(mi->getOperand(0).isDef());
152 mi->getOperand(0).setUse();
153 mi->RemoveOperand(1);
156 DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));