1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/Analysis/AliasAnalysis.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/ADT/BitVector.h"
46 #include "llvm/ADT/DenseMap.h"
47 #include "llvm/ADT/SmallSet.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/ADT/STLExtras.h"
52 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
53 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
54 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
55 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
56 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
57 STATISTIC(NumReMats, "Number of instructions re-materialized");
58 STATISTIC(NumDeletes, "Number of dead instructions deleted");
61 class TwoAddressInstructionPass : public MachineFunctionPass {
62 const TargetInstrInfo *TII;
63 const TargetRegisterInfo *TRI;
64 MachineRegisterInfo *MRI;
68 // DistanceMap - Keep track the distance of a MI from the start of the
69 // current basic block.
70 DenseMap<MachineInstr*, unsigned> DistanceMap;
72 // SrcRegMap - A map from virtual registers to physical registers which
73 // are likely targets to be coalesced to due to copies from physical
74 // registers to virtual registers. e.g. v1024 = move r0.
75 DenseMap<unsigned, unsigned> SrcRegMap;
77 // DstRegMap - A map from virtual registers to physical registers which
78 // are likely targets to be coalesced to due to copies to physical
79 // registers from virtual registers. e.g. r1 = move v1024.
80 DenseMap<unsigned, unsigned> DstRegMap;
82 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
83 /// during the initial walk of the machine function.
84 SmallVector<MachineInstr*, 16> RegSequences;
86 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
88 MachineBasicBlock::iterator OldPos);
90 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
91 MachineInstr *MI, MachineInstr *DefMI,
92 MachineBasicBlock *MBB, unsigned Loc);
94 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
97 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
100 bool isProfitableToCommute(unsigned regB, unsigned regC,
101 MachineInstr *MI, MachineBasicBlock *MBB,
104 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
105 MachineFunction::iterator &mbbi,
106 unsigned RegB, unsigned RegC, unsigned Dist);
108 bool isProfitableToConv3Addr(unsigned RegA);
110 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
111 MachineBasicBlock::iterator &nmi,
112 MachineFunction::iterator &mbbi,
113 unsigned RegB, unsigned Dist);
115 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
116 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
117 SmallVector<NewKill, 4> &NewKills,
118 MachineBasicBlock *MBB, unsigned Dist);
119 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
120 MachineBasicBlock::iterator &nmi,
121 MachineFunction::iterator &mbbi, unsigned Dist);
123 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
124 MachineBasicBlock::iterator &nmi,
125 MachineFunction::iterator &mbbi,
126 unsigned SrcIdx, unsigned DstIdx,
129 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
130 SmallPtrSet<MachineInstr*, 8> &Processed);
132 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
134 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
135 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
136 /// sub-register references of the register defined by REG_SEQUENCE.
137 bool EliminateRegSequences();
140 static char ID; // Pass identification, replacement for typeid
141 TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
143 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
144 AU.setPreservesCFG();
145 AU.addRequired<AliasAnalysis>();
146 AU.addPreserved<LiveVariables>();
147 AU.addPreservedID(MachineLoopInfoID);
148 AU.addPreservedID(MachineDominatorsID);
150 AU.addPreservedID(StrongPHIEliminationID);
152 AU.addPreservedID(PHIEliminationID);
153 MachineFunctionPass::getAnalysisUsage(AU);
156 /// runOnMachineFunction - Pass entry point.
157 bool runOnMachineFunction(MachineFunction&);
161 char TwoAddressInstructionPass::ID = 0;
162 static RegisterPass<TwoAddressInstructionPass>
163 X("twoaddressinstruction", "Two-Address instruction pass");
165 const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
167 /// Sink3AddrInstruction - A two-address instruction has been converted to a
168 /// three-address instruction to avoid clobbering a register. Try to sink it
169 /// past the instruction that would kill the above mentioned register to reduce
170 /// register pressure.
171 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
172 MachineInstr *MI, unsigned SavedReg,
173 MachineBasicBlock::iterator OldPos) {
174 // Check if it's safe to move this instruction.
175 bool SeenStore = true; // Be conservative.
176 if (!MI->isSafeToMove(TII, AA, SeenStore))
180 SmallSet<unsigned, 4> UseRegs;
182 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
183 const MachineOperand &MO = MI->getOperand(i);
186 unsigned MOReg = MO.getReg();
189 if (MO.isUse() && MOReg != SavedReg)
190 UseRegs.insert(MO.getReg());
194 // Don't try to move it if it implicitly defines a register.
197 // For now, don't move any instructions that define multiple registers.
199 DefReg = MO.getReg();
202 // Find the instruction that kills SavedReg.
203 MachineInstr *KillMI = NULL;
204 for (MachineRegisterInfo::use_nodbg_iterator
205 UI = MRI->use_nodbg_begin(SavedReg),
206 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
207 MachineOperand &UseMO = UI.getOperand();
210 KillMI = UseMO.getParent();
214 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
217 // If any of the definitions are used by another instruction between the
218 // position and the kill use, then it's not safe to sink it.
220 // FIXME: This can be sped up if there is an easy way to query whether an
221 // instruction is before or after another instruction. Then we can use
222 // MachineRegisterInfo def / use instead.
223 MachineOperand *KillMO = NULL;
224 MachineBasicBlock::iterator KillPos = KillMI;
227 unsigned NumVisited = 0;
228 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
229 MachineInstr *OtherMI = I;
230 // DBG_VALUE cannot be counted against the limit.
231 if (OtherMI->isDebugValue())
233 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
236 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
237 MachineOperand &MO = OtherMI->getOperand(i);
240 unsigned MOReg = MO.getReg();
247 if (OtherMI == KillMI && MOReg == SavedReg)
248 // Save the operand that kills the register. We want to unset the kill
249 // marker if we can sink MI past it.
251 else if (UseRegs.count(MOReg))
252 // One of the uses is killed before the destination.
258 // Update kill and LV information.
259 KillMO->setIsKill(false);
260 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
261 KillMO->setIsKill(true);
264 LV->replaceKillInstruction(SavedReg, KillMI, MI);
266 // Move instruction to its destination.
268 MBB->insert(KillPos, MI);
274 /// isTwoAddrUse - Return true if the specified MI is using the specified
275 /// register as a two-address operand.
276 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
277 const TargetInstrDesc &TID = UseMI->getDesc();
278 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
279 MachineOperand &MO = UseMI->getOperand(i);
280 if (MO.isReg() && MO.getReg() == Reg &&
281 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
282 // Earlier use is a two-address one.
288 /// isProfitableToReMat - Return true if the heuristics determines it is likely
289 /// to be profitable to re-materialize the definition of Reg rather than copy
292 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
293 const TargetRegisterClass *RC,
294 MachineInstr *MI, MachineInstr *DefMI,
295 MachineBasicBlock *MBB, unsigned Loc) {
296 bool OtherUse = false;
297 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
298 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
299 MachineOperand &UseMO = UI.getOperand();
300 MachineInstr *UseMI = UseMO.getParent();
301 MachineBasicBlock *UseMBB = UseMI->getParent();
303 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
304 if (DI != DistanceMap.end() && DI->second == Loc)
305 continue; // Current use.
307 // There is at least one other use in the MBB that will clobber the
309 if (isTwoAddrUse(UseMI, Reg))
314 // If other uses in MBB are not two-address uses, then don't remat.
318 // No other uses in the same block, remat if it's defined in the same
319 // block so it does not unnecessarily extend the live range.
320 return MBB == DefMI->getParent();
323 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
324 /// last instruction in the MBB that defines the specified register and the
325 /// two-address instruction which is being processed. It also returns the last
326 /// def location by reference
327 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
328 MachineBasicBlock *MBB, unsigned Dist,
331 unsigned LastUse = Dist;
332 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
333 E = MRI->reg_end(); I != E; ++I) {
334 MachineOperand &MO = I.getOperand();
335 MachineInstr *MI = MO.getParent();
336 if (MI->getParent() != MBB || MI->isDebugValue())
338 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
339 if (DI == DistanceMap.end())
341 if (MO.isUse() && DI->second < LastUse)
342 LastUse = DI->second;
343 if (MO.isDef() && DI->second > LastDef)
344 LastDef = DI->second;
347 return !(LastUse > LastDef && LastUse < Dist);
350 MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
351 MachineBasicBlock *MBB,
353 unsigned LastUseDist = 0;
354 MachineInstr *LastUse = 0;
355 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
356 E = MRI->reg_end(); I != E; ++I) {
357 MachineOperand &MO = I.getOperand();
358 MachineInstr *MI = MO.getParent();
359 if (MI->getParent() != MBB || MI->isDebugValue())
361 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
362 if (DI == DistanceMap.end())
364 if (DI->second >= Dist)
367 if (MO.isUse() && DI->second > LastUseDist) {
369 LastUseDist = DI->second;
375 /// isCopyToReg - Return true if the specified MI is a copy instruction or
376 /// a extract_subreg instruction. It also returns the source and destination
377 /// registers and whether they are physical registers by reference.
378 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
379 unsigned &SrcReg, unsigned &DstReg,
380 bool &IsSrcPhys, bool &IsDstPhys) {
383 unsigned SrcSubIdx, DstSubIdx;
384 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
385 if (MI.isExtractSubreg()) {
386 DstReg = MI.getOperand(0).getReg();
387 SrcReg = MI.getOperand(1).getReg();
388 } else if (MI.isInsertSubreg()) {
389 DstReg = MI.getOperand(0).getReg();
390 SrcReg = MI.getOperand(2).getReg();
391 } else if (MI.isSubregToReg()) {
392 DstReg = MI.getOperand(0).getReg();
393 SrcReg = MI.getOperand(2).getReg();
398 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
399 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
405 /// isKilled - Test if the given register value, which is used by the given
406 /// instruction, is killed by the given instruction. This looks through
407 /// coalescable copies to see if the original value is potentially not killed.
409 /// For example, in this code:
411 /// %reg1034 = copy %reg1024
412 /// %reg1035 = copy %reg1025<kill>
413 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
415 /// %reg1034 is not considered to be killed, since it is copied from a
416 /// register which is not killed. Treating it as not killed lets the
417 /// normal heuristics commute the (two-address) add, which lets
418 /// coalescing eliminate the extra copy.
420 static bool isKilled(MachineInstr &MI, unsigned Reg,
421 const MachineRegisterInfo *MRI,
422 const TargetInstrInfo *TII) {
423 MachineInstr *DefMI = &MI;
425 if (!DefMI->killsRegister(Reg))
427 if (TargetRegisterInfo::isPhysicalRegister(Reg))
429 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
430 // If there are multiple defs, we can't do a simple analysis, so just
431 // go with what the kill flag says.
432 if (llvm::next(Begin) != MRI->def_end())
435 bool IsSrcPhys, IsDstPhys;
436 unsigned SrcReg, DstReg;
437 // If the def is something other than a copy, then it isn't going to
438 // be coalesced, so follow the kill flag.
439 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
445 /// isTwoAddrUse - Return true if the specified MI uses the specified register
446 /// as a two-address use. If so, return the destination register by reference.
447 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
448 const TargetInstrDesc &TID = MI.getDesc();
449 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands();
450 for (unsigned i = 0; i != NumOps; ++i) {
451 const MachineOperand &MO = MI.getOperand(i);
452 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
455 if (MI.isRegTiedToDefOperand(i, &ti)) {
456 DstReg = MI.getOperand(ti).getReg();
463 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
464 /// use, return the use instruction if it's a copy or a two-address use.
466 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
467 MachineRegisterInfo *MRI,
468 const TargetInstrInfo *TII,
470 unsigned &DstReg, bool &IsDstPhys) {
471 if (!MRI->hasOneNonDBGUse(Reg))
472 // None or more than one use.
474 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
475 if (UseMI.getParent() != MBB)
479 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
484 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
485 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
491 /// getMappedReg - Return the physical register the specified virtual register
492 /// might be mapped to.
494 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
495 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
496 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
497 if (SI == RegMap.end())
501 if (TargetRegisterInfo::isPhysicalRegister(Reg))
506 /// regsAreCompatible - Return true if the two registers are equal or aliased.
509 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
514 return TRI->regsOverlap(RegA, RegB);
518 /// isProfitableToReMat - Return true if it's potentially profitable to commute
519 /// the two-address instruction that's being processed.
521 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
522 MachineInstr *MI, MachineBasicBlock *MBB,
524 // Determine if it's profitable to commute this two address instruction. In
525 // general, we want no uses between this instruction and the definition of
526 // the two-address register.
528 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
529 // %reg1029<def> = MOV8rr %reg1028
530 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
531 // insert => %reg1030<def> = MOV8rr %reg1028
532 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
533 // In this case, it might not be possible to coalesce the second MOV8rr
534 // instruction if the first one is coalesced. So it would be profitable to
536 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
537 // %reg1029<def> = MOV8rr %reg1028
538 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
539 // insert => %reg1030<def> = MOV8rr %reg1029
540 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
542 if (!MI->killsRegister(regC))
545 // Ok, we have something like:
546 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
547 // let's see if it's worth commuting it.
549 // Look for situations like this:
550 // %reg1024<def> = MOV r1
551 // %reg1025<def> = MOV r0
552 // %reg1026<def> = ADD %reg1024, %reg1025
554 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
555 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
556 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
557 unsigned ToRegB = getMappedReg(regB, DstRegMap);
558 unsigned ToRegC = getMappedReg(regC, DstRegMap);
559 if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
560 (regsAreCompatible(FromRegB, ToRegC, TRI) ||
561 regsAreCompatible(FromRegC, ToRegB, TRI)))
564 // If there is a use of regC between its last def (could be livein) and this
565 // instruction, then bail.
566 unsigned LastDefC = 0;
567 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
570 // If there is a use of regB between its last def (could be livein) and this
571 // instruction, then go ahead and make this transformation.
572 unsigned LastDefB = 0;
573 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
576 // Since there are no intervening uses for both registers, then commute
577 // if the def of regC is closer. Its live interval is shorter.
578 return LastDefB && LastDefC && LastDefC > LastDefB;
581 /// CommuteInstruction - Commute a two-address instruction and update the basic
582 /// block, distance map, and live variables if needed. Return true if it is
585 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
586 MachineFunction::iterator &mbbi,
587 unsigned RegB, unsigned RegC, unsigned Dist) {
588 MachineInstr *MI = mi;
589 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
590 MachineInstr *NewMI = TII->commuteInstruction(MI);
593 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
597 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
598 // If the instruction changed to commute it, update livevar.
601 // Update live variables
602 LV->replaceKillInstruction(RegC, MI, NewMI);
604 mbbi->insert(mi, NewMI); // Insert the new inst
605 mbbi->erase(mi); // Nuke the old inst.
607 DistanceMap.insert(std::make_pair(NewMI, Dist));
610 // Update source register map.
611 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
613 unsigned RegA = MI->getOperand(0).getReg();
614 SrcRegMap[RegA] = FromRegC;
620 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
621 /// given 2-address instruction to a 3-address one.
623 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
624 // Look for situations like this:
625 // %reg1024<def> = MOV r1
626 // %reg1025<def> = MOV r0
627 // %reg1026<def> = ADD %reg1024, %reg1025
629 // Turn ADD into a 3-address instruction to avoid a copy.
630 unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
631 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
632 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
635 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
636 /// three address one. Return true if this transformation was successful.
638 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
639 MachineBasicBlock::iterator &nmi,
640 MachineFunction::iterator &mbbi,
641 unsigned RegB, unsigned Dist) {
642 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
644 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
645 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
648 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
649 // FIXME: Temporary workaround. If the new instruction doesn't
650 // uses RegB, convertToThreeAddress must have created more
651 // then one instruction.
652 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
654 mbbi->erase(mi); // Nuke the old inst.
657 DistanceMap.insert(std::make_pair(NewMI, Dist));
659 nmi = llvm::next(mi);
667 /// ProcessCopy - If the specified instruction is not yet processed, process it
668 /// if it's a copy. For a copy instruction, we find the physical registers the
669 /// source and destination registers might be mapped to. These are kept in
670 /// point-to maps used to determine future optimizations. e.g.
673 /// v1026 = add v1024, v1025
675 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
676 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
677 /// potentially joined with r1 on the output side. It's worthwhile to commute
678 /// 'add' to eliminate a copy.
679 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
680 MachineBasicBlock *MBB,
681 SmallPtrSet<MachineInstr*, 8> &Processed) {
682 if (Processed.count(MI))
685 bool IsSrcPhys, IsDstPhys;
686 unsigned SrcReg, DstReg;
687 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
690 if (IsDstPhys && !IsSrcPhys)
691 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
692 else if (!IsDstPhys && IsSrcPhys) {
693 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
695 assert(SrcRegMap[DstReg] == SrcReg &&
696 "Can't map to two src physical registers!");
698 SmallVector<unsigned, 4> VirtRegPairs;
701 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
702 IsCopy, NewReg, IsDstPhys)) {
704 if (!Processed.insert(UseMI))
708 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
709 if (DI != DistanceMap.end())
710 // Earlier in the same MBB.Reached via a back edge.
714 VirtRegPairs.push_back(NewReg);
717 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
719 assert(SrcRegMap[NewReg] == DstReg &&
720 "Can't map to two src physical registers!");
721 VirtRegPairs.push_back(NewReg);
725 if (!VirtRegPairs.empty()) {
726 unsigned ToReg = VirtRegPairs.back();
727 VirtRegPairs.pop_back();
728 while (!VirtRegPairs.empty()) {
729 unsigned FromReg = VirtRegPairs.back();
730 VirtRegPairs.pop_back();
731 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
733 assert(DstRegMap[FromReg] == ToReg &&
734 "Can't map to two dst physical registers!");
740 Processed.insert(MI);
743 /// isSafeToDelete - If the specified instruction does not produce any side
744 /// effects and all of its defs are dead, then it's safe to delete.
745 static bool isSafeToDelete(MachineInstr *MI,
746 const TargetInstrInfo *TII,
747 SmallVector<unsigned, 4> &Kills) {
748 const TargetInstrDesc &TID = MI->getDesc();
749 if (TID.mayStore() || TID.isCall())
751 if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
754 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
755 MachineOperand &MO = MI->getOperand(i);
758 if (MO.isDef() && !MO.isDead())
760 if (MO.isUse() && MO.isKill())
761 Kills.push_back(MO.getReg());
766 /// canUpdateDeletedKills - Check if all the registers listed in Kills are
767 /// killed by instructions in MBB preceding the current instruction at
768 /// position Dist. If so, return true and record information about the
769 /// preceding kills in NewKills.
770 bool TwoAddressInstructionPass::
771 canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
772 SmallVector<NewKill, 4> &NewKills,
773 MachineBasicBlock *MBB, unsigned Dist) {
774 while (!Kills.empty()) {
775 unsigned Kill = Kills.back();
777 if (TargetRegisterInfo::isPhysicalRegister(Kill))
780 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
784 bool isModRef = LastKill->definesRegister(Kill);
785 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
791 /// DeleteUnusedInstr - If an instruction with a tied register operand can
792 /// be safely deleted, just delete it.
794 TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
795 MachineBasicBlock::iterator &nmi,
796 MachineFunction::iterator &mbbi,
798 // Check if the instruction has no side effects and if all its defs are dead.
799 SmallVector<unsigned, 4> Kills;
800 if (!isSafeToDelete(mi, TII, Kills))
803 // If this instruction kills some virtual registers, we need to
804 // update the kill information. If it's not possible to do so,
806 SmallVector<NewKill, 4> NewKills;
807 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
811 while (!NewKills.empty()) {
812 MachineInstr *NewKill = NewKills.back().second;
813 unsigned Kill = NewKills.back().first.first;
814 bool isDead = NewKills.back().first.second;
816 if (LV->removeVirtualRegisterKilled(Kill, mi)) {
818 LV->addVirtualRegisterDead(Kill, NewKill);
820 LV->addVirtualRegisterKilled(Kill, NewKill);
825 mbbi->erase(mi); // Nuke the old inst.
830 /// TryInstructionTransform - For the case where an instruction has a single
831 /// pair of tied register operands, attempt some transformations that may
832 /// either eliminate the tied operands or improve the opportunities for
833 /// coalescing away the register copy. Returns true if the tied operands
834 /// are eliminated altogether.
835 bool TwoAddressInstructionPass::
836 TryInstructionTransform(MachineBasicBlock::iterator &mi,
837 MachineBasicBlock::iterator &nmi,
838 MachineFunction::iterator &mbbi,
839 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
840 const TargetInstrDesc &TID = mi->getDesc();
841 unsigned regA = mi->getOperand(DstIdx).getReg();
842 unsigned regB = mi->getOperand(SrcIdx).getReg();
844 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
845 "cannot make instruction into two-address form");
847 // If regA is dead and the instruction can be deleted, just delete
848 // it so it doesn't clobber regB.
849 bool regBKilled = isKilled(*mi, regB, MRI, TII);
850 if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
851 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
853 return true; // Done with this instruction.
856 // Check if it is profitable to commute the operands.
857 unsigned SrcOp1, SrcOp2;
859 unsigned regCIdx = ~0U;
860 bool TryCommute = false;
861 bool AggressiveCommute = false;
862 if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
863 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
864 if (SrcIdx == SrcOp1)
866 else if (SrcIdx == SrcOp2)
869 if (regCIdx != ~0U) {
870 regC = mi->getOperand(regCIdx).getReg();
871 if (!regBKilled && isKilled(*mi, regC, MRI, TII))
872 // If C dies but B does not, swap the B and C operands.
873 // This makes the live ranges of A and C joinable.
875 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
877 AggressiveCommute = true;
882 // If it's profitable to commute, try to do so.
883 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
885 if (AggressiveCommute)
890 if (TID.isConvertibleTo3Addr()) {
891 // This instruction is potentially convertible to a true
892 // three-address instruction. Check if it is profitable.
893 if (!regBKilled || isProfitableToConv3Addr(regA)) {
894 // Try to convert it.
895 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
896 ++NumConvertedTo3Addr;
897 return true; // Done with this instruction.
902 // If this is an instruction with a load folded into it, try unfolding
903 // the load, e.g. avoid this:
909 // because it's preferable to schedule a load than a register copy.
910 if (TID.mayLoad() && !regBKilled) {
911 // Determine if a load can be unfolded.
912 unsigned LoadRegIndex;
914 TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(),
916 /*UnfoldStore=*/false,
919 const TargetInstrDesc &UnfoldTID = TII->get(NewOpc);
920 if (UnfoldTID.getNumDefs() == 1) {
921 MachineFunction &MF = *mbbi->getParent();
924 DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
925 const TargetRegisterClass *RC =
926 UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
927 unsigned Reg = MRI->createVirtualRegister(RC);
928 SmallVector<MachineInstr *, 2> NewMIs;
930 TII->unfoldMemoryOperand(MF, mi, Reg,
931 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
935 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
937 assert(NewMIs.size() == 2 &&
938 "Unfolded a load into multiple instructions!");
939 // The load was previously folded, so this is the only use.
940 NewMIs[1]->addRegisterKilled(Reg, TRI);
942 // Tentatively insert the instructions into the block so that they
943 // look "normal" to the transformation logic.
944 mbbi->insert(mi, NewMIs[0]);
945 mbbi->insert(mi, NewMIs[1]);
947 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
948 << "2addr: NEW INST: " << *NewMIs[1]);
950 // Transform the instruction, now that it no longer has a load.
951 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
952 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
953 MachineBasicBlock::iterator NewMI = NewMIs[1];
954 bool TransformSuccess =
955 TryInstructionTransform(NewMI, mi, mbbi,
956 NewSrcIdx, NewDstIdx, Dist);
957 if (TransformSuccess ||
958 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
959 // Success, or at least we made an improvement. Keep the unfolded
960 // instructions and discard the original.
962 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
963 MachineOperand &MO = mi->getOperand(i);
964 if (MO.isReg() && MO.getReg() != 0 &&
965 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
968 if (NewMIs[0]->killsRegister(MO.getReg()))
969 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]);
971 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
972 "Kill missing after load unfold!");
973 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]);
976 } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) {
977 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
978 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
980 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
981 "Dead flag missing after load unfold!");
982 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
987 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
989 mi->eraseFromParent();
991 if (TransformSuccess)
994 // Transforming didn't eliminate the tie and didn't lead to an
995 // improvement. Clean up the unfolded instructions and keep the
997 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
998 NewMIs[0]->eraseFromParent();
999 NewMIs[1]->eraseFromParent();
1008 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1010 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
1011 DEBUG(dbgs() << "Machine Function\n");
1012 const TargetMachine &TM = MF.getTarget();
1013 MRI = &MF.getRegInfo();
1014 TII = TM.getInstrInfo();
1015 TRI = TM.getRegisterInfo();
1016 LV = getAnalysisIfAvailable<LiveVariables>();
1017 AA = &getAnalysis<AliasAnalysis>();
1019 bool MadeChange = false;
1021 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1022 DEBUG(dbgs() << "********** Function: "
1023 << MF.getFunction()->getName() << '\n');
1025 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
1026 BitVector ReMatRegs;
1027 ReMatRegs.resize(MRI->getLastVirtReg()+1);
1029 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
1031 TiedOperandMap TiedOperands(4);
1033 SmallPtrSet<MachineInstr*, 8> Processed;
1034 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
1035 mbbi != mbbe; ++mbbi) {
1037 DistanceMap.clear();
1041 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
1043 MachineBasicBlock::iterator nmi = llvm::next(mi);
1044 if (mi->isDebugValue()) {
1049 // Remember REG_SEQUENCE instructions, we'll deal with them later.
1050 if (mi->isRegSequence())
1051 RegSequences.push_back(&*mi);
1053 const TargetInstrDesc &TID = mi->getDesc();
1054 bool FirstTied = true;
1056 DistanceMap.insert(std::make_pair(mi, ++Dist));
1058 ProcessCopy(&*mi, &*mbbi, Processed);
1060 // First scan through all the tied register uses in this instruction
1061 // and record a list of pairs of tied operands for each register.
1062 unsigned NumOps = mi->isInlineAsm()
1063 ? mi->getNumOperands() : TID.getNumOperands();
1064 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1065 unsigned DstIdx = 0;
1066 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1071 ++NumTwoAddressInstrs;
1072 DEBUG(dbgs() << '\t' << *mi);
1075 assert(mi->getOperand(SrcIdx).isReg() &&
1076 mi->getOperand(SrcIdx).getReg() &&
1077 mi->getOperand(SrcIdx).isUse() &&
1078 "two address instruction invalid");
1080 unsigned regB = mi->getOperand(SrcIdx).getReg();
1081 TiedOperandMap::iterator OI = TiedOperands.find(regB);
1082 if (OI == TiedOperands.end()) {
1083 SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
1084 OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
1086 OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
1089 // Now iterate over the information collected above.
1090 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1091 OE = TiedOperands.end(); OI != OE; ++OI) {
1092 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
1094 // If the instruction has a single pair of tied operands, try some
1095 // transformations that may either eliminate the tied operands or
1096 // improve the opportunities for coalescing away the register copy.
1097 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
1098 unsigned SrcIdx = TiedPairs[0].first;
1099 unsigned DstIdx = TiedPairs[0].second;
1101 // If the registers are already equal, nothing needs to be done.
1102 if (mi->getOperand(SrcIdx).getReg() ==
1103 mi->getOperand(DstIdx).getReg())
1104 break; // Done with this instruction.
1106 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
1107 break; // The tied operands have been eliminated.
1110 bool RemovedKillFlag = false;
1111 bool AllUsesCopied = true;
1112 unsigned LastCopiedReg = 0;
1113 unsigned regB = OI->first;
1114 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1115 unsigned SrcIdx = TiedPairs[tpi].first;
1116 unsigned DstIdx = TiedPairs[tpi].second;
1117 unsigned regA = mi->getOperand(DstIdx).getReg();
1118 // Grab regB from the instruction because it may have changed if the
1119 // instruction was commuted.
1120 regB = mi->getOperand(SrcIdx).getReg();
1123 // The register is tied to multiple destinations (or else we would
1124 // not have continued this far), but this use of the register
1125 // already matches the tied destination. Leave it.
1126 AllUsesCopied = false;
1129 LastCopiedReg = regA;
1131 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1132 "cannot make instruction into two-address form");
1135 // First, verify that we don't have a use of "a" in the instruction
1136 // (a = b + a for example) because our transformation will not
1137 // work. This should never occur because we are in SSA form.
1138 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1139 assert(i == DstIdx ||
1140 !mi->getOperand(i).isReg() ||
1141 mi->getOperand(i).getReg() != regA);
1144 // Emit a copy or rematerialize the definition.
1145 const TargetRegisterClass *rc = MRI->getRegClass(regB);
1146 MachineInstr *DefMI = MRI->getVRegDef(regB);
1147 // If it's safe and profitable, remat the definition instead of
1150 DefMI->getDesc().isAsCheapAsAMove() &&
1151 DefMI->isSafeToReMat(TII, AA, regB) &&
1152 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1153 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
1154 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1155 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
1156 ReMatRegs.set(regB);
1159 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc,
1162 assert(Emitted && "Unable to issue a copy instruction!\n");
1165 MachineBasicBlock::iterator prevMI = prior(mi);
1166 // Update DistanceMap.
1167 DistanceMap.insert(std::make_pair(prevMI, Dist));
1168 DistanceMap[mi] = ++Dist;
1170 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
1172 MachineOperand &MO = mi->getOperand(SrcIdx);
1173 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1174 "inconsistent operand info for 2-reg pass");
1176 MO.setIsKill(false);
1177 RemovedKillFlag = true;
1182 if (AllUsesCopied) {
1183 // Replace other (un-tied) uses of regB with LastCopiedReg.
1184 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1185 MachineOperand &MO = mi->getOperand(i);
1186 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1188 MO.setIsKill(false);
1189 RemovedKillFlag = true;
1191 MO.setReg(LastCopiedReg);
1195 // Update live variables for regB.
1196 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1197 LV->addVirtualRegisterKilled(regB, prior(mi));
1199 } else if (RemovedKillFlag) {
1200 // Some tied uses of regB matched their destination registers, so
1201 // regB is still used in this instruction, but a kill flag was
1202 // removed from a different tied use of regB, so now we need to add
1203 // a kill flag to one of the remaining uses of regB.
1204 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1205 MachineOperand &MO = mi->getOperand(i);
1206 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1213 // Schedule the source copy / remat inserted to form two-address
1214 // instruction. FIXME: Does it matter the distance map may not be
1215 // accurate after it's scheduled?
1216 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
1220 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1223 // Clear TiedOperands here instead of at the top of the loop
1224 // since most instructions do not have tied operands.
1225 TiedOperands.clear();
1230 // Some remat'ed instructions are dead.
1231 int VReg = ReMatRegs.find_first();
1232 while (VReg != -1) {
1233 if (MRI->use_nodbg_empty(VReg)) {
1234 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1235 DefMI->eraseFromParent();
1237 VReg = ReMatRegs.find_next(VReg);
1240 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1241 // SSA form. It's now safe to de-SSA.
1242 MadeChange |= EliminateRegSequences();
1247 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1248 unsigned DstReg, unsigned SubIdx,
1249 MachineRegisterInfo *MRI,
1250 const TargetRegisterInfo &TRI) {
1251 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1252 RE = MRI->reg_end(); RI != RE; ) {
1253 MachineOperand &MO = RI.getOperand();
1255 MO.substVirtReg(DstReg, SubIdx, TRI);
1259 /// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
1260 /// EXTRACT_SUBREG from the same register and to the same virtual register
1261 /// with different sub-register indices, attempt to combine the
1262 /// EXTRACT_SUBREGs and pre-coalesce them. e.g.
1263 /// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
1264 /// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
1265 /// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
1266 /// Since D subregs 5, 6 can combine to a Q register, we can coalesce
1267 /// reg1026 to reg1029.
1269 TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
1271 SmallSet<unsigned, 4> Seen;
1272 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
1273 unsigned SrcReg = Srcs[i];
1274 if (!Seen.insert(SrcReg))
1277 // Check that the instructions are all in the same basic block.
1278 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg);
1279 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg);
1280 if (SrcDefMI->getParent() != DstDefMI->getParent())
1283 // If there are no other uses than extract_subreg which feed into
1284 // the reg_sequence, then we might be able to coalesce them.
1285 bool CanCoalesce = true;
1286 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
1287 for (MachineRegisterInfo::use_nodbg_iterator
1288 UI = MRI->use_nodbg_begin(SrcReg),
1289 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1290 MachineInstr *UseMI = &*UI;
1291 if (!UseMI->isExtractSubreg() ||
1292 UseMI->getOperand(0).getReg() != DstReg ||
1293 UseMI->getOperand(1).getSubReg() != 0) {
1294 CanCoalesce = false;
1297 SrcSubIndices.push_back(UseMI->getOperand(2).getImm());
1298 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
1301 if (!CanCoalesce || SrcSubIndices.size() < 2)
1304 // Check that the source subregisters can be combined.
1305 std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
1306 unsigned NewSrcSubIdx = 0;
1307 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
1311 // Check that the destination subregisters can also be combined.
1312 std::sort(DstSubIndices.begin(), DstSubIndices.end());
1313 unsigned NewDstSubIdx = 0;
1314 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
1318 // If neither source nor destination can be combined to the full register,
1319 // just give up. This could be improved if it ever matters.
1320 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
1323 // Now that we know that all the uses are extract_subregs and that those
1324 // subregs can somehow be combined, scan all the extract_subregs again to
1325 // make sure the subregs are in the right order and can be composed.
1326 MachineInstr *SomeMI = 0;
1328 for (MachineRegisterInfo::use_nodbg_iterator
1329 UI = MRI->use_nodbg_begin(SrcReg),
1330 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1331 MachineInstr *UseMI = &*UI;
1332 assert(UseMI->isExtractSubreg());
1333 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
1334 unsigned SrcSubIdx = UseMI->getOperand(2).getImm();
1335 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
1336 if ((NewDstSubIdx == 0 &&
1337 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
1338 (NewSrcSubIdx == 0 &&
1339 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
1340 CanCoalesce = false;
1343 // Keep track of one of the uses.
1349 // Insert a copy or an extract to replace the original extracts.
1350 MachineBasicBlock::iterator InsertLoc = SomeMI;
1352 // Insert an extract subreg.
1353 BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
1354 TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg)
1355 .addReg(SrcReg).addImm(NewSrcSubIdx);
1356 } else if (NewDstSubIdx) {
1357 // Do a subreg insertion.
1358 BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
1359 TII->get(TargetOpcode::INSERT_SUBREG), DstReg)
1360 .addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx);
1364 TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg,
1365 MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg),
1366 SomeMI->getDebugLoc());
1369 MachineBasicBlock::iterator CopyMI = prior(InsertLoc);
1371 // Remove all the old extract instructions.
1372 for (MachineRegisterInfo::use_nodbg_iterator
1373 UI = MRI->use_nodbg_begin(SrcReg),
1374 UE = MRI->use_nodbg_end(); UI != UE; ) {
1375 MachineInstr *UseMI = &*UI;
1377 if (UseMI == CopyMI)
1379 assert(UseMI->isExtractSubreg());
1380 // Move any kills to the new copy or extract instruction.
1381 if (UseMI->getOperand(1).isKill()) {
1382 MachineOperand *KillMO = CopyMI->findRegisterUseOperand(SrcReg);
1383 KillMO->setIsKill();
1385 // Update live variables
1386 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
1388 UseMI->eraseFromParent();
1393 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
1394 MachineRegisterInfo *MRI) {
1395 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
1396 UE = MRI->use_end(); UI != UE; ++UI) {
1397 MachineInstr *UseMI = &*UI;
1398 if (UseMI != RegSeq && UseMI->isRegSequence())
1404 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1405 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1406 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1408 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1409 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1411 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1412 bool TwoAddressInstructionPass::EliminateRegSequences() {
1413 if (RegSequences.empty())
1416 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1417 MachineInstr *MI = RegSequences[i];
1418 unsigned DstReg = MI->getOperand(0).getReg();
1419 if (MI->getOperand(0).getSubReg() ||
1420 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1421 !(MI->getNumOperands() & 1)) {
1422 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1423 llvm_unreachable(0);
1426 bool IsImpDef = true;
1427 SmallVector<unsigned, 4> RealSrcs;
1428 SmallSet<unsigned, 4> Seen;
1429 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1430 unsigned SrcReg = MI->getOperand(i).getReg();
1431 if (MI->getOperand(i).getSubReg() ||
1432 TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1433 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1434 llvm_unreachable(0);
1437 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
1438 if (DefMI->isImplicitDef()) {
1439 DefMI->eraseFromParent();
1444 // Remember EXTRACT_SUBREG sources. These might be candidate for
1446 if (DefMI->isExtractSubreg())
1447 RealSrcs.push_back(DefMI->getOperand(1).getReg());
1449 if (!Seen.insert(SrcReg) ||
1450 MI->getParent() != DefMI->getParent() ||
1451 !MI->getOperand(i).isKill() ||
1452 HasOtherRegSequenceUses(SrcReg, MI, MRI)) {
1453 // REG_SEQUENCE cannot have duplicated operands, add a copy.
1454 // Also add an copy if the source is live-in the block. We don't want
1455 // to end up with a partial-redef of a livein, e.g.
1457 // reg1051:10<def> =
1463 // LiveIntervalAnalysis won't like it.
1465 // If the REG_SEQUENCE doesn't kill its source, keeping live variables
1466 // correctly up to date becomes very difficult. Insert a copy.
1468 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
1469 unsigned NewReg = MRI->createVirtualRegister(RC);
1470 MachineBasicBlock::iterator InsertLoc = MI;
1472 TII->copyRegToReg(*MI->getParent(), InsertLoc, NewReg, SrcReg, RC, RC,
1475 assert(Emitted && "Unable to issue a copy instruction!\n");
1476 MI->getOperand(i).setReg(NewReg);
1477 if (MI->getOperand(i).isKill()) {
1478 MachineBasicBlock::iterator CopyMI = prior(InsertLoc);
1479 MachineOperand *KillMO = CopyMI->findRegisterUseOperand(SrcReg);
1480 KillMO->setIsKill();
1482 // Update live variables
1483 LV->replaceKillInstruction(SrcReg, MI, &*CopyMI);
1488 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1489 unsigned SrcReg = MI->getOperand(i).getReg();
1490 unsigned SubIdx = MI->getOperand(i+1).getImm();
1491 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1495 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1496 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1497 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1498 MI->RemoveOperand(j);
1500 DEBUG(dbgs() << "Eliminated: " << *MI);
1501 MI->eraseFromParent();
1504 // Try coalescing some EXTRACT_SUBREG instructions. This can create
1505 // INSERT_SUBREG instructions that must have <undef> flags added by
1506 // LiveIntervalAnalysis, so only run it when LiveVariables is available.
1508 CoalesceExtSubRegs(RealSrcs, DstReg);
1511 RegSequences.clear();