1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/DenseMap.h"
45 #include "llvm/ADT/SmallPtrSet.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/STLExtras.h"
50 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
51 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
52 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
53 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
54 STATISTIC(NumReMats, "Number of instructions re-materialized");
57 EnableReMat("two-addr-remat", cl::init(false), cl::Hidden,
58 cl::desc("Two-addr conversion should remat when possible."));
61 class VISIBILITY_HIDDEN TwoAddressInstructionPass
62 : public MachineFunctionPass {
63 const TargetInstrInfo *TII;
64 const TargetRegisterInfo *TRI;
65 MachineRegisterInfo *MRI;
68 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
70 MachineBasicBlock::iterator OldPos);
72 bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
73 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
74 MachineInstr *MI, unsigned Loc,
75 MachineInstr *DefMI, MachineBasicBlock *MBB,
76 DenseMap<MachineInstr*, unsigned> &DistanceMap);
78 static char ID; // Pass identification, replacement for typeid
79 TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
81 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
82 AU.addRequired<LiveVariables>();
83 AU.addPreserved<LiveVariables>();
84 AU.addPreservedID(MachineLoopInfoID);
85 AU.addPreservedID(MachineDominatorsID);
86 AU.addPreservedID(PHIEliminationID);
87 MachineFunctionPass::getAnalysisUsage(AU);
90 /// runOnMachineFunction - Pass entry point.
91 bool runOnMachineFunction(MachineFunction&);
95 char TwoAddressInstructionPass::ID = 0;
96 static RegisterPass<TwoAddressInstructionPass>
97 X("twoaddressinstruction", "Two-Address instruction pass");
99 const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
101 /// Sink3AddrInstruction - A two-address instruction has been converted to a
102 /// three-address instruction to avoid clobbering a register. Try to sink it
103 /// past the instruction that would kill the above mentioned register to reduce
104 /// register pressure.
105 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
106 MachineInstr *MI, unsigned SavedReg,
107 MachineBasicBlock::iterator OldPos) {
108 // Check if it's safe to move this instruction.
109 bool SeenStore = true; // Be conservative.
110 if (!MI->isSafeToMove(TII, SeenStore))
114 SmallSet<unsigned, 4> UseRegs;
116 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
117 const MachineOperand &MO = MI->getOperand(i);
118 if (!MO.isRegister())
120 unsigned MOReg = MO.getReg();
123 if (MO.isUse() && MOReg != SavedReg)
124 UseRegs.insert(MO.getReg());
128 // Don't try to move it if it implicitly defines a register.
131 // For now, don't move any instructions that define multiple registers.
133 DefReg = MO.getReg();
136 // Find the instruction that kills SavedReg.
137 MachineInstr *KillMI = NULL;
138 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
139 UE = MRI->use_end(); UI != UE; ++UI) {
140 MachineOperand &UseMO = UI.getOperand();
143 KillMI = UseMO.getParent();
147 if (!KillMI || KillMI->getParent() != MBB)
150 // If any of the definitions are used by another instruction between the
151 // position and the kill use, then it's not safe to sink it.
153 // FIXME: This can be sped up if there is an easy way to query whether an
154 // instruction is before or after another instruction. Then we can use
155 // MachineRegisterInfo def / use instead.
156 MachineOperand *KillMO = NULL;
157 MachineBasicBlock::iterator KillPos = KillMI;
160 unsigned NumVisited = 0;
161 for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
162 MachineInstr *OtherMI = I;
163 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
166 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = OtherMI->getOperand(i);
168 if (!MO.isRegister())
170 unsigned MOReg = MO.getReg();
177 if (OtherMI == KillMI && MOReg == SavedReg)
178 // Save the operand that kills the register. We want to unset the kill
179 // marker if we can sink MI past it.
181 else if (UseRegs.count(MOReg))
182 // One of the uses is killed before the destination.
188 // Update kill and LV information.
189 KillMO->setIsKill(false);
190 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
191 KillMO->setIsKill(true);
192 LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg);
193 VarInfo.removeKill(KillMI);
194 VarInfo.Kills.push_back(MI);
196 // Move instruction to its destination.
198 MBB->insert(KillPos, MI);
204 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
205 /// instruction which defined the specified register instead of copying it.
207 TwoAddressInstructionPass::isSafeToReMat(unsigned DstReg, MachineInstr *MI) {
208 const TargetInstrDesc &TID = MI->getDesc();
209 if (!TID.isAsCheapAsAMove())
211 bool SawStore = false;
212 if (!MI->isSafeToMove(TII, SawStore))
214 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
215 MachineOperand &MO = MI->getOperand(i);
216 if (!MO.isRegister())
218 // FIXME: For now, do not remat any instruction with register operands.
219 // Later on, we can loosen the restriction is the register operands have
220 // not been modified between the def and use. Note, this is different from
221 // MachineSink because the code in no longer in two-address form (at least
225 else if (!MO.isDead() && MO.getReg() != DstReg)
231 /// isTwoAddrUse - Return true if the specified MI is using the specified
232 /// register as a two-address operand.
233 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
234 const TargetInstrDesc &TID = UseMI->getDesc();
235 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
236 MachineOperand &MO = UseMI->getOperand(i);
237 if (MO.isRegister() && MO.getReg() == Reg &&
238 (MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1))
239 // Earlier use is a two-address one.
245 /// isProfitableToReMat - Return true if the heuristics determines it is likely
246 /// to be profitable to re-materialize the definition of Reg rather than copy
249 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
250 const TargetRegisterClass *RC,
251 MachineInstr *MI, unsigned Loc,
252 MachineInstr *DefMI, MachineBasicBlock *MBB,
253 DenseMap<MachineInstr*, unsigned> &DistanceMap) {
254 if (DefMI->getParent() != MBB)
256 // If earlier uses in MBB are not two-address uses, then don't remat.
257 bool OtherUse = false;
258 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
259 UE = MRI->use_end(); UI != UE; ++UI) {
260 MachineOperand &UseMO = UI.getOperand();
263 MachineInstr *UseMI = UseMO.getParent();
264 if (UseMI->getParent() != MBB)
266 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
267 if (DI != DistanceMap.end() && DI->second == Loc)
268 continue; // Current use.
270 // There is at least one other use in the MBB that will clobber the
272 if (isTwoAddrUse(UseMI, Reg))
278 /// runOnMachineFunction - Reduce two-address instructions to two operands.
280 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
281 DOUT << "Machine Function\n";
282 const TargetMachine &TM = MF.getTarget();
283 MRI = &MF.getRegInfo();
284 TII = TM.getInstrInfo();
285 TRI = TM.getRegisterInfo();
286 LV = &getAnalysis<LiveVariables>();
288 bool MadeChange = false;
290 DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
291 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
293 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
295 ReMatRegs.resize(MRI->getLastVirtReg()+1);
297 // DistanceMap - Keep track the distance of a MI from the start of the
298 // current basic block.
299 DenseMap<MachineInstr*, unsigned> DistanceMap;
301 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
302 mbbi != mbbe; ++mbbi) {
305 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
307 MachineBasicBlock::iterator nmi = next(mi);
308 const TargetInstrDesc &TID = mi->getDesc();
309 bool FirstTied = true;
311 DistanceMap.insert(std::make_pair(mi, ++Dist));
312 for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
313 int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
318 ++NumTwoAddressInstrs;
319 DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
324 assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
325 mi->getOperand(si).isUse() && "two address instruction invalid");
327 // If the two operands are the same we just remove the use
328 // and mark the def as def&use, otherwise we have to insert a copy.
329 if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
335 unsigned regA = mi->getOperand(ti).getReg();
336 unsigned regB = mi->getOperand(si).getReg();
338 assert(TargetRegisterInfo::isVirtualRegister(regA) &&
339 TargetRegisterInfo::isVirtualRegister(regB) &&
340 "cannot update physical register live information");
343 // First, verify that we don't have a use of a in the instruction (a =
344 // b + a for example) because our transformation will not work. This
345 // should never occur because we are in SSA form.
346 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
347 assert((int)i == ti ||
348 !mi->getOperand(i).isRegister() ||
349 mi->getOperand(i).getReg() != regA);
352 // If this instruction is not the killing user of B, see if we can
353 // rearrange the code to make it so. Making it the killing user will
354 // allow us to coalesce A and B together, eliminating the copy we are
356 if (!mi->killsRegister(regB)) {
357 // If this instruction is commutative, check to see if C dies. If
358 // so, swap the B and C operands. This makes the live ranges of A
360 // FIXME: This code also works for A := B op C instructions.
361 if (TID.isCommutable() && mi->getNumOperands() >= 3) {
362 assert(mi->getOperand(3-si).isRegister() &&
363 "Not a proper commutative instruction!");
364 unsigned regC = mi->getOperand(3-si).getReg();
366 if (mi->killsRegister(regC)) {
367 DOUT << "2addr: COMMUTING : " << *mi;
368 MachineInstr *NewMI = TII->commuteInstruction(mi);
371 DOUT << "2addr: COMMUTING FAILED!\n";
373 DOUT << "2addr: COMMUTED TO: " << *NewMI;
374 // If the instruction changed to commute it, update livevar.
376 LV->instructionChanged(mi, NewMI); // Update live variables
377 mbbi->insert(mi, NewMI); // Insert the new inst
378 mbbi->erase(mi); // Nuke the old inst.
380 DistanceMap.insert(std::make_pair(NewMI, Dist));
385 goto InstructionRearranged;
390 // If this instruction is potentially convertible to a true
391 // three-address instruction,
392 if (TID.isConvertibleTo3Addr()) {
393 // FIXME: This assumes there are no more operands which are tied
394 // to another register.
396 for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
397 assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
400 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, *LV);
402 DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
403 DOUT << "2addr: TO 3-ADDR: " << *NewMI;
406 if (NewMI->findRegisterUseOperand(regB, false, TRI))
407 // FIXME: Temporary workaround. If the new instruction doesn't
408 // uses regB, convertToThreeAddress must have created more
409 // then one instruction.
410 Sunk = Sink3AddrInstruction(mbbi, NewMI, regB, mi);
412 mbbi->erase(mi); // Nuke the old inst.
415 DistanceMap.insert(std::make_pair(NewMI, Dist));
420 ++NumConvertedTo3Addr;
421 break; // Done with this instruction.
426 InstructionRearranged:
427 const TargetRegisterClass* rc = MRI->getRegClass(regA);
428 MachineInstr *DefMI = MRI->getVRegDef(regB);
429 // If it's safe and profitable, remat the definition instead of
431 if (EnableReMat && DefMI &&
432 isSafeToReMat(regB, DefMI) &&
433 isProfitableToReMat(regB, rc, mi, Dist, DefMI, mbbi,DistanceMap)){
434 DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
435 TII->reMaterialize(*mbbi, mi, regA, DefMI);
439 TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
442 MachineBasicBlock::iterator prevMi = prior(mi);
443 DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
445 // Update live variables for regB.
446 LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB);
448 // regB is used in this BB.
449 varInfoB.UsedBlocks[mbbi->getNumber()] = true;
451 if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
452 LV->addVirtualRegisterKilled(regB, prevMi);
454 if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
455 LV->addVirtualRegisterDead(regB, prevMi);
457 // Replace all occurences of regB with regA.
458 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
459 if (mi->getOperand(i).isRegister() &&
460 mi->getOperand(i).getReg() == regB)
461 mi->getOperand(i).setReg(regA);
465 assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
466 mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
469 DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
477 // Some remat'ed instructions are dead.
478 int VReg = ReMatRegs.find_first();
480 if (MRI->use_empty(VReg)) {
481 MachineInstr *DefMI = MRI->getVRegDef(VReg);
482 DefMI->eraseFromParent();
484 VReg = ReMatRegs.find_next(VReg);