1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Analysis/AliasAnalysis.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/ADT/BitVector.h"
45 #include "llvm/ADT/DenseMap.h"
46 #include "llvm/ADT/SmallSet.h"
47 #include "llvm/ADT/Statistic.h"
48 #include "llvm/ADT/STLExtras.h"
51 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
52 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
53 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
54 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
55 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
56 STATISTIC(NumReMats, "Number of instructions re-materialized");
57 STATISTIC(NumDeletes, "Number of dead instructions deleted");
60 class TwoAddressInstructionPass : public MachineFunctionPass {
61 const TargetInstrInfo *TII;
62 const TargetRegisterInfo *TRI;
63 MachineRegisterInfo *MRI;
67 // DistanceMap - Keep track the distance of a MI from the start of the
68 // current basic block.
69 DenseMap<MachineInstr*, unsigned> DistanceMap;
71 // SrcRegMap - A map from virtual registers to physical registers which
72 // are likely targets to be coalesced to due to copies from physical
73 // registers to virtual registers. e.g. v1024 = move r0.
74 DenseMap<unsigned, unsigned> SrcRegMap;
76 // DstRegMap - A map from virtual registers to physical registers which
77 // are likely targets to be coalesced to due to copies to physical
78 // registers from virtual registers. e.g. r1 = move v1024.
79 DenseMap<unsigned, unsigned> DstRegMap;
81 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
82 /// during the initial walk of the machine function.
83 SmallVector<MachineInstr*, 16> RegSequences;
85 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
87 MachineBasicBlock::iterator OldPos);
89 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
90 MachineInstr *MI, MachineInstr *DefMI,
91 MachineBasicBlock *MBB, unsigned Loc);
93 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
96 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
99 bool isProfitableToCommute(unsigned regB, unsigned regC,
100 MachineInstr *MI, MachineBasicBlock *MBB,
103 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
104 MachineFunction::iterator &mbbi,
105 unsigned RegB, unsigned RegC, unsigned Dist);
107 bool isProfitableToConv3Addr(unsigned RegA);
109 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
110 MachineBasicBlock::iterator &nmi,
111 MachineFunction::iterator &mbbi,
112 unsigned RegB, unsigned Dist);
114 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
115 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
116 SmallVector<NewKill, 4> &NewKills,
117 MachineBasicBlock *MBB, unsigned Dist);
118 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
119 MachineBasicBlock::iterator &nmi,
120 MachineFunction::iterator &mbbi, unsigned Dist);
122 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
123 MachineBasicBlock::iterator &nmi,
124 MachineFunction::iterator &mbbi,
125 unsigned SrcIdx, unsigned DstIdx,
128 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
129 SmallPtrSet<MachineInstr*, 8> &Processed);
131 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
132 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
133 /// sub-register references of the register defined by REG_SEQUENCE.
134 bool EliminateRegSequences();
136 static char ID; // Pass identification, replacement for typeid
137 TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
139 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
140 AU.setPreservesCFG();
141 AU.addRequired<AliasAnalysis>();
142 AU.addPreserved<LiveVariables>();
143 AU.addPreservedID(MachineLoopInfoID);
144 AU.addPreservedID(MachineDominatorsID);
146 AU.addPreservedID(StrongPHIEliminationID);
148 AU.addPreservedID(PHIEliminationID);
149 MachineFunctionPass::getAnalysisUsage(AU);
152 /// runOnMachineFunction - Pass entry point.
153 bool runOnMachineFunction(MachineFunction&);
157 char TwoAddressInstructionPass::ID = 0;
158 static RegisterPass<TwoAddressInstructionPass>
159 X("twoaddressinstruction", "Two-Address instruction pass");
161 const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
163 /// Sink3AddrInstruction - A two-address instruction has been converted to a
164 /// three-address instruction to avoid clobbering a register. Try to sink it
165 /// past the instruction that would kill the above mentioned register to reduce
166 /// register pressure.
167 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
168 MachineInstr *MI, unsigned SavedReg,
169 MachineBasicBlock::iterator OldPos) {
170 // Check if it's safe to move this instruction.
171 bool SeenStore = true; // Be conservative.
172 if (!MI->isSafeToMove(TII, AA, SeenStore))
176 SmallSet<unsigned, 4> UseRegs;
178 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
179 const MachineOperand &MO = MI->getOperand(i);
182 unsigned MOReg = MO.getReg();
185 if (MO.isUse() && MOReg != SavedReg)
186 UseRegs.insert(MO.getReg());
190 // Don't try to move it if it implicitly defines a register.
193 // For now, don't move any instructions that define multiple registers.
195 DefReg = MO.getReg();
198 // Find the instruction that kills SavedReg.
199 MachineInstr *KillMI = NULL;
200 for (MachineRegisterInfo::use_nodbg_iterator
201 UI = MRI->use_nodbg_begin(SavedReg),
202 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
203 MachineOperand &UseMO = UI.getOperand();
206 KillMI = UseMO.getParent();
210 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
213 // If any of the definitions are used by another instruction between the
214 // position and the kill use, then it's not safe to sink it.
216 // FIXME: This can be sped up if there is an easy way to query whether an
217 // instruction is before or after another instruction. Then we can use
218 // MachineRegisterInfo def / use instead.
219 MachineOperand *KillMO = NULL;
220 MachineBasicBlock::iterator KillPos = KillMI;
223 unsigned NumVisited = 0;
224 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
225 MachineInstr *OtherMI = I;
226 // DBG_VALUE cannot be counted against the limit.
227 if (OtherMI->isDebugValue())
229 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
232 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
233 MachineOperand &MO = OtherMI->getOperand(i);
236 unsigned MOReg = MO.getReg();
243 if (OtherMI == KillMI && MOReg == SavedReg)
244 // Save the operand that kills the register. We want to unset the kill
245 // marker if we can sink MI past it.
247 else if (UseRegs.count(MOReg))
248 // One of the uses is killed before the destination.
254 // Update kill and LV information.
255 KillMO->setIsKill(false);
256 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
257 KillMO->setIsKill(true);
260 LV->replaceKillInstruction(SavedReg, KillMI, MI);
262 // Move instruction to its destination.
264 MBB->insert(KillPos, MI);
270 /// isTwoAddrUse - Return true if the specified MI is using the specified
271 /// register as a two-address operand.
272 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
273 const TargetInstrDesc &TID = UseMI->getDesc();
274 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
275 MachineOperand &MO = UseMI->getOperand(i);
276 if (MO.isReg() && MO.getReg() == Reg &&
277 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
278 // Earlier use is a two-address one.
284 /// isProfitableToReMat - Return true if the heuristics determines it is likely
285 /// to be profitable to re-materialize the definition of Reg rather than copy
288 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
289 const TargetRegisterClass *RC,
290 MachineInstr *MI, MachineInstr *DefMI,
291 MachineBasicBlock *MBB, unsigned Loc) {
292 bool OtherUse = false;
293 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
294 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
295 MachineOperand &UseMO = UI.getOperand();
296 MachineInstr *UseMI = UseMO.getParent();
297 MachineBasicBlock *UseMBB = UseMI->getParent();
299 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
300 if (DI != DistanceMap.end() && DI->second == Loc)
301 continue; // Current use.
303 // There is at least one other use in the MBB that will clobber the
305 if (isTwoAddrUse(UseMI, Reg))
310 // If other uses in MBB are not two-address uses, then don't remat.
314 // No other uses in the same block, remat if it's defined in the same
315 // block so it does not unnecessarily extend the live range.
316 return MBB == DefMI->getParent();
319 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
320 /// last instruction in the MBB that defines the specified register and the
321 /// two-address instruction which is being processed. It also returns the last
322 /// def location by reference
323 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
324 MachineBasicBlock *MBB, unsigned Dist,
327 unsigned LastUse = Dist;
328 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
329 E = MRI->reg_end(); I != E; ++I) {
330 MachineOperand &MO = I.getOperand();
331 MachineInstr *MI = MO.getParent();
332 if (MI->getParent() != MBB || MI->isDebugValue())
334 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
335 if (DI == DistanceMap.end())
337 if (MO.isUse() && DI->second < LastUse)
338 LastUse = DI->second;
339 if (MO.isDef() && DI->second > LastDef)
340 LastDef = DI->second;
343 return !(LastUse > LastDef && LastUse < Dist);
346 MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
347 MachineBasicBlock *MBB,
349 unsigned LastUseDist = 0;
350 MachineInstr *LastUse = 0;
351 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
352 E = MRI->reg_end(); I != E; ++I) {
353 MachineOperand &MO = I.getOperand();
354 MachineInstr *MI = MO.getParent();
355 if (MI->getParent() != MBB || MI->isDebugValue())
357 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
358 if (DI == DistanceMap.end())
360 if (DI->second >= Dist)
363 if (MO.isUse() && DI->second > LastUseDist) {
365 LastUseDist = DI->second;
371 /// isCopyToReg - Return true if the specified MI is a copy instruction or
372 /// a extract_subreg instruction. It also returns the source and destination
373 /// registers and whether they are physical registers by reference.
374 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
375 unsigned &SrcReg, unsigned &DstReg,
376 bool &IsSrcPhys, bool &IsDstPhys) {
379 unsigned SrcSubIdx, DstSubIdx;
380 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
381 if (MI.isExtractSubreg()) {
382 DstReg = MI.getOperand(0).getReg();
383 SrcReg = MI.getOperand(1).getReg();
384 } else if (MI.isInsertSubreg()) {
385 DstReg = MI.getOperand(0).getReg();
386 SrcReg = MI.getOperand(2).getReg();
387 } else if (MI.isSubregToReg()) {
388 DstReg = MI.getOperand(0).getReg();
389 SrcReg = MI.getOperand(2).getReg();
394 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
395 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
401 /// isKilled - Test if the given register value, which is used by the given
402 /// instruction, is killed by the given instruction. This looks through
403 /// coalescable copies to see if the original value is potentially not killed.
405 /// For example, in this code:
407 /// %reg1034 = copy %reg1024
408 /// %reg1035 = copy %reg1025<kill>
409 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
411 /// %reg1034 is not considered to be killed, since it is copied from a
412 /// register which is not killed. Treating it as not killed lets the
413 /// normal heuristics commute the (two-address) add, which lets
414 /// coalescing eliminate the extra copy.
416 static bool isKilled(MachineInstr &MI, unsigned Reg,
417 const MachineRegisterInfo *MRI,
418 const TargetInstrInfo *TII) {
419 MachineInstr *DefMI = &MI;
421 if (!DefMI->killsRegister(Reg))
423 if (TargetRegisterInfo::isPhysicalRegister(Reg))
425 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
426 // If there are multiple defs, we can't do a simple analysis, so just
427 // go with what the kill flag says.
428 if (llvm::next(Begin) != MRI->def_end())
431 bool IsSrcPhys, IsDstPhys;
432 unsigned SrcReg, DstReg;
433 // If the def is something other than a copy, then it isn't going to
434 // be coalesced, so follow the kill flag.
435 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
441 /// isTwoAddrUse - Return true if the specified MI uses the specified register
442 /// as a two-address use. If so, return the destination register by reference.
443 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
444 const TargetInstrDesc &TID = MI.getDesc();
445 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands();
446 for (unsigned i = 0; i != NumOps; ++i) {
447 const MachineOperand &MO = MI.getOperand(i);
448 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
451 if (MI.isRegTiedToDefOperand(i, &ti)) {
452 DstReg = MI.getOperand(ti).getReg();
459 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
460 /// use, return the use instruction if it's a copy or a two-address use.
462 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
463 MachineRegisterInfo *MRI,
464 const TargetInstrInfo *TII,
466 unsigned &DstReg, bool &IsDstPhys) {
467 if (!MRI->hasOneNonDBGUse(Reg))
468 // None or more than one use.
470 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
471 if (UseMI.getParent() != MBB)
475 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
480 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
481 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
487 /// getMappedReg - Return the physical register the specified virtual register
488 /// might be mapped to.
490 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
491 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
492 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
493 if (SI == RegMap.end())
497 if (TargetRegisterInfo::isPhysicalRegister(Reg))
502 /// regsAreCompatible - Return true if the two registers are equal or aliased.
505 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
510 return TRI->regsOverlap(RegA, RegB);
514 /// isProfitableToReMat - Return true if it's potentially profitable to commute
515 /// the two-address instruction that's being processed.
517 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
518 MachineInstr *MI, MachineBasicBlock *MBB,
520 // Determine if it's profitable to commute this two address instruction. In
521 // general, we want no uses between this instruction and the definition of
522 // the two-address register.
524 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
525 // %reg1029<def> = MOV8rr %reg1028
526 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
527 // insert => %reg1030<def> = MOV8rr %reg1028
528 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
529 // In this case, it might not be possible to coalesce the second MOV8rr
530 // instruction if the first one is coalesced. So it would be profitable to
532 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
533 // %reg1029<def> = MOV8rr %reg1028
534 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
535 // insert => %reg1030<def> = MOV8rr %reg1029
536 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
538 if (!MI->killsRegister(regC))
541 // Ok, we have something like:
542 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
543 // let's see if it's worth commuting it.
545 // Look for situations like this:
546 // %reg1024<def> = MOV r1
547 // %reg1025<def> = MOV r0
548 // %reg1026<def> = ADD %reg1024, %reg1025
550 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
551 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
552 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
553 unsigned ToRegB = getMappedReg(regB, DstRegMap);
554 unsigned ToRegC = getMappedReg(regC, DstRegMap);
555 if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
556 (regsAreCompatible(FromRegB, ToRegC, TRI) ||
557 regsAreCompatible(FromRegC, ToRegB, TRI)))
560 // If there is a use of regC between its last def (could be livein) and this
561 // instruction, then bail.
562 unsigned LastDefC = 0;
563 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
566 // If there is a use of regB between its last def (could be livein) and this
567 // instruction, then go ahead and make this transformation.
568 unsigned LastDefB = 0;
569 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
572 // Since there are no intervening uses for both registers, then commute
573 // if the def of regC is closer. Its live interval is shorter.
574 return LastDefB && LastDefC && LastDefC > LastDefB;
577 /// CommuteInstruction - Commute a two-address instruction and update the basic
578 /// block, distance map, and live variables if needed. Return true if it is
581 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
582 MachineFunction::iterator &mbbi,
583 unsigned RegB, unsigned RegC, unsigned Dist) {
584 MachineInstr *MI = mi;
585 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
586 MachineInstr *NewMI = TII->commuteInstruction(MI);
589 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
593 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
594 // If the instruction changed to commute it, update livevar.
597 // Update live variables
598 LV->replaceKillInstruction(RegC, MI, NewMI);
600 mbbi->insert(mi, NewMI); // Insert the new inst
601 mbbi->erase(mi); // Nuke the old inst.
603 DistanceMap.insert(std::make_pair(NewMI, Dist));
606 // Update source register map.
607 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
609 unsigned RegA = MI->getOperand(0).getReg();
610 SrcRegMap[RegA] = FromRegC;
616 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
617 /// given 2-address instruction to a 3-address one.
619 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
620 // Look for situations like this:
621 // %reg1024<def> = MOV r1
622 // %reg1025<def> = MOV r0
623 // %reg1026<def> = ADD %reg1024, %reg1025
625 // Turn ADD into a 3-address instruction to avoid a copy.
626 unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
627 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
628 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
631 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
632 /// three address one. Return true if this transformation was successful.
634 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
635 MachineBasicBlock::iterator &nmi,
636 MachineFunction::iterator &mbbi,
637 unsigned RegB, unsigned Dist) {
638 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
640 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
641 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
644 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
645 // FIXME: Temporary workaround. If the new instruction doesn't
646 // uses RegB, convertToThreeAddress must have created more
647 // then one instruction.
648 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
650 mbbi->erase(mi); // Nuke the old inst.
653 DistanceMap.insert(std::make_pair(NewMI, Dist));
655 nmi = llvm::next(mi);
663 /// ProcessCopy - If the specified instruction is not yet processed, process it
664 /// if it's a copy. For a copy instruction, we find the physical registers the
665 /// source and destination registers might be mapped to. These are kept in
666 /// point-to maps used to determine future optimizations. e.g.
669 /// v1026 = add v1024, v1025
671 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
672 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
673 /// potentially joined with r1 on the output side. It's worthwhile to commute
674 /// 'add' to eliminate a copy.
675 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
676 MachineBasicBlock *MBB,
677 SmallPtrSet<MachineInstr*, 8> &Processed) {
678 if (Processed.count(MI))
681 bool IsSrcPhys, IsDstPhys;
682 unsigned SrcReg, DstReg;
683 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
686 if (IsDstPhys && !IsSrcPhys)
687 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
688 else if (!IsDstPhys && IsSrcPhys) {
689 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
691 assert(SrcRegMap[DstReg] == SrcReg &&
692 "Can't map to two src physical registers!");
694 SmallVector<unsigned, 4> VirtRegPairs;
697 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
698 IsCopy, NewReg, IsDstPhys)) {
700 if (!Processed.insert(UseMI))
704 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
705 if (DI != DistanceMap.end())
706 // Earlier in the same MBB.Reached via a back edge.
710 VirtRegPairs.push_back(NewReg);
713 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
715 assert(SrcRegMap[NewReg] == DstReg &&
716 "Can't map to two src physical registers!");
717 VirtRegPairs.push_back(NewReg);
721 if (!VirtRegPairs.empty()) {
722 unsigned ToReg = VirtRegPairs.back();
723 VirtRegPairs.pop_back();
724 while (!VirtRegPairs.empty()) {
725 unsigned FromReg = VirtRegPairs.back();
726 VirtRegPairs.pop_back();
727 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
729 assert(DstRegMap[FromReg] == ToReg &&
730 "Can't map to two dst physical registers!");
736 Processed.insert(MI);
739 /// isSafeToDelete - If the specified instruction does not produce any side
740 /// effects and all of its defs are dead, then it's safe to delete.
741 static bool isSafeToDelete(MachineInstr *MI,
742 const TargetInstrInfo *TII,
743 SmallVector<unsigned, 4> &Kills) {
744 const TargetInstrDesc &TID = MI->getDesc();
745 if (TID.mayStore() || TID.isCall())
747 if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
750 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
751 MachineOperand &MO = MI->getOperand(i);
754 if (MO.isDef() && !MO.isDead())
756 if (MO.isUse() && MO.isKill())
757 Kills.push_back(MO.getReg());
762 /// canUpdateDeletedKills - Check if all the registers listed in Kills are
763 /// killed by instructions in MBB preceding the current instruction at
764 /// position Dist. If so, return true and record information about the
765 /// preceding kills in NewKills.
766 bool TwoAddressInstructionPass::
767 canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
768 SmallVector<NewKill, 4> &NewKills,
769 MachineBasicBlock *MBB, unsigned Dist) {
770 while (!Kills.empty()) {
771 unsigned Kill = Kills.back();
773 if (TargetRegisterInfo::isPhysicalRegister(Kill))
776 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
780 bool isModRef = LastKill->modifiesRegister(Kill);
781 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
787 /// DeleteUnusedInstr - If an instruction with a tied register operand can
788 /// be safely deleted, just delete it.
790 TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
791 MachineBasicBlock::iterator &nmi,
792 MachineFunction::iterator &mbbi,
794 // Check if the instruction has no side effects and if all its defs are dead.
795 SmallVector<unsigned, 4> Kills;
796 if (!isSafeToDelete(mi, TII, Kills))
799 // If this instruction kills some virtual registers, we need to
800 // update the kill information. If it's not possible to do so,
802 SmallVector<NewKill, 4> NewKills;
803 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
807 while (!NewKills.empty()) {
808 MachineInstr *NewKill = NewKills.back().second;
809 unsigned Kill = NewKills.back().first.first;
810 bool isDead = NewKills.back().first.second;
812 if (LV->removeVirtualRegisterKilled(Kill, mi)) {
814 LV->addVirtualRegisterDead(Kill, NewKill);
816 LV->addVirtualRegisterKilled(Kill, NewKill);
821 mbbi->erase(mi); // Nuke the old inst.
826 /// TryInstructionTransform - For the case where an instruction has a single
827 /// pair of tied register operands, attempt some transformations that may
828 /// either eliminate the tied operands or improve the opportunities for
829 /// coalescing away the register copy. Returns true if the tied operands
830 /// are eliminated altogether.
831 bool TwoAddressInstructionPass::
832 TryInstructionTransform(MachineBasicBlock::iterator &mi,
833 MachineBasicBlock::iterator &nmi,
834 MachineFunction::iterator &mbbi,
835 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
836 const TargetInstrDesc &TID = mi->getDesc();
837 unsigned regA = mi->getOperand(DstIdx).getReg();
838 unsigned regB = mi->getOperand(SrcIdx).getReg();
840 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
841 "cannot make instruction into two-address form");
843 // If regA is dead and the instruction can be deleted, just delete
844 // it so it doesn't clobber regB.
845 bool regBKilled = isKilled(*mi, regB, MRI, TII);
846 if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
847 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
849 return true; // Done with this instruction.
852 // Check if it is profitable to commute the operands.
853 unsigned SrcOp1, SrcOp2;
855 unsigned regCIdx = ~0U;
856 bool TryCommute = false;
857 bool AggressiveCommute = false;
858 if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
859 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
860 if (SrcIdx == SrcOp1)
862 else if (SrcIdx == SrcOp2)
865 if (regCIdx != ~0U) {
866 regC = mi->getOperand(regCIdx).getReg();
867 if (!regBKilled && isKilled(*mi, regC, MRI, TII))
868 // If C dies but B does not, swap the B and C operands.
869 // This makes the live ranges of A and C joinable.
871 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
873 AggressiveCommute = true;
878 // If it's profitable to commute, try to do so.
879 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
881 if (AggressiveCommute)
886 if (TID.isConvertibleTo3Addr()) {
887 // This instruction is potentially convertible to a true
888 // three-address instruction. Check if it is profitable.
889 if (!regBKilled || isProfitableToConv3Addr(regA)) {
890 // Try to convert it.
891 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
892 ++NumConvertedTo3Addr;
893 return true; // Done with this instruction.
900 /// runOnMachineFunction - Reduce two-address instructions to two operands.
902 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
903 DEBUG(dbgs() << "Machine Function\n");
904 const TargetMachine &TM = MF.getTarget();
905 MRI = &MF.getRegInfo();
906 TII = TM.getInstrInfo();
907 TRI = TM.getRegisterInfo();
908 LV = getAnalysisIfAvailable<LiveVariables>();
909 AA = &getAnalysis<AliasAnalysis>();
911 bool MadeChange = false;
913 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
914 DEBUG(dbgs() << "********** Function: "
915 << MF.getFunction()->getName() << '\n');
917 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
919 ReMatRegs.resize(MRI->getLastVirtReg()+1);
921 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
923 TiedOperandMap TiedOperands(4);
925 SmallPtrSet<MachineInstr*, 8> Processed;
926 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
927 mbbi != mbbe; ++mbbi) {
933 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
935 MachineBasicBlock::iterator nmi = llvm::next(mi);
936 if (mi->isDebugValue()) {
941 // Remember REG_SEQUENCE instructions, we'll deal with them later.
942 if (mi->isRegSequence())
943 RegSequences.push_back(&*mi);
945 const TargetInstrDesc &TID = mi->getDesc();
946 bool FirstTied = true;
948 DistanceMap.insert(std::make_pair(mi, ++Dist));
950 ProcessCopy(&*mi, &*mbbi, Processed);
952 // First scan through all the tied register uses in this instruction
953 // and record a list of pairs of tied operands for each register.
954 unsigned NumOps = mi->isInlineAsm()
955 ? mi->getNumOperands() : TID.getNumOperands();
956 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
958 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
963 ++NumTwoAddressInstrs;
964 DEBUG(dbgs() << '\t' << *mi);
967 assert(mi->getOperand(SrcIdx).isReg() &&
968 mi->getOperand(SrcIdx).getReg() &&
969 mi->getOperand(SrcIdx).isUse() &&
970 "two address instruction invalid");
972 unsigned regB = mi->getOperand(SrcIdx).getReg();
973 TiedOperandMap::iterator OI = TiedOperands.find(regB);
974 if (OI == TiedOperands.end()) {
975 SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
976 OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
978 OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
981 // Now iterate over the information collected above.
982 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
983 OE = TiedOperands.end(); OI != OE; ++OI) {
984 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
986 // If the instruction has a single pair of tied operands, try some
987 // transformations that may either eliminate the tied operands or
988 // improve the opportunities for coalescing away the register copy.
989 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
990 unsigned SrcIdx = TiedPairs[0].first;
991 unsigned DstIdx = TiedPairs[0].second;
993 // If the registers are already equal, nothing needs to be done.
994 if (mi->getOperand(SrcIdx).getReg() ==
995 mi->getOperand(DstIdx).getReg())
996 break; // Done with this instruction.
998 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
999 break; // The tied operands have been eliminated.
1002 bool RemovedKillFlag = false;
1003 bool AllUsesCopied = true;
1004 unsigned LastCopiedReg = 0;
1005 unsigned regB = OI->first;
1006 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1007 unsigned SrcIdx = TiedPairs[tpi].first;
1008 unsigned DstIdx = TiedPairs[tpi].second;
1009 unsigned regA = mi->getOperand(DstIdx).getReg();
1010 // Grab regB from the instruction because it may have changed if the
1011 // instruction was commuted.
1012 regB = mi->getOperand(SrcIdx).getReg();
1015 // The register is tied to multiple destinations (or else we would
1016 // not have continued this far), but this use of the register
1017 // already matches the tied destination. Leave it.
1018 AllUsesCopied = false;
1021 LastCopiedReg = regA;
1023 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1024 "cannot make instruction into two-address form");
1027 // First, verify that we don't have a use of "a" in the instruction
1028 // (a = b + a for example) because our transformation will not
1029 // work. This should never occur because we are in SSA form.
1030 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1031 assert(i == DstIdx ||
1032 !mi->getOperand(i).isReg() ||
1033 mi->getOperand(i).getReg() != regA);
1036 // Emit a copy or rematerialize the definition.
1037 const TargetRegisterClass *rc = MRI->getRegClass(regB);
1038 MachineInstr *DefMI = MRI->getVRegDef(regB);
1039 // If it's safe and profitable, remat the definition instead of
1042 DefMI->getDesc().isAsCheapAsAMove() &&
1043 DefMI->isSafeToReMat(TII, AA, regB) &&
1044 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1045 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
1046 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1047 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, TRI);
1048 ReMatRegs.set(regB);
1051 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
1053 assert(Emitted && "Unable to issue a copy instruction!\n");
1056 MachineBasicBlock::iterator prevMI = prior(mi);
1057 // Update DistanceMap.
1058 DistanceMap.insert(std::make_pair(prevMI, Dist));
1059 DistanceMap[mi] = ++Dist;
1061 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
1063 MachineOperand &MO = mi->getOperand(SrcIdx);
1064 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1065 "inconsistent operand info for 2-reg pass");
1067 MO.setIsKill(false);
1068 RemovedKillFlag = true;
1073 if (AllUsesCopied) {
1074 // Replace other (un-tied) uses of regB with LastCopiedReg.
1075 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1076 MachineOperand &MO = mi->getOperand(i);
1077 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1079 MO.setIsKill(false);
1080 RemovedKillFlag = true;
1082 MO.setReg(LastCopiedReg);
1086 // Update live variables for regB.
1087 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1088 LV->addVirtualRegisterKilled(regB, prior(mi));
1090 } else if (RemovedKillFlag) {
1091 // Some tied uses of regB matched their destination registers, so
1092 // regB is still used in this instruction, but a kill flag was
1093 // removed from a different tied use of regB, so now we need to add
1094 // a kill flag to one of the remaining uses of regB.
1095 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1096 MachineOperand &MO = mi->getOperand(i);
1097 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1106 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1109 // Clear TiedOperands here instead of at the top of the loop
1110 // since most instructions do not have tied operands.
1111 TiedOperands.clear();
1116 // Some remat'ed instructions are dead.
1117 int VReg = ReMatRegs.find_first();
1118 while (VReg != -1) {
1119 if (MRI->use_nodbg_empty(VReg)) {
1120 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1121 DefMI->eraseFromParent();
1123 VReg = ReMatRegs.find_next(VReg);
1126 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1127 // SSA form. It's now safe to de-SSA.
1128 MadeChange |= EliminateRegSequences();
1133 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1134 unsigned DstReg, unsigned SrcIdx,
1135 MachineRegisterInfo *MRI) {
1136 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1137 UE = MRI->reg_end(); RI != UE; ) {
1138 MachineOperand &MO = RI.getOperand();
1141 MO.setSubReg(SrcIdx);
1145 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1146 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1147 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1149 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1150 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1152 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1153 bool TwoAddressInstructionPass::EliminateRegSequences() {
1154 if (RegSequences.empty())
1157 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1158 MachineInstr *MI = RegSequences[i];
1159 unsigned DstReg = MI->getOperand(0).getReg();
1160 if (MI->getOperand(0).getSubReg() ||
1161 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1162 !(MI->getNumOperands() & 1)) {
1163 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1164 llvm_unreachable(0);
1166 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1167 unsigned SrcReg = MI->getOperand(i).getReg();
1168 if (MI->getOperand(i).getSubReg() ||
1169 TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1170 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1171 llvm_unreachable(0);
1173 unsigned SrcIdx = MI->getOperand(i+1).getImm();
1174 UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI);
1177 DEBUG(dbgs() << "Eliminated: " << *MI);
1178 MI->eraseFromParent();