1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/ADT/STLExtras.h"
46 Statistic<> NumTwoAddressInstrs("twoaddressinstruction",
47 "Number of two-address instructions");
48 Statistic<> NumCommuted("twoaddressinstruction",
49 "Number of instructions commuted to coalesce");
50 Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
51 "Number of instructions promoted to 3-address");
53 struct TwoAddressInstructionPass : public MachineFunctionPass {
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
56 /// runOnMachineFunction - pass entry point
57 bool runOnMachineFunction(MachineFunction&);
60 RegisterPass<TwoAddressInstructionPass>
61 X("twoaddressinstruction", "Two-Address instruction pass");
64 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
66 void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
67 AU.addRequired<LiveVariables>();
68 AU.addPreserved<LiveVariables>();
69 AU.addPreservedID(PHIEliminationID);
70 MachineFunctionPass::getAnalysisUsage(AU);
73 /// runOnMachineFunction - Reduce two-address instructions to two
76 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
77 DEBUG(std::cerr << "Machine Function\n");
78 const TargetMachine &TM = MF.getTarget();
79 const MRegisterInfo &MRI = *TM.getRegisterInfo();
80 const TargetInstrInfo &TII = *TM.getInstrInfo();
81 LiveVariables &LV = getAnalysis<LiveVariables>();
83 bool MadeChange = false;
85 DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
86 DEBUG(std::cerr << "********** Function: "
87 << MF.getFunction()->getName() << '\n');
89 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
90 mbbi != mbbe; ++mbbi) {
91 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
93 unsigned opcode = mi->getOpcode();
95 // ignore if it is not a two-address instruction
96 if (!TII.isTwoAddrInstr(opcode))
99 ++NumTwoAddressInstrs;
100 DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
101 assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
102 mi->getOperand(1).isUse() && "two address instruction invalid");
104 // if the two operands are the same we just remove the use
105 // and mark the def as def&use, otherwise we have to insert a copy.
106 if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
112 unsigned regA = mi->getOperand(0).getReg();
113 unsigned regB = mi->getOperand(1).getReg();
115 assert(MRegisterInfo::isVirtualRegister(regA) &&
116 MRegisterInfo::isVirtualRegister(regB) &&
117 "cannot update physical register live information");
120 // First, verify that we do not have a use of a in the instruction (a =
121 // b + a for example) because our transformation will not work. This
122 // should never occur because we are in SSA form.
123 for (unsigned i = 1; i != mi->getNumOperands(); ++i)
124 assert(!mi->getOperand(i).isRegister() ||
125 mi->getOperand(i).getReg() != regA);
128 // If this instruction is not the killing user of B, see if we can
129 // rearrange the code to make it so. Making it the killing user will
130 // allow us to coalesce A and B together, eliminating the copy we are
132 if (!LV.KillsRegister(mi, regB)) {
133 const TargetInstrDescriptor &TID = TII.get(opcode);
135 // If this instruction is commutative, check to see if C dies. If so,
136 // swap the B and C operands. This makes the live ranges of A and C
138 if (TID.Flags & M_COMMUTABLE) {
139 assert(mi->getOperand(2).isRegister() &&
140 "Not a proper commutative instruction!");
141 unsigned regC = mi->getOperand(2).getReg();
142 if (LV.KillsRegister(mi, regC)) {
143 DEBUG(std::cerr << "2addr: COMMUTING : " << *mi);
144 MachineInstr *NewMI = TII.commuteInstruction(mi);
146 DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
148 DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
149 // If the instruction changed to commute it, update livevar.
151 LV.instructionChanged(mi, NewMI); // Update live variables
152 mbbi->insert(mi, NewMI); // Insert the new inst
153 mbbi->erase(mi); // Nuke the old inst.
159 goto InstructionRearranged;
163 // If this instruction is potentially convertible to a true
164 // three-address instruction,
165 if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
166 if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
167 DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
168 DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New);
169 LV.instructionChanged(mi, New); // Update live variables
170 mbbi->insert(mi, New); // Insert the new inst
171 mbbi->erase(mi); // Nuke the old inst.
173 ++NumConvertedTo3Addr;
174 assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
175 "convertToThreeAddress returned a 2-addr instruction??");
176 // Done with this instruction.
180 InstructionRearranged:
181 const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
182 MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
184 MachineBasicBlock::iterator prevMi = prior(mi);
185 DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
187 // Update live variables for regA
188 LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
189 varInfo.DefInst = prevMi;
191 // update live variables for regB
192 if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
193 LV.addVirtualRegisterKilled(regB, prevMi);
195 if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
196 LV.addVirtualRegisterDead(regB, prevMi);
198 // replace all occurences of regB with regA
199 for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
200 if (mi->getOperand(i).isRegister() &&
201 mi->getOperand(i).getReg() == regB)
202 mi->SetMachineOperandReg(i, regA);
206 assert(mi->getOperand(0).isDef());
207 mi->getOperand(0).setUse();
208 mi->RemoveOperand(1);
211 DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));