1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/Analysis/AliasAnalysis.h"
39 #include "llvm/MC/MCInstrItineraries.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/ADT/BitVector.h"
47 #include "llvm/ADT/DenseMap.h"
48 #include "llvm/ADT/SmallSet.h"
49 #include "llvm/ADT/Statistic.h"
50 #include "llvm/ADT/STLExtras.h"
53 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
54 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
55 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
56 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
57 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
58 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
59 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
62 class TwoAddressInstructionPass : public MachineFunctionPass {
63 const TargetInstrInfo *TII;
64 const TargetRegisterInfo *TRI;
65 const InstrItineraryData *InstrItins;
66 MachineRegisterInfo *MRI;
69 CodeGenOpt::Level OptLevel;
71 // DistanceMap - Keep track the distance of a MI from the start of the
72 // current basic block.
73 DenseMap<MachineInstr*, unsigned> DistanceMap;
75 // SrcRegMap - A map from virtual registers to physical registers which
76 // are likely targets to be coalesced to due to copies from physical
77 // registers to virtual registers. e.g. v1024 = move r0.
78 DenseMap<unsigned, unsigned> SrcRegMap;
80 // DstRegMap - A map from virtual registers to physical registers which
81 // are likely targets to be coalesced to due to copies to physical
82 // registers from virtual registers. e.g. r1 = move v1024.
83 DenseMap<unsigned, unsigned> DstRegMap;
85 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
86 /// during the initial walk of the machine function.
87 SmallVector<MachineInstr*, 16> RegSequences;
89 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
91 MachineBasicBlock::iterator OldPos);
93 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
96 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
97 MachineInstr *MI, MachineBasicBlock *MBB,
100 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
101 MachineFunction::iterator &mbbi,
102 unsigned RegB, unsigned RegC, unsigned Dist);
104 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
106 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
107 MachineBasicBlock::iterator &nmi,
108 MachineFunction::iterator &mbbi,
109 unsigned RegA, unsigned RegB, unsigned Dist);
111 bool isDefTooClose(unsigned Reg, unsigned Dist,
112 MachineInstr *MI, MachineBasicBlock *MBB);
114 bool RescheduleMIBelowKill(MachineBasicBlock *MBB,
115 MachineBasicBlock::iterator &mi,
116 MachineBasicBlock::iterator &nmi,
118 bool RescheduleKillAboveMI(MachineBasicBlock *MBB,
119 MachineBasicBlock::iterator &mi,
120 MachineBasicBlock::iterator &nmi,
123 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
124 MachineBasicBlock::iterator &nmi,
125 MachineFunction::iterator &mbbi,
126 unsigned SrcIdx, unsigned DstIdx,
128 SmallPtrSet<MachineInstr*, 8> &Processed);
130 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
131 SmallPtrSet<MachineInstr*, 8> &Processed);
133 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
134 SmallPtrSet<MachineInstr*, 8> &Processed);
136 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
138 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
139 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
140 /// sub-register references of the register defined by REG_SEQUENCE.
141 bool EliminateRegSequences();
144 static char ID; // Pass identification, replacement for typeid
145 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
146 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
149 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
150 AU.setPreservesCFG();
151 AU.addRequired<AliasAnalysis>();
152 AU.addPreserved<LiveVariables>();
153 AU.addPreservedID(MachineLoopInfoID);
154 AU.addPreservedID(MachineDominatorsID);
155 MachineFunctionPass::getAnalysisUsage(AU);
158 /// runOnMachineFunction - Pass entry point.
159 bool runOnMachineFunction(MachineFunction&);
163 char TwoAddressInstructionPass::ID = 0;
164 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
165 "Two-Address instruction pass", false, false)
166 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
167 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
168 "Two-Address instruction pass", false, false)
170 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
172 /// Sink3AddrInstruction - A two-address instruction has been converted to a
173 /// three-address instruction to avoid clobbering a register. Try to sink it
174 /// past the instruction that would kill the above mentioned register to reduce
175 /// register pressure.
176 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
177 MachineInstr *MI, unsigned SavedReg,
178 MachineBasicBlock::iterator OldPos) {
179 // FIXME: Shouldn't we be trying to do this before we three-addressify the
180 // instruction? After this transformation is done, we no longer need
181 // the instruction to be in three-address form.
183 // Check if it's safe to move this instruction.
184 bool SeenStore = true; // Be conservative.
185 if (!MI->isSafeToMove(TII, AA, SeenStore))
189 SmallSet<unsigned, 4> UseRegs;
191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
192 const MachineOperand &MO = MI->getOperand(i);
195 unsigned MOReg = MO.getReg();
198 if (MO.isUse() && MOReg != SavedReg)
199 UseRegs.insert(MO.getReg());
203 // Don't try to move it if it implicitly defines a register.
206 // For now, don't move any instructions that define multiple registers.
208 DefReg = MO.getReg();
211 // Find the instruction that kills SavedReg.
212 MachineInstr *KillMI = NULL;
213 for (MachineRegisterInfo::use_nodbg_iterator
214 UI = MRI->use_nodbg_begin(SavedReg),
215 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
216 MachineOperand &UseMO = UI.getOperand();
219 KillMI = UseMO.getParent();
223 // If we find the instruction that kills SavedReg, and it is in an
224 // appropriate location, we can try to sink the current instruction
226 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
227 KillMI->isTerminator())
230 // If any of the definitions are used by another instruction between the
231 // position and the kill use, then it's not safe to sink it.
233 // FIXME: This can be sped up if there is an easy way to query whether an
234 // instruction is before or after another instruction. Then we can use
235 // MachineRegisterInfo def / use instead.
236 MachineOperand *KillMO = NULL;
237 MachineBasicBlock::iterator KillPos = KillMI;
240 unsigned NumVisited = 0;
241 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
242 MachineInstr *OtherMI = I;
243 // DBG_VALUE cannot be counted against the limit.
244 if (OtherMI->isDebugValue())
246 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
249 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
250 MachineOperand &MO = OtherMI->getOperand(i);
253 unsigned MOReg = MO.getReg();
260 if (OtherMI == KillMI && MOReg == SavedReg)
261 // Save the operand that kills the register. We want to unset the kill
262 // marker if we can sink MI past it.
264 else if (UseRegs.count(MOReg))
265 // One of the uses is killed before the destination.
271 // Update kill and LV information.
272 KillMO->setIsKill(false);
273 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
274 KillMO->setIsKill(true);
277 LV->replaceKillInstruction(SavedReg, KillMI, MI);
279 // Move instruction to its destination.
281 MBB->insert(KillPos, MI);
287 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
288 /// last instruction in the MBB that defines the specified register and the
289 /// two-address instruction which is being processed. It also returns the last
290 /// def location by reference
291 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
292 MachineBasicBlock *MBB, unsigned Dist,
295 unsigned LastUse = Dist;
296 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
297 E = MRI->reg_end(); I != E; ++I) {
298 MachineOperand &MO = I.getOperand();
299 MachineInstr *MI = MO.getParent();
300 if (MI->getParent() != MBB || MI->isDebugValue())
302 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
303 if (DI == DistanceMap.end())
305 if (MO.isUse() && DI->second < LastUse)
306 LastUse = DI->second;
307 if (MO.isDef() && DI->second > LastDef)
308 LastDef = DI->second;
311 return !(LastUse > LastDef && LastUse < Dist);
314 /// isCopyToReg - Return true if the specified MI is a copy instruction or
315 /// a extract_subreg instruction. It also returns the source and destination
316 /// registers and whether they are physical registers by reference.
317 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
318 unsigned &SrcReg, unsigned &DstReg,
319 bool &IsSrcPhys, bool &IsDstPhys) {
323 DstReg = MI.getOperand(0).getReg();
324 SrcReg = MI.getOperand(1).getReg();
325 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
326 DstReg = MI.getOperand(0).getReg();
327 SrcReg = MI.getOperand(2).getReg();
331 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
332 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
336 /// isKilled - Test if the given register value, which is used by the given
337 /// instruction, is killed by the given instruction. This looks through
338 /// coalescable copies to see if the original value is potentially not killed.
340 /// For example, in this code:
342 /// %reg1034 = copy %reg1024
343 /// %reg1035 = copy %reg1025<kill>
344 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
346 /// %reg1034 is not considered to be killed, since it is copied from a
347 /// register which is not killed. Treating it as not killed lets the
348 /// normal heuristics commute the (two-address) add, which lets
349 /// coalescing eliminate the extra copy.
351 static bool isKilled(MachineInstr &MI, unsigned Reg,
352 const MachineRegisterInfo *MRI,
353 const TargetInstrInfo *TII) {
354 MachineInstr *DefMI = &MI;
356 if (!DefMI->killsRegister(Reg))
358 if (TargetRegisterInfo::isPhysicalRegister(Reg))
360 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
361 // If there are multiple defs, we can't do a simple analysis, so just
362 // go with what the kill flag says.
363 if (llvm::next(Begin) != MRI->def_end())
366 bool IsSrcPhys, IsDstPhys;
367 unsigned SrcReg, DstReg;
368 // If the def is something other than a copy, then it isn't going to
369 // be coalesced, so follow the kill flag.
370 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
376 /// isTwoAddrUse - Return true if the specified MI uses the specified register
377 /// as a two-address use. If so, return the destination register by reference.
378 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
379 const MCInstrDesc &MCID = MI.getDesc();
380 unsigned NumOps = MI.isInlineAsm()
381 ? MI.getNumOperands() : MCID.getNumOperands();
382 for (unsigned i = 0; i != NumOps; ++i) {
383 const MachineOperand &MO = MI.getOperand(i);
384 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
387 if (MI.isRegTiedToDefOperand(i, &ti)) {
388 DstReg = MI.getOperand(ti).getReg();
395 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
396 /// use, return the use instruction if it's a copy or a two-address use.
398 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
399 MachineRegisterInfo *MRI,
400 const TargetInstrInfo *TII,
402 unsigned &DstReg, bool &IsDstPhys) {
403 if (!MRI->hasOneNonDBGUse(Reg))
404 // None or more than one use.
406 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
407 if (UseMI.getParent() != MBB)
411 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
416 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
417 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
423 /// getMappedReg - Return the physical register the specified virtual register
424 /// might be mapped to.
426 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
427 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
428 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
429 if (SI == RegMap.end())
433 if (TargetRegisterInfo::isPhysicalRegister(Reg))
438 /// regsAreCompatible - Return true if the two registers are equal or aliased.
441 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
446 return TRI->regsOverlap(RegA, RegB);
450 /// isProfitableToCommute - Return true if it's potentially profitable to commute
451 /// the two-address instruction that's being processed.
453 TwoAddressInstructionPass::isProfitableToCommute(unsigned regA, unsigned regB,
455 MachineInstr *MI, MachineBasicBlock *MBB,
457 if (OptLevel == CodeGenOpt::None)
460 // Determine if it's profitable to commute this two address instruction. In
461 // general, we want no uses between this instruction and the definition of
462 // the two-address register.
464 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
465 // %reg1029<def> = MOV8rr %reg1028
466 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
467 // insert => %reg1030<def> = MOV8rr %reg1028
468 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
469 // In this case, it might not be possible to coalesce the second MOV8rr
470 // instruction if the first one is coalesced. So it would be profitable to
472 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
473 // %reg1029<def> = MOV8rr %reg1028
474 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
475 // insert => %reg1030<def> = MOV8rr %reg1029
476 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
478 if (!MI->killsRegister(regC))
481 // Ok, we have something like:
482 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
483 // let's see if it's worth commuting it.
485 // Look for situations like this:
486 // %reg1024<def> = MOV r1
487 // %reg1025<def> = MOV r0
488 // %reg1026<def> = ADD %reg1024, %reg1025
490 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
491 unsigned ToRegA = getMappedReg(regA, DstRegMap);
493 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
494 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
495 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
496 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
498 return !BComp && CComp;
501 // If there is a use of regC between its last def (could be livein) and this
502 // instruction, then bail.
503 unsigned LastDefC = 0;
504 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
507 // If there is a use of regB between its last def (could be livein) and this
508 // instruction, then go ahead and make this transformation.
509 unsigned LastDefB = 0;
510 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
513 // Since there are no intervening uses for both registers, then commute
514 // if the def of regC is closer. Its live interval is shorter.
515 return LastDefB && LastDefC && LastDefC > LastDefB;
518 /// CommuteInstruction - Commute a two-address instruction and update the basic
519 /// block, distance map, and live variables if needed. Return true if it is
522 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
523 MachineFunction::iterator &mbbi,
524 unsigned RegB, unsigned RegC, unsigned Dist) {
525 MachineInstr *MI = mi;
526 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
527 MachineInstr *NewMI = TII->commuteInstruction(MI);
530 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
534 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
535 // If the instruction changed to commute it, update livevar.
538 // Update live variables
539 LV->replaceKillInstruction(RegC, MI, NewMI);
541 mbbi->insert(mi, NewMI); // Insert the new inst
542 mbbi->erase(mi); // Nuke the old inst.
544 DistanceMap.insert(std::make_pair(NewMI, Dist));
547 // Update source register map.
548 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
550 unsigned RegA = MI->getOperand(0).getReg();
551 SrcRegMap[RegA] = FromRegC;
557 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
558 /// given 2-address instruction to a 3-address one.
560 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
561 // Look for situations like this:
562 // %reg1024<def> = MOV r1
563 // %reg1025<def> = MOV r0
564 // %reg1026<def> = ADD %reg1024, %reg1025
566 // Turn ADD into a 3-address instruction to avoid a copy.
567 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
570 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
571 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
574 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
575 /// three address one. Return true if this transformation was successful.
577 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
578 MachineBasicBlock::iterator &nmi,
579 MachineFunction::iterator &mbbi,
580 unsigned RegA, unsigned RegB,
582 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
584 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
585 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
588 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
589 // FIXME: Temporary workaround. If the new instruction doesn't
590 // uses RegB, convertToThreeAddress must have created more
591 // then one instruction.
592 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
594 mbbi->erase(mi); // Nuke the old inst.
597 DistanceMap.insert(std::make_pair(NewMI, Dist));
599 nmi = llvm::next(mi);
602 // Update source and destination register maps.
603 SrcRegMap.erase(RegA);
604 DstRegMap.erase(RegB);
611 /// ScanUses - Scan forward recursively for only uses, update maps if the use
612 /// is a copy or a two-address instruction.
614 TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
615 SmallPtrSet<MachineInstr*, 8> &Processed) {
616 SmallVector<unsigned, 4> VirtRegPairs;
620 unsigned Reg = DstReg;
621 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
622 NewReg, IsDstPhys)) {
623 if (IsCopy && !Processed.insert(UseMI))
626 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
627 if (DI != DistanceMap.end())
628 // Earlier in the same MBB.Reached via a back edge.
632 VirtRegPairs.push_back(NewReg);
635 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
637 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
638 VirtRegPairs.push_back(NewReg);
642 if (!VirtRegPairs.empty()) {
643 unsigned ToReg = VirtRegPairs.back();
644 VirtRegPairs.pop_back();
645 while (!VirtRegPairs.empty()) {
646 unsigned FromReg = VirtRegPairs.back();
647 VirtRegPairs.pop_back();
648 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
650 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
653 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
655 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
659 /// ProcessCopy - If the specified instruction is not yet processed, process it
660 /// if it's a copy. For a copy instruction, we find the physical registers the
661 /// source and destination registers might be mapped to. These are kept in
662 /// point-to maps used to determine future optimizations. e.g.
665 /// v1026 = add v1024, v1025
667 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
668 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
669 /// potentially joined with r1 on the output side. It's worthwhile to commute
670 /// 'add' to eliminate a copy.
671 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
672 MachineBasicBlock *MBB,
673 SmallPtrSet<MachineInstr*, 8> &Processed) {
674 if (Processed.count(MI))
677 bool IsSrcPhys, IsDstPhys;
678 unsigned SrcReg, DstReg;
679 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
682 if (IsDstPhys && !IsSrcPhys)
683 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
684 else if (!IsDstPhys && IsSrcPhys) {
685 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
687 assert(SrcRegMap[DstReg] == SrcReg &&
688 "Can't map to two src physical registers!");
690 ScanUses(DstReg, MBB, Processed);
693 Processed.insert(MI);
697 /// RescheduleMIBelowKill - If there is one more local instruction that reads
698 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
699 /// instruction in order to eliminate the need for the copy.
701 TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB,
702 MachineBasicBlock::iterator &mi,
703 MachineBasicBlock::iterator &nmi,
705 // Bail immediately if we don't have LV available. We use it to find kills
710 MachineInstr *MI = &*mi;
711 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
712 if (DI == DistanceMap.end())
713 // Must be created from unfolded load. Don't waste time trying this.
716 MachineInstr *KillMI = LV->getVarInfo(Reg).findKill(MBB);
717 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
718 // Don't mess with copies, they may be coalesced later.
721 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
722 KillMI->isBranch() || KillMI->isTerminator())
723 // Don't move pass calls, etc.
727 if (isTwoAddrUse(*KillMI, Reg, DstReg))
730 bool SeenStore = true;
731 if (!MI->isSafeToMove(TII, AA, SeenStore))
734 if (TII->getInstrLatency(InstrItins, MI) > 1)
735 // FIXME: Needs more sophisticated heuristics.
738 SmallSet<unsigned, 2> Uses;
739 SmallSet<unsigned, 2> Kills;
740 SmallSet<unsigned, 2> Defs;
741 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
742 const MachineOperand &MO = MI->getOperand(i);
745 unsigned MOReg = MO.getReg();
752 if (MO.isKill() && MOReg != Reg)
757 // Move the copies connected to MI down as well.
758 MachineBasicBlock::iterator From = MI;
759 MachineBasicBlock::iterator To = llvm::next(From);
760 while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) {
761 Defs.insert(To->getOperand(0).getReg());
765 // Check if the reschedule will not break depedencies.
766 unsigned NumVisited = 0;
767 MachineBasicBlock::iterator KillPos = KillMI;
769 for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) {
770 MachineInstr *OtherMI = I;
771 // DBG_VALUE cannot be counted against the limit.
772 if (OtherMI->isDebugValue())
774 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
777 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
778 OtherMI->isBranch() || OtherMI->isTerminator())
779 // Don't move pass calls, etc.
781 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
782 const MachineOperand &MO = OtherMI->getOperand(i);
785 unsigned MOReg = MO.getReg();
789 if (Uses.count(MOReg))
790 // Physical register use would be clobbered.
792 if (!MO.isDead() && Defs.count(MOReg))
793 // May clobber a physical register def.
794 // FIXME: This may be too conservative. It's ok if the instruction
795 // is sunken completely below the use.
798 if (Defs.count(MOReg))
801 ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg)))
802 // Don't want to extend other live ranges and update kills.
804 if (MOReg == Reg && !MO.isKill())
805 // We can't schedule across a use of the register in question.
807 // Ensure that if this is register in question, its the kill we expect.
808 assert((MOReg != Reg || OtherMI == KillMI) &&
809 "Found multiple kills of a register in a basic block");
814 // Move debug info as well.
815 while (From != MBB->begin() && llvm::prior(From)->isDebugValue())
818 // Copies following MI may have been moved as well.
820 MBB->splice(KillPos, MBB, From, To);
821 DistanceMap.erase(DI);
823 // Update live variables
824 LV->removeVirtualRegisterKilled(Reg, KillMI);
825 LV->addVirtualRegisterKilled(Reg, MI);
827 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
831 /// isDefTooClose - Return true if the re-scheduling will put the given
832 /// instruction too close to the defs of its register dependencies.
833 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
835 MachineBasicBlock *MBB) {
836 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
837 DE = MRI->def_end(); DI != DE; ++DI) {
838 MachineInstr *DefMI = &*DI;
839 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
842 return true; // MI is defining something KillMI uses
843 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
844 if (DDI == DistanceMap.end())
845 return true; // Below MI
846 unsigned DefDist = DDI->second;
847 assert(Dist > DefDist && "Visited def already?");
848 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
854 /// RescheduleKillAboveMI - If there is one more local instruction that reads
855 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
856 /// current two-address instruction in order to eliminate the need for the
859 TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB,
860 MachineBasicBlock::iterator &mi,
861 MachineBasicBlock::iterator &nmi,
863 // Bail immediately if we don't have LV available. We use it to find kills
868 MachineInstr *MI = &*mi;
869 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
870 if (DI == DistanceMap.end())
871 // Must be created from unfolded load. Don't waste time trying this.
874 MachineInstr *KillMI = LV->getVarInfo(Reg).findKill(MBB);
875 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
876 // Don't mess with copies, they may be coalesced later.
880 if (isTwoAddrUse(*KillMI, Reg, DstReg))
883 bool SeenStore = true;
884 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
887 SmallSet<unsigned, 2> Uses;
888 SmallSet<unsigned, 2> Kills;
889 SmallSet<unsigned, 2> Defs;
890 SmallSet<unsigned, 2> LiveDefs;
891 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
892 const MachineOperand &MO = KillMI->getOperand(i);
895 unsigned MOReg = MO.getReg();
899 if (isDefTooClose(MOReg, DI->second, MI, MBB))
901 if (MOReg == Reg && !MO.isKill())
904 if (MO.isKill() && MOReg != Reg)
906 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
909 LiveDefs.insert(MOReg);
913 // Check if the reschedule will not break depedencies.
914 unsigned NumVisited = 0;
915 MachineBasicBlock::iterator KillPos = KillMI;
916 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
917 MachineInstr *OtherMI = I;
918 // DBG_VALUE cannot be counted against the limit.
919 if (OtherMI->isDebugValue())
921 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
924 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
925 OtherMI->isBranch() || OtherMI->isTerminator())
926 // Don't move pass calls, etc.
928 SmallVector<unsigned, 2> OtherDefs;
929 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
930 const MachineOperand &MO = OtherMI->getOperand(i);
933 unsigned MOReg = MO.getReg();
937 if (Defs.count(MOReg))
938 // Moving KillMI can clobber the physical register if the def has
941 if (Kills.count(MOReg))
942 // Don't want to extend other live ranges and update kills.
944 if (OtherMI != MI && MOReg == Reg && !MO.isKill())
945 // We can't schedule across a use of the register in question.
948 OtherDefs.push_back(MOReg);
952 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
953 unsigned MOReg = OtherDefs[i];
954 if (Uses.count(MOReg))
956 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
957 LiveDefs.count(MOReg))
959 // Physical register def is seen.
964 // Move the old kill above MI, don't forget to move debug info as well.
965 MachineBasicBlock::iterator InsertPos = mi;
966 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
968 MachineBasicBlock::iterator From = KillMI;
969 MachineBasicBlock::iterator To = llvm::next(From);
970 while (llvm::prior(From)->isDebugValue())
972 MBB->splice(InsertPos, MBB, From, To);
974 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
975 DistanceMap.erase(DI);
977 // Update live variables
978 LV->removeVirtualRegisterKilled(Reg, KillMI);
979 LV->addVirtualRegisterKilled(Reg, MI);
981 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
985 /// TryInstructionTransform - For the case where an instruction has a single
986 /// pair of tied register operands, attempt some transformations that may
987 /// either eliminate the tied operands or improve the opportunities for
988 /// coalescing away the register copy. Returns true if no copy needs to be
989 /// inserted to untie mi's operands (either because they were untied, or
990 /// because mi was rescheduled, and will be visited again later).
991 bool TwoAddressInstructionPass::
992 TryInstructionTransform(MachineBasicBlock::iterator &mi,
993 MachineBasicBlock::iterator &nmi,
994 MachineFunction::iterator &mbbi,
995 unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
996 SmallPtrSet<MachineInstr*, 8> &Processed) {
997 if (OptLevel == CodeGenOpt::None)
1000 MachineInstr &MI = *mi;
1001 unsigned regA = MI.getOperand(DstIdx).getReg();
1002 unsigned regB = MI.getOperand(SrcIdx).getReg();
1004 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1005 "cannot make instruction into two-address form");
1006 bool regBKilled = isKilled(MI, regB, MRI, TII);
1008 if (TargetRegisterInfo::isVirtualRegister(regA))
1009 ScanUses(regA, &*mbbi, Processed);
1011 // Check if it is profitable to commute the operands.
1012 unsigned SrcOp1, SrcOp2;
1014 unsigned regCIdx = ~0U;
1015 bool TryCommute = false;
1016 bool AggressiveCommute = false;
1017 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1018 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1019 if (SrcIdx == SrcOp1)
1021 else if (SrcIdx == SrcOp2)
1024 if (regCIdx != ~0U) {
1025 regC = MI.getOperand(regCIdx).getReg();
1026 if (!regBKilled && isKilled(MI, regC, MRI, TII))
1027 // If C dies but B does not, swap the B and C operands.
1028 // This makes the live ranges of A and C joinable.
1030 else if (isProfitableToCommute(regA, regB, regC, &MI, mbbi, Dist)) {
1032 AggressiveCommute = true;
1037 // If it's profitable to commute, try to do so.
1038 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
1040 if (AggressiveCommute)
1045 // If there is one more use of regB later in the same MBB, consider
1046 // re-schedule this MI below it.
1047 if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
1052 if (MI.isConvertibleTo3Addr()) {
1053 // This instruction is potentially convertible to a true
1054 // three-address instruction. Check if it is profitable.
1055 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1056 // Try to convert it.
1057 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) {
1058 ++NumConvertedTo3Addr;
1059 return true; // Done with this instruction.
1064 // If there is one more use of regB later in the same MBB, consider
1065 // re-schedule it before this MI if it's legal.
1066 if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
1071 // If this is an instruction with a load folded into it, try unfolding
1072 // the load, e.g. avoid this:
1074 // addq (%rax), %rcx
1075 // in favor of this:
1076 // movq (%rax), %rcx
1078 // because it's preferable to schedule a load than a register copy.
1079 if (MI.mayLoad() && !regBKilled) {
1080 // Determine if a load can be unfolded.
1081 unsigned LoadRegIndex;
1083 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1084 /*UnfoldLoad=*/true,
1085 /*UnfoldStore=*/false,
1088 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1089 if (UnfoldMCID.getNumDefs() == 1) {
1090 MachineFunction &MF = *mbbi->getParent();
1093 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1094 const TargetRegisterClass *RC =
1095 TRI->getAllocatableClass(
1096 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, MF));
1097 unsigned Reg = MRI->createVirtualRegister(RC);
1098 SmallVector<MachineInstr *, 2> NewMIs;
1099 if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
1100 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1102 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1105 assert(NewMIs.size() == 2 &&
1106 "Unfolded a load into multiple instructions!");
1107 // The load was previously folded, so this is the only use.
1108 NewMIs[1]->addRegisterKilled(Reg, TRI);
1110 // Tentatively insert the instructions into the block so that they
1111 // look "normal" to the transformation logic.
1112 mbbi->insert(mi, NewMIs[0]);
1113 mbbi->insert(mi, NewMIs[1]);
1115 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1116 << "2addr: NEW INST: " << *NewMIs[1]);
1118 // Transform the instruction, now that it no longer has a load.
1119 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1120 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1121 MachineBasicBlock::iterator NewMI = NewMIs[1];
1122 bool TransformSuccess =
1123 TryInstructionTransform(NewMI, mi, mbbi,
1124 NewSrcIdx, NewDstIdx, Dist, Processed);
1125 if (TransformSuccess ||
1126 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1127 // Success, or at least we made an improvement. Keep the unfolded
1128 // instructions and discard the original.
1130 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1131 MachineOperand &MO = MI.getOperand(i);
1133 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1136 if (NewMIs[0]->killsRegister(MO.getReg()))
1137 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1139 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1140 "Kill missing after load unfold!");
1141 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1144 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1145 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1146 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1148 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1149 "Dead flag missing after load unfold!");
1150 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1155 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1157 MI.eraseFromParent();
1159 if (TransformSuccess)
1162 // Transforming didn't eliminate the tie and didn't lead to an
1163 // improvement. Clean up the unfolded instructions and keep the
1165 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1166 NewMIs[0]->eraseFromParent();
1167 NewMIs[1]->eraseFromParent();
1176 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1178 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
1179 const TargetMachine &TM = MF.getTarget();
1180 MRI = &MF.getRegInfo();
1181 TII = TM.getInstrInfo();
1182 TRI = TM.getRegisterInfo();
1183 InstrItins = TM.getInstrItineraryData();
1184 LV = getAnalysisIfAvailable<LiveVariables>();
1185 AA = &getAnalysis<AliasAnalysis>();
1186 OptLevel = TM.getOptLevel();
1188 bool MadeChange = false;
1190 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1191 DEBUG(dbgs() << "********** Function: "
1192 << MF.getFunction()->getName() << '\n');
1194 // This pass takes the function out of SSA form.
1197 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
1198 BitVector ReMatRegs(MRI->getNumVirtRegs());
1200 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
1202 TiedOperandMap TiedOperands(4);
1204 SmallPtrSet<MachineInstr*, 8> Processed;
1205 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
1206 mbbi != mbbe; ++mbbi) {
1208 DistanceMap.clear();
1212 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
1214 MachineBasicBlock::iterator nmi = llvm::next(mi);
1215 if (mi->isDebugValue()) {
1220 // Remember REG_SEQUENCE instructions, we'll deal with them later.
1221 if (mi->isRegSequence())
1222 RegSequences.push_back(&*mi);
1224 const MCInstrDesc &MCID = mi->getDesc();
1225 bool FirstTied = true;
1227 DistanceMap.insert(std::make_pair(mi, ++Dist));
1229 ProcessCopy(&*mi, &*mbbi, Processed);
1231 // First scan through all the tied register uses in this instruction
1232 // and record a list of pairs of tied operands for each register.
1233 unsigned NumOps = mi->isInlineAsm()
1234 ? mi->getNumOperands() : MCID.getNumOperands();
1235 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1236 unsigned DstIdx = 0;
1237 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1242 ++NumTwoAddressInstrs;
1243 DEBUG(dbgs() << '\t' << *mi);
1246 assert(mi->getOperand(SrcIdx).isReg() &&
1247 mi->getOperand(SrcIdx).getReg() &&
1248 mi->getOperand(SrcIdx).isUse() &&
1249 "two address instruction invalid");
1251 unsigned regB = mi->getOperand(SrcIdx).getReg();
1253 // Deal with <undef> uses immediately - simply rewrite the src operand.
1254 if (mi->getOperand(SrcIdx).isUndef()) {
1255 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1256 // Constrain the DstReg register class if required.
1257 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1258 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1260 MRI->constrainRegClass(DstReg, RC);
1261 mi->getOperand(SrcIdx).setReg(DstReg);
1262 DEBUG(dbgs() << "\t\trewrite undef:\t" << *mi);
1265 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx));
1268 // If the instruction has a single pair of tied operands, try some
1269 // transformations that may either eliminate the tied operands or
1270 // improve the opportunities for coalescing away the register copy.
1271 if (TiedOperands.size() == 1) {
1272 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs
1273 = TiedOperands.begin()->second;
1274 if (TiedPairs.size() == 1) {
1275 unsigned SrcIdx = TiedPairs[0].first;
1276 unsigned DstIdx = TiedPairs[0].second;
1277 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1278 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1279 if (SrcReg != DstReg &&
1280 TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist,
1282 // The tied operands have been eliminated or shifted further down the
1283 // block to ease elimination. Continue processing with 'nmi'.
1284 TiedOperands.clear();
1291 // Now iterate over the information collected above.
1292 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1293 OE = TiedOperands.end(); OI != OE; ++OI) {
1294 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
1296 bool IsEarlyClobber = false;
1297 bool RemovedKillFlag = false;
1298 bool AllUsesCopied = true;
1299 unsigned LastCopiedReg = 0;
1300 unsigned regB = OI->first;
1301 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1302 unsigned SrcIdx = TiedPairs[tpi].first;
1303 unsigned DstIdx = TiedPairs[tpi].second;
1305 const MachineOperand &DstMO = mi->getOperand(DstIdx);
1306 unsigned regA = DstMO.getReg();
1307 IsEarlyClobber |= DstMO.isEarlyClobber();
1309 // Grab regB from the instruction because it may have changed if the
1310 // instruction was commuted.
1311 regB = mi->getOperand(SrcIdx).getReg();
1314 // The register is tied to multiple destinations (or else we would
1315 // not have continued this far), but this use of the register
1316 // already matches the tied destination. Leave it.
1317 AllUsesCopied = false;
1320 LastCopiedReg = regA;
1322 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1323 "cannot make instruction into two-address form");
1326 // First, verify that we don't have a use of "a" in the instruction
1327 // (a = b + a for example) because our transformation will not
1328 // work. This should never occur because we are in SSA form.
1329 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1330 assert(i == DstIdx ||
1331 !mi->getOperand(i).isReg() ||
1332 mi->getOperand(i).getReg() != regA);
1336 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
1339 // Update DistanceMap.
1340 MachineBasicBlock::iterator prevMI = prior(mi);
1341 DistanceMap.insert(std::make_pair(prevMI, Dist));
1342 DistanceMap[mi] = ++Dist;
1344 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
1346 MachineOperand &MO = mi->getOperand(SrcIdx);
1347 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1348 "inconsistent operand info for 2-reg pass");
1350 MO.setIsKill(false);
1351 RemovedKillFlag = true;
1354 // Make sure regA is a legal regclass for the SrcIdx operand.
1355 if (TargetRegisterInfo::isVirtualRegister(regA) &&
1356 TargetRegisterInfo::isVirtualRegister(regB))
1357 MRI->constrainRegClass(regA, MRI->getRegClass(regB));
1361 // Propagate SrcRegMap.
1362 SrcRegMap[regA] = regB;
1365 if (AllUsesCopied) {
1366 if (!IsEarlyClobber) {
1367 // Replace other (un-tied) uses of regB with LastCopiedReg.
1368 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1369 MachineOperand &MO = mi->getOperand(i);
1370 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1372 MO.setIsKill(false);
1373 RemovedKillFlag = true;
1375 MO.setReg(LastCopiedReg);
1380 // Update live variables for regB.
1381 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1382 LV->addVirtualRegisterKilled(regB, prior(mi));
1384 } else if (RemovedKillFlag) {
1385 // Some tied uses of regB matched their destination registers, so
1386 // regB is still used in this instruction, but a kill flag was
1387 // removed from a different tied use of regB, so now we need to add
1388 // a kill flag to one of the remaining uses of regB.
1389 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1390 MachineOperand &MO = mi->getOperand(i);
1391 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1398 // We didn't change anything if there was a single tied pair, and that
1399 // pair didn't require copies.
1400 if (AllUsesCopied || TiedPairs.size() > 1) {
1403 // Schedule the source copy / remat inserted to form two-address
1404 // instruction. FIXME: Does it matter the distance map may not be
1405 // accurate after it's scheduled?
1406 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
1409 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1412 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1413 if (mi->isInsertSubreg()) {
1414 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1415 // To %reg:subidx = COPY %subreg
1416 unsigned SubIdx = mi->getOperand(3).getImm();
1417 mi->RemoveOperand(3);
1418 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1419 mi->getOperand(0).setSubReg(SubIdx);
1420 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1421 mi->RemoveOperand(1);
1422 mi->setDesc(TII->get(TargetOpcode::COPY));
1423 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1426 // Clear TiedOperands here instead of at the top of the loop
1427 // since most instructions do not have tied operands.
1428 TiedOperands.clear();
1433 // Some remat'ed instructions are dead.
1434 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
1435 unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
1436 if (MRI->use_nodbg_empty(VReg)) {
1437 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1438 DefMI->eraseFromParent();
1442 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1443 // SSA form. It's now safe to de-SSA.
1444 MadeChange |= EliminateRegSequences();
1449 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1450 unsigned DstReg, unsigned SubIdx,
1451 MachineRegisterInfo *MRI,
1452 const TargetRegisterInfo &TRI) {
1453 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1454 RE = MRI->reg_end(); RI != RE; ) {
1455 MachineOperand &MO = RI.getOperand();
1457 MO.substVirtReg(DstReg, SubIdx, TRI);
1461 // Find the first def of Reg, assuming they are all in the same basic block.
1462 static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) {
1463 SmallPtrSet<MachineInstr*, 8> Defs;
1464 MachineInstr *First = 0;
1465 for (MachineRegisterInfo::def_iterator RI = MRI->def_begin(Reg);
1466 MachineInstr *MI = RI.skipInstruction(); Defs.insert(MI))
1471 MachineBasicBlock *MBB = First->getParent();
1472 MachineBasicBlock::iterator A = First, B = First;
1476 if (A != MBB->begin()) {
1479 if (Defs.erase(A)) First = A;
1481 if (B != MBB->end()) {
1486 } while (Moving && !Defs.empty());
1487 assert(Defs.empty() && "Instructions outside basic block!");
1491 /// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
1492 /// EXTRACT_SUBREG from the same register and to the same virtual register
1493 /// with different sub-register indices, attempt to combine the
1494 /// EXTRACT_SUBREGs and pre-coalesce them. e.g.
1495 /// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
1496 /// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
1497 /// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
1498 /// Since D subregs 5, 6 can combine to a Q register, we can coalesce
1499 /// reg1026 to reg1029.
1501 TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
1503 SmallSet<unsigned, 4> Seen;
1504 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
1505 unsigned SrcReg = Srcs[i];
1506 if (!Seen.insert(SrcReg))
1509 // Check that the instructions are all in the same basic block.
1510 MachineInstr *SrcDefMI = MRI->getUniqueVRegDef(SrcReg);
1511 MachineInstr *DstDefMI = MRI->getUniqueVRegDef(DstReg);
1512 if (!SrcDefMI || !DstDefMI ||
1513 SrcDefMI->getParent() != DstDefMI->getParent())
1516 // If there are no other uses than copies which feed into
1517 // the reg_sequence, then we might be able to coalesce them.
1518 bool CanCoalesce = true;
1519 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
1520 for (MachineRegisterInfo::use_nodbg_iterator
1521 UI = MRI->use_nodbg_begin(SrcReg),
1522 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1523 MachineInstr *UseMI = &*UI;
1524 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
1525 CanCoalesce = false;
1528 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
1529 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
1532 if (!CanCoalesce || SrcSubIndices.size() < 2)
1535 // Check that the source subregisters can be combined.
1536 std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
1537 unsigned NewSrcSubIdx = 0;
1538 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
1542 // Check that the destination subregisters can also be combined.
1543 std::sort(DstSubIndices.begin(), DstSubIndices.end());
1544 unsigned NewDstSubIdx = 0;
1545 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
1549 // If neither source nor destination can be combined to the full register,
1550 // just give up. This could be improved if it ever matters.
1551 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
1554 // Now that we know that all the uses are extract_subregs and that those
1555 // subregs can somehow be combined, scan all the extract_subregs again to
1556 // make sure the subregs are in the right order and can be composed.
1557 MachineInstr *SomeMI = 0;
1559 for (MachineRegisterInfo::use_nodbg_iterator
1560 UI = MRI->use_nodbg_begin(SrcReg),
1561 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1562 MachineInstr *UseMI = &*UI;
1563 assert(UseMI->isCopy());
1564 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
1565 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
1566 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
1567 if ((NewDstSubIdx == 0 &&
1568 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
1569 (NewSrcSubIdx == 0 &&
1570 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
1571 CanCoalesce = false;
1574 // Keep track of one of the uses. Preferably the first one which has a
1575 // <def,undef> flag.
1576 if (!SomeMI || UseMI->getOperand(0).isUndef())
1582 // Insert a copy to replace the original.
1583 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
1584 SomeMI->getDebugLoc(),
1585 TII->get(TargetOpcode::COPY))
1586 .addReg(DstReg, RegState::Define |
1587 getUndefRegState(SomeMI->getOperand(0).isUndef()),
1589 .addReg(SrcReg, 0, NewSrcSubIdx);
1591 // Remove all the old extract instructions.
1592 for (MachineRegisterInfo::use_nodbg_iterator
1593 UI = MRI->use_nodbg_begin(SrcReg),
1594 UE = MRI->use_nodbg_end(); UI != UE; ) {
1595 MachineInstr *UseMI = &*UI;
1597 if (UseMI == CopyMI)
1599 assert(UseMI->isCopy());
1600 // Move any kills to the new copy or extract instruction.
1601 if (UseMI->getOperand(1).isKill()) {
1602 CopyMI->getOperand(1).setIsKill();
1604 // Update live variables
1605 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
1607 UseMI->eraseFromParent();
1612 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
1613 MachineRegisterInfo *MRI) {
1614 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
1615 UE = MRI->use_end(); UI != UE; ++UI) {
1616 MachineInstr *UseMI = &*UI;
1617 if (UseMI != RegSeq && UseMI->isRegSequence())
1623 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1624 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1625 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1627 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1628 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1630 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1631 bool TwoAddressInstructionPass::EliminateRegSequences() {
1632 if (RegSequences.empty())
1635 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1636 MachineInstr *MI = RegSequences[i];
1637 unsigned DstReg = MI->getOperand(0).getReg();
1638 if (MI->getOperand(0).getSubReg() ||
1639 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1640 !(MI->getNumOperands() & 1)) {
1641 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1642 llvm_unreachable(0);
1645 bool IsImpDef = true;
1646 SmallVector<unsigned, 4> RealSrcs;
1647 SmallSet<unsigned, 4> Seen;
1648 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1649 // Nothing needs to be inserted for <undef> operands.
1650 if (MI->getOperand(i).isUndef()) {
1651 MI->getOperand(i).setReg(0);
1654 unsigned SrcReg = MI->getOperand(i).getReg();
1655 unsigned SrcSubIdx = MI->getOperand(i).getSubReg();
1656 unsigned SubIdx = MI->getOperand(i+1).getImm();
1657 // DefMI of NULL means the value does not have a vreg in this block
1658 // i.e., its a physical register or a subreg.
1659 // In either case we force a copy to be generated.
1660 MachineInstr *DefMI = NULL;
1661 if (!MI->getOperand(i).getSubReg() &&
1662 !TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1663 DefMI = MRI->getUniqueVRegDef(SrcReg);
1666 if (DefMI && DefMI->isImplicitDef()) {
1667 DefMI->eraseFromParent();
1672 // Remember COPY sources. These might be candidate for coalescing.
1673 if (DefMI && DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
1674 RealSrcs.push_back(DefMI->getOperand(1).getReg());
1676 bool isKill = MI->getOperand(i).isKill();
1677 if (!DefMI || !Seen.insert(SrcReg) ||
1678 MI->getParent() != DefMI->getParent() ||
1679 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
1680 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
1681 MRI->getRegClass(SrcReg), SubIdx)) {
1682 // REG_SEQUENCE cannot have duplicated operands, add a copy.
1683 // Also add an copy if the source is live-in the block. We don't want
1684 // to end up with a partial-redef of a livein, e.g.
1686 // reg1051:10<def> =
1692 // LiveIntervalAnalysis won't like it.
1694 // If the REG_SEQUENCE doesn't kill its source, keeping live variables
1695 // correctly up to date becomes very difficult. Insert a copy.
1697 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1698 // might insert a COPY that uses SrcReg after is was killed.
1700 for (unsigned j = i + 2; j < e; j += 2)
1701 if (MI->getOperand(j).getReg() == SrcReg) {
1702 MI->getOperand(j).setIsKill();
1707 MachineBasicBlock::iterator InsertLoc = MI;
1708 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
1709 MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
1710 .addReg(DstReg, RegState::Define, SubIdx)
1711 .addReg(SrcReg, getKillRegState(isKill), SrcSubIdx);
1712 MI->getOperand(i).setReg(0);
1713 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1714 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1715 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1719 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1720 unsigned SrcReg = MI->getOperand(i).getReg();
1721 if (!SrcReg) continue;
1722 unsigned SubIdx = MI->getOperand(i+1).getImm();
1723 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1726 // Set <def,undef> flags on the first DstReg def in the basic block.
1727 // It marks the beginning of the live range. All the other defs are
1728 // read-modify-write.
1729 if (MachineInstr *Def = findFirstDef(DstReg, MRI)) {
1730 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
1731 MachineOperand &MO = Def->getOperand(i);
1732 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1735 // Make sure there is a full non-subreg imp-def operand on the
1736 // instruction. This shouldn't be necessary, but it seems that at least
1737 // RAFast requires it.
1738 Def->addRegisterDefined(DstReg, TRI);
1739 DEBUG(dbgs() << "First def: " << *Def);
1743 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1744 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1745 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1746 MI->RemoveOperand(j);
1748 DEBUG(dbgs() << "Eliminated: " << *MI);
1749 MI->eraseFromParent();
1752 // Try coalescing some EXTRACT_SUBREG instructions. This can create
1753 // INSERT_SUBREG instructions that must have <undef> flags added by
1754 // LiveIntervalAnalysis, so only run it when LiveVariables is available.
1756 CoalesceExtSubRegs(RealSrcs, DstReg);
1759 RegSequences.clear();