1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "Support/Debug.h"
41 #include "Support/Statistic.h"
42 #include "Support/STLExtras.h"
46 Statistic<> numTwoAddressInstrs("twoaddressinstruction",
47 "Number of two-address instructions");
48 Statistic<> numInstrsAdded("twoaddressinstruction",
49 "Number of instructions added");
51 struct TwoAddressInstructionPass : public MachineFunctionPass {
52 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
54 /// runOnMachineFunction - pass entry point
55 bool runOnMachineFunction(MachineFunction&);
58 RegisterPass<TwoAddressInstructionPass>
59 X("twoaddressinstruction", "Two-Address instruction pass");
62 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
64 void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
65 AU.addPreserved<LiveVariables>();
66 AU.addPreservedID(PHIEliminationID);
67 MachineFunctionPass::getAnalysisUsage(AU);
70 /// runOnMachineFunction - Reduce two-address instructions to two
73 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
74 DEBUG(std::cerr << "Machine Function\n");
75 const TargetMachine &TM = MF.getTarget();
76 const MRegisterInfo &MRI = *TM.getRegisterInfo();
77 const TargetInstrInfo &TII = *TM.getInstrInfo();
78 LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
80 bool MadeChange = false;
82 DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
83 DEBUG(std::cerr << "********** Function: "
84 << MF.getFunction()->getName() << '\n');
86 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
87 mbbi != mbbe; ++mbbi) {
88 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
90 unsigned opcode = mi->getOpcode();
92 // ignore if it is not a two-address instruction
93 if (!TII.isTwoAddrInstr(opcode))
96 ++numTwoAddressInstrs;
97 DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
98 assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
99 mi->getOperand(1).isUse() && "two address instruction invalid");
101 // if the two operands are the same we just remove the use
102 // and mark the def as def&use, otherwise we have to insert a copy.
103 if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
109 unsigned regA = mi->getOperand(0).getReg();
110 unsigned regB = mi->getOperand(1).getReg();
112 assert(MRegisterInfo::isVirtualRegister(regA) &&
113 MRegisterInfo::isVirtualRegister(regB) &&
114 "cannot update physical register live information");
116 // first make sure we do not have a use of a in the
117 // instruction (a = b + a for example) because our
118 // transformation will not work. This should never occur
119 // because we are in SSA form.
121 for (unsigned i = 1; i != mi->getNumOperands(); ++i)
122 assert(!mi->getOperand(i).isRegister() ||
123 mi->getOperand(i).getReg() != regA);
126 const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
127 unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
128 numInstrsAdded += Added;
130 MachineBasicBlock::iterator prevMi = prior(mi);
131 DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
134 // update live variables for regA
135 assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
136 LiveVariables::VarInfo& varInfo = LV->getVarInfo(regA);
137 varInfo.DefInst = prevMi;
139 // update live variables for regB
140 if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
141 LV->addVirtualRegisterKilled(regB, prevMi);
143 if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
144 LV->addVirtualRegisterDead(regB, prevMi);
147 // replace all occurences of regB with regA
148 for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
149 if (mi->getOperand(i).isRegister() &&
150 mi->getOperand(i).getReg() == regB)
151 mi->SetMachineOperandReg(i, regA);
155 assert(mi->getOperand(0).isDef());
156 mi->getOperand(0).setUse();
157 mi->RemoveOperand(1);
160 DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));