1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Analysis/AliasAnalysis.h"
38 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
39 #include "llvm/CodeGen/LiveVariables.h"
40 #include "llvm/CodeGen/MachineFunctionPass.h"
41 #include "llvm/CodeGen/MachineInstr.h"
42 #include "llvm/CodeGen/MachineInstrBuilder.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCInstrItineraries.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetMachine.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Target/TargetRegisterInfo.h"
54 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
55 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
56 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
57 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
58 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
59 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
60 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
63 class TwoAddressInstructionPass : public MachineFunctionPass {
65 const TargetInstrInfo *TII;
66 const TargetRegisterInfo *TRI;
67 const InstrItineraryData *InstrItins;
68 MachineRegisterInfo *MRI;
73 CodeGenOpt::Level OptLevel;
75 // The current basic block being processed.
76 MachineBasicBlock *MBB;
78 // DistanceMap - Keep track the distance of a MI from the start of the
79 // current basic block.
80 DenseMap<MachineInstr*, unsigned> DistanceMap;
82 // Set of already processed instructions in the current block.
83 SmallPtrSet<MachineInstr*, 8> Processed;
85 // SrcRegMap - A map from virtual registers to physical registers which are
86 // likely targets to be coalesced to due to copies from physical registers to
87 // virtual registers. e.g. v1024 = move r0.
88 DenseMap<unsigned, unsigned> SrcRegMap;
90 // DstRegMap - A map from virtual registers to physical registers which are
91 // likely targets to be coalesced to due to copies to physical registers from
92 // virtual registers. e.g. r1 = move v1024.
93 DenseMap<unsigned, unsigned> DstRegMap;
95 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
96 MachineBasicBlock::iterator OldPos);
98 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
100 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
101 MachineInstr *MI, unsigned Dist);
103 bool commuteInstruction(MachineBasicBlock::iterator &mi,
104 unsigned RegB, unsigned RegC, unsigned Dist);
106 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
108 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
109 MachineBasicBlock::iterator &nmi,
110 unsigned RegA, unsigned RegB, unsigned Dist);
112 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
114 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
115 MachineBasicBlock::iterator &nmi,
117 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
118 MachineBasicBlock::iterator &nmi,
121 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
122 MachineBasicBlock::iterator &nmi,
123 unsigned SrcIdx, unsigned DstIdx,
126 void scanUses(unsigned DstReg);
128 void processCopy(MachineInstr *MI);
130 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
131 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
132 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
133 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
134 void eliminateRegSequence(MachineBasicBlock::iterator&);
137 static char ID; // Pass identification, replacement for typeid
138 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
139 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
142 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
143 AU.setPreservesCFG();
144 AU.addRequired<AliasAnalysis>();
145 AU.addPreserved<LiveVariables>();
146 AU.addPreserved<SlotIndexes>();
147 AU.addPreserved<LiveIntervals>();
148 AU.addPreservedID(MachineLoopInfoID);
149 AU.addPreservedID(MachineDominatorsID);
150 MachineFunctionPass::getAnalysisUsage(AU);
153 /// runOnMachineFunction - Pass entry point.
154 bool runOnMachineFunction(MachineFunction&);
156 } // end anonymous namespace
158 char TwoAddressInstructionPass::ID = 0;
159 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
160 "Two-Address instruction pass", false, false)
161 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
162 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
163 "Two-Address instruction pass", false, false)
165 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
167 /// sink3AddrInstruction - A two-address instruction has been converted to a
168 /// three-address instruction to avoid clobbering a register. Try to sink it
169 /// past the instruction that would kill the above mentioned register to reduce
170 /// register pressure.
171 bool TwoAddressInstructionPass::
172 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
173 MachineBasicBlock::iterator OldPos) {
174 // FIXME: Shouldn't we be trying to do this before we three-addressify the
175 // instruction? After this transformation is done, we no longer need
176 // the instruction to be in three-address form.
178 // Check if it's safe to move this instruction.
179 bool SeenStore = true; // Be conservative.
180 if (!MI->isSafeToMove(TII, AA, SeenStore))
184 SmallSet<unsigned, 4> UseRegs;
186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
187 const MachineOperand &MO = MI->getOperand(i);
190 unsigned MOReg = MO.getReg();
193 if (MO.isUse() && MOReg != SavedReg)
194 UseRegs.insert(MO.getReg());
198 // Don't try to move it if it implicitly defines a register.
201 // For now, don't move any instructions that define multiple registers.
203 DefReg = MO.getReg();
206 // Find the instruction that kills SavedReg.
207 MachineInstr *KillMI = NULL;
208 for (MachineRegisterInfo::use_nodbg_iterator
209 UI = MRI->use_nodbg_begin(SavedReg),
210 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
211 MachineOperand &UseMO = UI.getOperand();
214 KillMI = UseMO.getParent();
218 // If we find the instruction that kills SavedReg, and it is in an
219 // appropriate location, we can try to sink the current instruction
221 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
222 KillMI == OldPos || KillMI->isTerminator())
225 // If any of the definitions are used by another instruction between the
226 // position and the kill use, then it's not safe to sink it.
228 // FIXME: This can be sped up if there is an easy way to query whether an
229 // instruction is before or after another instruction. Then we can use
230 // MachineRegisterInfo def / use instead.
231 MachineOperand *KillMO = NULL;
232 MachineBasicBlock::iterator KillPos = KillMI;
235 unsigned NumVisited = 0;
236 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
237 MachineInstr *OtherMI = I;
238 // DBG_VALUE cannot be counted against the limit.
239 if (OtherMI->isDebugValue())
241 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
244 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
245 MachineOperand &MO = OtherMI->getOperand(i);
248 unsigned MOReg = MO.getReg();
255 if (OtherMI == KillMI && MOReg == SavedReg)
256 // Save the operand that kills the register. We want to unset the kill
257 // marker if we can sink MI past it.
259 else if (UseRegs.count(MOReg))
260 // One of the uses is killed before the destination.
265 assert(KillMO && "Didn't find kill");
267 // Update kill and LV information.
268 KillMO->setIsKill(false);
269 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
270 KillMO->setIsKill(true);
273 LV->replaceKillInstruction(SavedReg, KillMI, MI);
275 // Move instruction to its destination.
277 MBB->insert(KillPos, MI);
286 /// noUseAfterLastDef - Return true if there are no intervening uses between the
287 /// last instruction in the MBB that defines the specified register and the
288 /// two-address instruction which is being processed. It also returns the last
289 /// def location by reference
290 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
293 unsigned LastUse = Dist;
294 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
295 E = MRI->reg_end(); I != E; ++I) {
296 MachineOperand &MO = I.getOperand();
297 MachineInstr *MI = MO.getParent();
298 if (MI->getParent() != MBB || MI->isDebugValue())
300 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
301 if (DI == DistanceMap.end())
303 if (MO.isUse() && DI->second < LastUse)
304 LastUse = DI->second;
305 if (MO.isDef() && DI->second > LastDef)
306 LastDef = DI->second;
309 return !(LastUse > LastDef && LastUse < Dist);
312 /// isCopyToReg - Return true if the specified MI is a copy instruction or
313 /// a extract_subreg instruction. It also returns the source and destination
314 /// registers and whether they are physical registers by reference.
315 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
316 unsigned &SrcReg, unsigned &DstReg,
317 bool &IsSrcPhys, bool &IsDstPhys) {
321 DstReg = MI.getOperand(0).getReg();
322 SrcReg = MI.getOperand(1).getReg();
323 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
324 DstReg = MI.getOperand(0).getReg();
325 SrcReg = MI.getOperand(2).getReg();
329 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
330 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
334 /// isKilled - Test if the given register value, which is used by the given
335 /// instruction, is killed by the given instruction. This looks through
336 /// coalescable copies to see if the original value is potentially not killed.
338 /// For example, in this code:
340 /// %reg1034 = copy %reg1024
341 /// %reg1035 = copy %reg1025<kill>
342 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
344 /// %reg1034 is not considered to be killed, since it is copied from a
345 /// register which is not killed. Treating it as not killed lets the
346 /// normal heuristics commute the (two-address) add, which lets
347 /// coalescing eliminate the extra copy.
349 static bool isKilled(MachineInstr &MI, unsigned Reg,
350 const MachineRegisterInfo *MRI,
351 const TargetInstrInfo *TII) {
352 MachineInstr *DefMI = &MI;
354 if (!DefMI->killsRegister(Reg))
356 if (TargetRegisterInfo::isPhysicalRegister(Reg))
358 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
359 // If there are multiple defs, we can't do a simple analysis, so just
360 // go with what the kill flag says.
361 if (llvm::next(Begin) != MRI->def_end())
364 bool IsSrcPhys, IsDstPhys;
365 unsigned SrcReg, DstReg;
366 // If the def is something other than a copy, then it isn't going to
367 // be coalesced, so follow the kill flag.
368 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
374 /// isTwoAddrUse - Return true if the specified MI uses the specified register
375 /// as a two-address use. If so, return the destination register by reference.
376 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
377 const MCInstrDesc &MCID = MI.getDesc();
378 unsigned NumOps = MI.isInlineAsm()
379 ? MI.getNumOperands() : MCID.getNumOperands();
380 for (unsigned i = 0; i != NumOps; ++i) {
381 const MachineOperand &MO = MI.getOperand(i);
382 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
385 if (MI.isRegTiedToDefOperand(i, &ti)) {
386 DstReg = MI.getOperand(ti).getReg();
393 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
394 /// use, return the use instruction if it's a copy or a two-address use.
396 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
397 MachineRegisterInfo *MRI,
398 const TargetInstrInfo *TII,
400 unsigned &DstReg, bool &IsDstPhys) {
401 if (!MRI->hasOneNonDBGUse(Reg))
402 // None or more than one use.
404 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
405 if (UseMI.getParent() != MBB)
409 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
414 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
415 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
421 /// getMappedReg - Return the physical register the specified virtual register
422 /// might be mapped to.
424 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
425 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
426 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
427 if (SI == RegMap.end())
431 if (TargetRegisterInfo::isPhysicalRegister(Reg))
436 /// regsAreCompatible - Return true if the two registers are equal or aliased.
439 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
444 return TRI->regsOverlap(RegA, RegB);
448 /// isProfitableToCommute - Return true if it's potentially profitable to commute
449 /// the two-address instruction that's being processed.
451 TwoAddressInstructionPass::
452 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
453 MachineInstr *MI, unsigned Dist) {
454 if (OptLevel == CodeGenOpt::None)
457 // Determine if it's profitable to commute this two address instruction. In
458 // general, we want no uses between this instruction and the definition of
459 // the two-address register.
461 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
462 // %reg1029<def> = MOV8rr %reg1028
463 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
464 // insert => %reg1030<def> = MOV8rr %reg1028
465 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
466 // In this case, it might not be possible to coalesce the second MOV8rr
467 // instruction if the first one is coalesced. So it would be profitable to
469 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
470 // %reg1029<def> = MOV8rr %reg1028
471 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
472 // insert => %reg1030<def> = MOV8rr %reg1029
473 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
475 if (!MI->killsRegister(regC))
478 // Ok, we have something like:
479 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
480 // let's see if it's worth commuting it.
482 // Look for situations like this:
483 // %reg1024<def> = MOV r1
484 // %reg1025<def> = MOV r0
485 // %reg1026<def> = ADD %reg1024, %reg1025
487 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
488 unsigned ToRegA = getMappedReg(regA, DstRegMap);
490 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
491 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
492 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
493 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
495 return !BComp && CComp;
498 // If there is a use of regC between its last def (could be livein) and this
499 // instruction, then bail.
500 unsigned LastDefC = 0;
501 if (!noUseAfterLastDef(regC, Dist, LastDefC))
504 // If there is a use of regB between its last def (could be livein) and this
505 // instruction, then go ahead and make this transformation.
506 unsigned LastDefB = 0;
507 if (!noUseAfterLastDef(regB, Dist, LastDefB))
510 // Since there are no intervening uses for both registers, then commute
511 // if the def of regC is closer. Its live interval is shorter.
512 return LastDefB && LastDefC && LastDefC > LastDefB;
515 /// commuteInstruction - Commute a two-address instruction and update the basic
516 /// block, distance map, and live variables if needed. Return true if it is
518 bool TwoAddressInstructionPass::
519 commuteInstruction(MachineBasicBlock::iterator &mi,
520 unsigned RegB, unsigned RegC, unsigned Dist) {
521 MachineInstr *MI = mi;
522 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
523 MachineInstr *NewMI = TII->commuteInstruction(MI);
526 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
530 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
531 // If the instruction changed to commute it, update livevar.
534 // Update live variables
535 LV->replaceKillInstruction(RegC, MI, NewMI);
537 Indexes->replaceMachineInstrInMaps(MI, NewMI);
539 MBB->insert(mi, NewMI); // Insert the new inst
540 MBB->erase(mi); // Nuke the old inst.
542 DistanceMap.insert(std::make_pair(NewMI, Dist));
545 // Update source register map.
546 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
548 unsigned RegA = MI->getOperand(0).getReg();
549 SrcRegMap[RegA] = FromRegC;
555 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
556 /// given 2-address instruction to a 3-address one.
558 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
559 // Look for situations like this:
560 // %reg1024<def> = MOV r1
561 // %reg1025<def> = MOV r0
562 // %reg1026<def> = ADD %reg1024, %reg1025
564 // Turn ADD into a 3-address instruction to avoid a copy.
565 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
568 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
569 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
572 /// convertInstTo3Addr - Convert the specified two-address instruction into a
573 /// three address one. Return true if this transformation was successful.
575 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
576 MachineBasicBlock::iterator &nmi,
577 unsigned RegA, unsigned RegB,
579 // FIXME: Why does convertToThreeAddress() need an iterator reference?
580 MachineFunction::iterator MFI = MBB;
581 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
582 assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
586 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
587 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
591 Indexes->replaceMachineInstrInMaps(mi, NewMI);
593 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
594 // FIXME: Temporary workaround. If the new instruction doesn't
595 // uses RegB, convertToThreeAddress must have created more
596 // then one instruction.
597 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
599 MBB->erase(mi); // Nuke the old inst.
602 DistanceMap.insert(std::make_pair(NewMI, Dist));
604 nmi = llvm::next(mi);
607 // Update source and destination register maps.
608 SrcRegMap.erase(RegA);
609 DstRegMap.erase(RegB);
613 /// scanUses - Scan forward recursively for only uses, update maps if the use
614 /// is a copy or a two-address instruction.
616 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
617 SmallVector<unsigned, 4> VirtRegPairs;
621 unsigned Reg = DstReg;
622 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
623 NewReg, IsDstPhys)) {
624 if (IsCopy && !Processed.insert(UseMI))
627 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
628 if (DI != DistanceMap.end())
629 // Earlier in the same MBB.Reached via a back edge.
633 VirtRegPairs.push_back(NewReg);
636 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
638 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
639 VirtRegPairs.push_back(NewReg);
643 if (!VirtRegPairs.empty()) {
644 unsigned ToReg = VirtRegPairs.back();
645 VirtRegPairs.pop_back();
646 while (!VirtRegPairs.empty()) {
647 unsigned FromReg = VirtRegPairs.back();
648 VirtRegPairs.pop_back();
649 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
651 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
654 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
656 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
660 /// processCopy - If the specified instruction is not yet processed, process it
661 /// if it's a copy. For a copy instruction, we find the physical registers the
662 /// source and destination registers might be mapped to. These are kept in
663 /// point-to maps used to determine future optimizations. e.g.
666 /// v1026 = add v1024, v1025
668 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
669 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
670 /// potentially joined with r1 on the output side. It's worthwhile to commute
671 /// 'add' to eliminate a copy.
672 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
673 if (Processed.count(MI))
676 bool IsSrcPhys, IsDstPhys;
677 unsigned SrcReg, DstReg;
678 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
681 if (IsDstPhys && !IsSrcPhys)
682 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
683 else if (!IsDstPhys && IsSrcPhys) {
684 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
686 assert(SrcRegMap[DstReg] == SrcReg &&
687 "Can't map to two src physical registers!");
692 Processed.insert(MI);
696 /// rescheduleMIBelowKill - If there is one more local instruction that reads
697 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
698 /// instruction in order to eliminate the need for the copy.
699 bool TwoAddressInstructionPass::
700 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
701 MachineBasicBlock::iterator &nmi,
703 // Bail immediately if we don't have LV available. We use it to find kills
708 MachineInstr *MI = &*mi;
709 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
710 if (DI == DistanceMap.end())
711 // Must be created from unfolded load. Don't waste time trying this.
714 MachineInstr *KillMI = LV->getVarInfo(Reg).findKill(MBB);
715 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
716 // Don't mess with copies, they may be coalesced later.
719 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
720 KillMI->isBranch() || KillMI->isTerminator())
721 // Don't move pass calls, etc.
725 if (isTwoAddrUse(*KillMI, Reg, DstReg))
728 bool SeenStore = true;
729 if (!MI->isSafeToMove(TII, AA, SeenStore))
732 if (TII->getInstrLatency(InstrItins, MI) > 1)
733 // FIXME: Needs more sophisticated heuristics.
736 SmallSet<unsigned, 2> Uses;
737 SmallSet<unsigned, 2> Kills;
738 SmallSet<unsigned, 2> Defs;
739 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
740 const MachineOperand &MO = MI->getOperand(i);
743 unsigned MOReg = MO.getReg();
750 if (MO.isKill() && MOReg != Reg)
755 // Move the copies connected to MI down as well.
756 MachineBasicBlock::iterator From = MI;
757 MachineBasicBlock::iterator To = llvm::next(From);
758 while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) {
759 Defs.insert(To->getOperand(0).getReg());
763 // Check if the reschedule will not break depedencies.
764 unsigned NumVisited = 0;
765 MachineBasicBlock::iterator KillPos = KillMI;
767 for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) {
768 MachineInstr *OtherMI = I;
769 // DBG_VALUE cannot be counted against the limit.
770 if (OtherMI->isDebugValue())
772 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
775 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
776 OtherMI->isBranch() || OtherMI->isTerminator())
777 // Don't move pass calls, etc.
779 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
780 const MachineOperand &MO = OtherMI->getOperand(i);
783 unsigned MOReg = MO.getReg();
787 if (Uses.count(MOReg))
788 // Physical register use would be clobbered.
790 if (!MO.isDead() && Defs.count(MOReg))
791 // May clobber a physical register def.
792 // FIXME: This may be too conservative. It's ok if the instruction
793 // is sunken completely below the use.
796 if (Defs.count(MOReg))
799 ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg)))
800 // Don't want to extend other live ranges and update kills.
802 if (MOReg == Reg && !MO.isKill())
803 // We can't schedule across a use of the register in question.
805 // Ensure that if this is register in question, its the kill we expect.
806 assert((MOReg != Reg || OtherMI == KillMI) &&
807 "Found multiple kills of a register in a basic block");
812 // Move debug info as well.
813 while (From != MBB->begin() && llvm::prior(From)->isDebugValue())
816 // Copies following MI may have been moved as well.
818 MBB->splice(KillPos, MBB, From, To);
819 DistanceMap.erase(DI);
821 // Update live variables
822 LV->removeVirtualRegisterKilled(Reg, KillMI);
823 LV->addVirtualRegisterKilled(Reg, MI);
827 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
831 /// isDefTooClose - Return true if the re-scheduling will put the given
832 /// instruction too close to the defs of its register dependencies.
833 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
835 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
836 DE = MRI->def_end(); DI != DE; ++DI) {
837 MachineInstr *DefMI = &*DI;
838 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
841 return true; // MI is defining something KillMI uses
842 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
843 if (DDI == DistanceMap.end())
844 return true; // Below MI
845 unsigned DefDist = DDI->second;
846 assert(Dist > DefDist && "Visited def already?");
847 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
853 /// rescheduleKillAboveMI - If there is one more local instruction that reads
854 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
855 /// current two-address instruction in order to eliminate the need for the
857 bool TwoAddressInstructionPass::
858 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
859 MachineBasicBlock::iterator &nmi,
861 // Bail immediately if we don't have LV available. We use it to find kills
866 MachineInstr *MI = &*mi;
867 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
868 if (DI == DistanceMap.end())
869 // Must be created from unfolded load. Don't waste time trying this.
872 MachineInstr *KillMI = LV->getVarInfo(Reg).findKill(MBB);
873 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
874 // Don't mess with copies, they may be coalesced later.
878 if (isTwoAddrUse(*KillMI, Reg, DstReg))
881 bool SeenStore = true;
882 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
885 SmallSet<unsigned, 2> Uses;
886 SmallSet<unsigned, 2> Kills;
887 SmallSet<unsigned, 2> Defs;
888 SmallSet<unsigned, 2> LiveDefs;
889 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
890 const MachineOperand &MO = KillMI->getOperand(i);
893 unsigned MOReg = MO.getReg();
897 if (isDefTooClose(MOReg, DI->second, MI))
899 if (MOReg == Reg && !MO.isKill())
902 if (MO.isKill() && MOReg != Reg)
904 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
907 LiveDefs.insert(MOReg);
911 // Check if the reschedule will not break depedencies.
912 unsigned NumVisited = 0;
913 MachineBasicBlock::iterator KillPos = KillMI;
914 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
915 MachineInstr *OtherMI = I;
916 // DBG_VALUE cannot be counted against the limit.
917 if (OtherMI->isDebugValue())
919 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
922 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
923 OtherMI->isBranch() || OtherMI->isTerminator())
924 // Don't move pass calls, etc.
926 SmallVector<unsigned, 2> OtherDefs;
927 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
928 const MachineOperand &MO = OtherMI->getOperand(i);
931 unsigned MOReg = MO.getReg();
935 if (Defs.count(MOReg))
936 // Moving KillMI can clobber the physical register if the def has
939 if (Kills.count(MOReg))
940 // Don't want to extend other live ranges and update kills.
942 if (OtherMI != MI && MOReg == Reg && !MO.isKill())
943 // We can't schedule across a use of the register in question.
946 OtherDefs.push_back(MOReg);
950 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
951 unsigned MOReg = OtherDefs[i];
952 if (Uses.count(MOReg))
954 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
955 LiveDefs.count(MOReg))
957 // Physical register def is seen.
962 // Move the old kill above MI, don't forget to move debug info as well.
963 MachineBasicBlock::iterator InsertPos = mi;
964 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
966 MachineBasicBlock::iterator From = KillMI;
967 MachineBasicBlock::iterator To = llvm::next(From);
968 while (llvm::prior(From)->isDebugValue())
970 MBB->splice(InsertPos, MBB, From, To);
972 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
973 DistanceMap.erase(DI);
975 // Update live variables
976 LV->removeVirtualRegisterKilled(Reg, KillMI);
977 LV->addVirtualRegisterKilled(Reg, MI);
979 LIS->handleMove(KillMI);
981 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
985 /// tryInstructionTransform - For the case where an instruction has a single
986 /// pair of tied register operands, attempt some transformations that may
987 /// either eliminate the tied operands or improve the opportunities for
988 /// coalescing away the register copy. Returns true if no copy needs to be
989 /// inserted to untie mi's operands (either because they were untied, or
990 /// because mi was rescheduled, and will be visited again later).
991 bool TwoAddressInstructionPass::
992 tryInstructionTransform(MachineBasicBlock::iterator &mi,
993 MachineBasicBlock::iterator &nmi,
994 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
995 if (OptLevel == CodeGenOpt::None)
998 MachineInstr &MI = *mi;
999 unsigned regA = MI.getOperand(DstIdx).getReg();
1000 unsigned regB = MI.getOperand(SrcIdx).getReg();
1002 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1003 "cannot make instruction into two-address form");
1004 bool regBKilled = isKilled(MI, regB, MRI, TII);
1006 if (TargetRegisterInfo::isVirtualRegister(regA))
1009 // Check if it is profitable to commute the operands.
1010 unsigned SrcOp1, SrcOp2;
1012 unsigned regCIdx = ~0U;
1013 bool TryCommute = false;
1014 bool AggressiveCommute = false;
1015 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1016 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1017 if (SrcIdx == SrcOp1)
1019 else if (SrcIdx == SrcOp2)
1022 if (regCIdx != ~0U) {
1023 regC = MI.getOperand(regCIdx).getReg();
1024 if (!regBKilled && isKilled(MI, regC, MRI, TII))
1025 // If C dies but B does not, swap the B and C operands.
1026 // This makes the live ranges of A and C joinable.
1028 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1030 AggressiveCommute = true;
1035 // If it's profitable to commute, try to do so.
1036 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1038 if (AggressiveCommute)
1043 // If there is one more use of regB later in the same MBB, consider
1044 // re-schedule this MI below it.
1045 if (rescheduleMIBelowKill(mi, nmi, regB)) {
1050 if (MI.isConvertibleTo3Addr()) {
1051 // This instruction is potentially convertible to a true
1052 // three-address instruction. Check if it is profitable.
1053 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1054 // Try to convert it.
1055 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1056 ++NumConvertedTo3Addr;
1057 return true; // Done with this instruction.
1062 // If there is one more use of regB later in the same MBB, consider
1063 // re-schedule it before this MI if it's legal.
1064 if (rescheduleKillAboveMI(mi, nmi, regB)) {
1069 // If this is an instruction with a load folded into it, try unfolding
1070 // the load, e.g. avoid this:
1072 // addq (%rax), %rcx
1073 // in favor of this:
1074 // movq (%rax), %rcx
1076 // because it's preferable to schedule a load than a register copy.
1077 if (MI.mayLoad() && !regBKilled) {
1078 // Determine if a load can be unfolded.
1079 unsigned LoadRegIndex;
1081 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1082 /*UnfoldLoad=*/true,
1083 /*UnfoldStore=*/false,
1086 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1087 if (UnfoldMCID.getNumDefs() == 1) {
1089 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1090 const TargetRegisterClass *RC =
1091 TRI->getAllocatableClass(
1092 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1093 unsigned Reg = MRI->createVirtualRegister(RC);
1094 SmallVector<MachineInstr *, 2> NewMIs;
1095 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1096 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1098 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1101 assert(NewMIs.size() == 2 &&
1102 "Unfolded a load into multiple instructions!");
1103 // The load was previously folded, so this is the only use.
1104 NewMIs[1]->addRegisterKilled(Reg, TRI);
1106 // Tentatively insert the instructions into the block so that they
1107 // look "normal" to the transformation logic.
1108 MBB->insert(mi, NewMIs[0]);
1109 MBB->insert(mi, NewMIs[1]);
1111 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1112 << "2addr: NEW INST: " << *NewMIs[1]);
1114 // Transform the instruction, now that it no longer has a load.
1115 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1116 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1117 MachineBasicBlock::iterator NewMI = NewMIs[1];
1118 bool TransformSuccess =
1119 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist);
1120 if (TransformSuccess ||
1121 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1122 // Success, or at least we made an improvement. Keep the unfolded
1123 // instructions and discard the original.
1125 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1126 MachineOperand &MO = MI.getOperand(i);
1128 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1131 if (NewMIs[0]->killsRegister(MO.getReg()))
1132 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1134 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1135 "Kill missing after load unfold!");
1136 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1139 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1140 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1141 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1143 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1144 "Dead flag missing after load unfold!");
1145 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1150 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1152 MI.eraseFromParent();
1154 if (TransformSuccess)
1157 // Transforming didn't eliminate the tie and didn't lead to an
1158 // improvement. Clean up the unfolded instructions and keep the
1160 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1161 NewMIs[0]->eraseFromParent();
1162 NewMIs[1]->eraseFromParent();
1171 // Collect tied operands of MI that need to be handled.
1172 // Rewrite trivial cases immediately.
1173 // Return true if any tied operands where found, including the trivial ones.
1174 bool TwoAddressInstructionPass::
1175 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1176 const MCInstrDesc &MCID = MI->getDesc();
1177 bool AnyOps = false;
1178 unsigned NumOps = MI->getNumOperands();
1180 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1181 unsigned DstIdx = 0;
1182 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1185 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1186 MachineOperand &DstMO = MI->getOperand(DstIdx);
1187 unsigned SrcReg = SrcMO.getReg();
1188 unsigned DstReg = DstMO.getReg();
1189 // Tied constraint already satisfied?
1190 if (SrcReg == DstReg)
1193 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1195 // Deal with <undef> uses immediately - simply rewrite the src operand.
1196 if (SrcMO.isUndef()) {
1197 // Constrain the DstReg register class if required.
1198 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1199 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1201 MRI->constrainRegClass(DstReg, RC);
1202 SrcMO.setReg(DstReg);
1203 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1206 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1211 // Process a list of tied MI operands that all use the same source register.
1212 // The tied pairs are of the form (SrcIdx, DstIdx).
1214 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1215 TiedPairList &TiedPairs,
1217 bool IsEarlyClobber = false;
1218 bool RemovedKillFlag = false;
1219 bool AllUsesCopied = true;
1220 unsigned LastCopiedReg = 0;
1222 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1223 unsigned SrcIdx = TiedPairs[tpi].first;
1224 unsigned DstIdx = TiedPairs[tpi].second;
1226 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1227 unsigned RegA = DstMO.getReg();
1228 IsEarlyClobber |= DstMO.isEarlyClobber();
1230 // Grab RegB from the instruction because it may have changed if the
1231 // instruction was commuted.
1232 RegB = MI->getOperand(SrcIdx).getReg();
1235 // The register is tied to multiple destinations (or else we would
1236 // not have continued this far), but this use of the register
1237 // already matches the tied destination. Leave it.
1238 AllUsesCopied = false;
1241 LastCopiedReg = RegA;
1243 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1244 "cannot make instruction into two-address form");
1247 // First, verify that we don't have a use of "a" in the instruction
1248 // (a = b + a for example) because our transformation will not
1249 // work. This should never occur because we are in SSA form.
1250 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1251 assert(i == DstIdx ||
1252 !MI->getOperand(i).isReg() ||
1253 MI->getOperand(i).getReg() != RegA);
1257 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1258 TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
1260 // Update DistanceMap.
1261 MachineBasicBlock::iterator PrevMI = MI;
1263 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1264 DistanceMap[MI] = ++Dist;
1268 CopyIdx = Indexes->insertMachineInstrInMaps(PrevMI).getRegSlot();
1270 DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
1272 MachineOperand &MO = MI->getOperand(SrcIdx);
1273 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1274 "inconsistent operand info for 2-reg pass");
1276 MO.setIsKill(false);
1277 RemovedKillFlag = true;
1280 // Make sure regA is a legal regclass for the SrcIdx operand.
1281 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1282 TargetRegisterInfo::isVirtualRegister(RegB))
1283 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
1287 // Propagate SrcRegMap.
1288 SrcRegMap[RegA] = RegB;
1292 if (AllUsesCopied) {
1293 if (!IsEarlyClobber) {
1294 // Replace other (un-tied) uses of regB with LastCopiedReg.
1295 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1296 MachineOperand &MO = MI->getOperand(i);
1297 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1299 MO.setIsKill(false);
1300 RemovedKillFlag = true;
1302 MO.setReg(LastCopiedReg);
1307 // Update live variables for regB.
1308 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1309 MachineBasicBlock::iterator PrevMI = MI;
1311 LV->addVirtualRegisterKilled(RegB, PrevMI);
1314 } else if (RemovedKillFlag) {
1315 // Some tied uses of regB matched their destination registers, so
1316 // regB is still used in this instruction, but a kill flag was
1317 // removed from a different tied use of regB, so now we need to add
1318 // a kill flag to one of the remaining uses of regB.
1319 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1320 MachineOperand &MO = MI->getOperand(i);
1321 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1329 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1331 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1333 const TargetMachine &TM = MF->getTarget();
1334 MRI = &MF->getRegInfo();
1335 TII = TM.getInstrInfo();
1336 TRI = TM.getRegisterInfo();
1337 InstrItins = TM.getInstrItineraryData();
1338 Indexes = getAnalysisIfAvailable<SlotIndexes>();
1339 LV = getAnalysisIfAvailable<LiveVariables>();
1340 LIS = getAnalysisIfAvailable<LiveIntervals>();
1341 AA = &getAnalysis<AliasAnalysis>();
1342 OptLevel = TM.getOptLevel();
1344 bool MadeChange = false;
1346 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1347 DEBUG(dbgs() << "********** Function: "
1348 << MF->getName() << '\n');
1350 // This pass takes the function out of SSA form.
1353 TiedOperandMap TiedOperands;
1354 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1355 MBBI != MBBE; ++MBBI) {
1358 DistanceMap.clear();
1362 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1364 MachineBasicBlock::iterator nmi = llvm::next(mi);
1365 if (mi->isDebugValue()) {
1370 // Expand REG_SEQUENCE instructions. This will position mi at the first
1371 // expanded instruction.
1372 if (mi->isRegSequence())
1373 eliminateRegSequence(mi);
1375 DistanceMap.insert(std::make_pair(mi, ++Dist));
1379 // First scan through all the tied register uses in this instruction
1380 // and record a list of pairs of tied operands for each register.
1381 if (!collectTiedOperands(mi, TiedOperands)) {
1386 ++NumTwoAddressInstrs;
1388 DEBUG(dbgs() << '\t' << *mi);
1390 // If the instruction has a single pair of tied operands, try some
1391 // transformations that may either eliminate the tied operands or
1392 // improve the opportunities for coalescing away the register copy.
1393 if (TiedOperands.size() == 1) {
1394 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs
1395 = TiedOperands.begin()->second;
1396 if (TiedPairs.size() == 1) {
1397 unsigned SrcIdx = TiedPairs[0].first;
1398 unsigned DstIdx = TiedPairs[0].second;
1399 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1400 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1401 if (SrcReg != DstReg &&
1402 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist)) {
1403 // The tied operands have been eliminated or shifted further down the
1404 // block to ease elimination. Continue processing with 'nmi'.
1405 TiedOperands.clear();
1412 // Now iterate over the information collected above.
1413 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1414 OE = TiedOperands.end(); OI != OE; ++OI) {
1415 processTiedPairs(mi, OI->second, Dist);
1416 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1419 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1420 if (mi->isInsertSubreg()) {
1421 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1422 // To %reg:subidx = COPY %subreg
1423 unsigned SubIdx = mi->getOperand(3).getImm();
1424 mi->RemoveOperand(3);
1425 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1426 mi->getOperand(0).setSubReg(SubIdx);
1427 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1428 mi->RemoveOperand(1);
1429 mi->setDesc(TII->get(TargetOpcode::COPY));
1430 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1433 // Clear TiedOperands here instead of at the top of the loop
1434 // since most instructions do not have tied operands.
1435 TiedOperands.clear();
1443 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1445 /// The instruction is turned into a sequence of sub-register copies:
1447 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1451 /// %dst:ssub0<def,undef> = COPY %v1
1452 /// %dst:ssub1<def> = COPY %v2
1454 void TwoAddressInstructionPass::
1455 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1456 MachineInstr *MI = MBBI;
1457 unsigned DstReg = MI->getOperand(0).getReg();
1458 if (MI->getOperand(0).getSubReg() ||
1459 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1460 !(MI->getNumOperands() & 1)) {
1461 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1462 llvm_unreachable(0);
1465 bool DefEmitted = false;
1466 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1467 MachineOperand &UseMO = MI->getOperand(i);
1468 unsigned SrcReg = UseMO.getReg();
1469 unsigned SubIdx = MI->getOperand(i+1).getImm();
1470 // Nothing needs to be inserted for <undef> operands.
1471 if (UseMO.isUndef())
1474 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1475 // might insert a COPY that uses SrcReg after is was killed.
1476 bool isKill = UseMO.isKill();
1478 for (unsigned j = i + 2; j < e; j += 2)
1479 if (MI->getOperand(j).getReg() == SrcReg) {
1480 MI->getOperand(j).setIsKill();
1481 UseMO.setIsKill(false);
1486 // Insert the sub-register copy.
1487 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1488 TII->get(TargetOpcode::COPY))
1489 .addReg(DstReg, RegState::Define, SubIdx)
1492 // The first def needs an <undef> flag because there is no live register
1495 CopyMI->getOperand(0).setIsUndef(true);
1496 // Return an iterator pointing to the first inserted instr.
1501 // Update LiveVariables' kill info.
1502 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1503 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1505 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1509 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1510 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1511 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1512 MI->RemoveOperand(j);
1514 DEBUG(dbgs() << "Eliminated: " << *MI);
1515 MI->eraseFromParent();