1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Analysis/AliasAnalysis.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/ADT/BitVector.h"
45 #include "llvm/ADT/DenseMap.h"
46 #include "llvm/ADT/SmallSet.h"
47 #include "llvm/ADT/Statistic.h"
48 #include "llvm/ADT/STLExtras.h"
51 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
52 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
53 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
54 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
55 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
56 STATISTIC(NumReMats, "Number of instructions re-materialized");
57 STATISTIC(NumDeletes, "Number of dead instructions deleted");
60 class VISIBILITY_HIDDEN TwoAddressInstructionPass
61 : public MachineFunctionPass {
62 const TargetInstrInfo *TII;
63 const TargetRegisterInfo *TRI;
64 MachineRegisterInfo *MRI;
68 // DistanceMap - Keep track the distance of a MI from the start of the
69 // current basic block.
70 DenseMap<MachineInstr*, unsigned> DistanceMap;
72 // SrcRegMap - A map from virtual registers to physical registers which
73 // are likely targets to be coalesced to due to copies from physical
74 // registers to virtual registers. e.g. v1024 = move r0.
75 DenseMap<unsigned, unsigned> SrcRegMap;
77 // DstRegMap - A map from virtual registers to physical registers which
78 // are likely targets to be coalesced to due to copies to physical
79 // registers from virtual registers. e.g. r1 = move v1024.
80 DenseMap<unsigned, unsigned> DstRegMap;
82 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
84 MachineBasicBlock::iterator OldPos);
86 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
87 MachineInstr *MI, MachineInstr *DefMI,
88 MachineBasicBlock *MBB, unsigned Loc);
90 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
93 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
96 bool isProfitableToCommute(unsigned regB, unsigned regC,
97 MachineInstr *MI, MachineBasicBlock *MBB,
100 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
101 MachineFunction::iterator &mbbi,
102 unsigned RegB, unsigned RegC, unsigned Dist);
104 bool isProfitableToConv3Addr(unsigned RegA);
106 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
107 MachineBasicBlock::iterator &nmi,
108 MachineFunction::iterator &mbbi,
109 unsigned RegB, unsigned Dist);
111 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
112 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
113 SmallVector<NewKill, 4> &NewKills,
114 MachineBasicBlock *MBB, unsigned Dist);
115 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
116 MachineBasicBlock::iterator &nmi,
117 MachineFunction::iterator &mbbi,
118 unsigned regB, unsigned regBIdx, unsigned Dist);
120 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
121 MachineBasicBlock::iterator &nmi,
122 MachineFunction::iterator &mbbi,
123 unsigned SrcIdx, unsigned DstIdx,
126 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
127 SmallPtrSet<MachineInstr*, 8> &Processed);
130 static char ID; // Pass identification, replacement for typeid
131 TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
133 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
134 AU.setPreservesCFG();
135 AU.addRequired<AliasAnalysis>();
136 AU.addPreserved<LiveVariables>();
137 AU.addPreservedID(MachineLoopInfoID);
138 AU.addPreservedID(MachineDominatorsID);
140 AU.addPreservedID(StrongPHIEliminationID);
142 AU.addPreservedID(PHIEliminationID);
143 MachineFunctionPass::getAnalysisUsage(AU);
146 /// runOnMachineFunction - Pass entry point.
147 bool runOnMachineFunction(MachineFunction&);
151 char TwoAddressInstructionPass::ID = 0;
152 static RegisterPass<TwoAddressInstructionPass>
153 X("twoaddressinstruction", "Two-Address instruction pass");
155 const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
157 /// Sink3AddrInstruction - A two-address instruction has been converted to a
158 /// three-address instruction to avoid clobbering a register. Try to sink it
159 /// past the instruction that would kill the above mentioned register to reduce
160 /// register pressure.
161 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
162 MachineInstr *MI, unsigned SavedReg,
163 MachineBasicBlock::iterator OldPos) {
164 // Check if it's safe to move this instruction.
165 bool SeenStore = true; // Be conservative.
166 if (!MI->isSafeToMove(TII, SeenStore, AA))
170 SmallSet<unsigned, 4> UseRegs;
172 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
173 const MachineOperand &MO = MI->getOperand(i);
176 unsigned MOReg = MO.getReg();
179 if (MO.isUse() && MOReg != SavedReg)
180 UseRegs.insert(MO.getReg());
184 // Don't try to move it if it implicitly defines a register.
187 // For now, don't move any instructions that define multiple registers.
189 DefReg = MO.getReg();
192 // Find the instruction that kills SavedReg.
193 MachineInstr *KillMI = NULL;
194 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
195 UE = MRI->use_end(); UI != UE; ++UI) {
196 MachineOperand &UseMO = UI.getOperand();
199 KillMI = UseMO.getParent();
203 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
206 // If any of the definitions are used by another instruction between the
207 // position and the kill use, then it's not safe to sink it.
209 // FIXME: This can be sped up if there is an easy way to query whether an
210 // instruction is before or after another instruction. Then we can use
211 // MachineRegisterInfo def / use instead.
212 MachineOperand *KillMO = NULL;
213 MachineBasicBlock::iterator KillPos = KillMI;
216 unsigned NumVisited = 0;
217 for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
218 MachineInstr *OtherMI = I;
219 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
222 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
223 MachineOperand &MO = OtherMI->getOperand(i);
226 unsigned MOReg = MO.getReg();
233 if (OtherMI == KillMI && MOReg == SavedReg)
234 // Save the operand that kills the register. We want to unset the kill
235 // marker if we can sink MI past it.
237 else if (UseRegs.count(MOReg))
238 // One of the uses is killed before the destination.
244 // Update kill and LV information.
245 KillMO->setIsKill(false);
246 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
247 KillMO->setIsKill(true);
250 LV->replaceKillInstruction(SavedReg, KillMI, MI);
252 // Move instruction to its destination.
254 MBB->insert(KillPos, MI);
260 /// isTwoAddrUse - Return true if the specified MI is using the specified
261 /// register as a two-address operand.
262 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
263 const TargetInstrDesc &TID = UseMI->getDesc();
264 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
265 MachineOperand &MO = UseMI->getOperand(i);
266 if (MO.isReg() && MO.getReg() == Reg &&
267 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
268 // Earlier use is a two-address one.
274 /// isProfitableToReMat - Return true if the heuristics determines it is likely
275 /// to be profitable to re-materialize the definition of Reg rather than copy
278 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
279 const TargetRegisterClass *RC,
280 MachineInstr *MI, MachineInstr *DefMI,
281 MachineBasicBlock *MBB, unsigned Loc) {
282 bool OtherUse = false;
283 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
284 UE = MRI->use_end(); UI != UE; ++UI) {
285 MachineOperand &UseMO = UI.getOperand();
286 MachineInstr *UseMI = UseMO.getParent();
287 MachineBasicBlock *UseMBB = UseMI->getParent();
289 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
290 if (DI != DistanceMap.end() && DI->second == Loc)
291 continue; // Current use.
293 // There is at least one other use in the MBB that will clobber the
295 if (isTwoAddrUse(UseMI, Reg))
300 // If other uses in MBB are not two-address uses, then don't remat.
304 // No other uses in the same block, remat if it's defined in the same
305 // block so it does not unnecessarily extend the live range.
306 return MBB == DefMI->getParent();
309 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
310 /// last instruction in the MBB that defines the specified register and the
311 /// two-address instruction which is being processed. It also returns the last
312 /// def location by reference
313 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
314 MachineBasicBlock *MBB, unsigned Dist,
317 unsigned LastUse = Dist;
318 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
319 E = MRI->reg_end(); I != E; ++I) {
320 MachineOperand &MO = I.getOperand();
321 MachineInstr *MI = MO.getParent();
322 if (MI->getParent() != MBB)
324 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
325 if (DI == DistanceMap.end())
327 if (MO.isUse() && DI->second < LastUse)
328 LastUse = DI->second;
329 if (MO.isDef() && DI->second > LastDef)
330 LastDef = DI->second;
333 return !(LastUse > LastDef && LastUse < Dist);
336 MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
337 MachineBasicBlock *MBB,
339 unsigned LastUseDist = 0;
340 MachineInstr *LastUse = 0;
341 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
342 E = MRI->reg_end(); I != E; ++I) {
343 MachineOperand &MO = I.getOperand();
344 MachineInstr *MI = MO.getParent();
345 if (MI->getParent() != MBB)
347 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
348 if (DI == DistanceMap.end())
350 if (DI->second >= Dist)
353 if (MO.isUse() && DI->second > LastUseDist) {
355 LastUseDist = DI->second;
361 /// isCopyToReg - Return true if the specified MI is a copy instruction or
362 /// a extract_subreg instruction. It also returns the source and destination
363 /// registers and whether they are physical registers by reference.
364 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
365 unsigned &SrcReg, unsigned &DstReg,
366 bool &IsSrcPhys, bool &IsDstPhys) {
369 unsigned SrcSubIdx, DstSubIdx;
370 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
371 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
372 DstReg = MI.getOperand(0).getReg();
373 SrcReg = MI.getOperand(1).getReg();
374 } else if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
375 DstReg = MI.getOperand(0).getReg();
376 SrcReg = MI.getOperand(2).getReg();
377 } else if (MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
378 DstReg = MI.getOperand(0).getReg();
379 SrcReg = MI.getOperand(2).getReg();
384 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
385 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
391 /// isKilled - Test if the given register value, which is used by the given
392 /// instruction, is killed by the given instruction. This looks through
393 /// coalescable copies to see if the original value is potentially not killed.
395 /// For example, in this code:
397 /// %reg1034 = copy %reg1024
398 /// %reg1035 = copy %reg1025<kill>
399 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
401 /// %reg1034 is not considered to be killed, since it is copied from a
402 /// register which is not killed. Treating it as not killed lets the
403 /// normal heuristics commute the (two-address) add, which lets
404 /// coalescing eliminate the extra copy.
406 static bool isKilled(MachineInstr &MI, unsigned Reg,
407 const MachineRegisterInfo *MRI,
408 const TargetInstrInfo *TII) {
409 MachineInstr *DefMI = &MI;
411 if (!DefMI->killsRegister(Reg))
413 if (TargetRegisterInfo::isPhysicalRegister(Reg))
415 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
416 // If there are multiple defs, we can't do a simple analysis, so just
417 // go with what the kill flag says.
418 if (next(Begin) != MRI->def_end())
421 bool IsSrcPhys, IsDstPhys;
422 unsigned SrcReg, DstReg;
423 // If the def is something other than a copy, then it isn't going to
424 // be coalesced, so follow the kill flag.
425 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
431 /// isTwoAddrUse - Return true if the specified MI uses the specified register
432 /// as a two-address use. If so, return the destination register by reference.
433 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
434 const TargetInstrDesc &TID = MI.getDesc();
435 unsigned NumOps = (MI.getOpcode() == TargetInstrInfo::INLINEASM)
436 ? MI.getNumOperands() : TID.getNumOperands();
437 for (unsigned i = 0; i != NumOps; ++i) {
438 const MachineOperand &MO = MI.getOperand(i);
439 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
442 if (MI.isRegTiedToDefOperand(i, &ti)) {
443 DstReg = MI.getOperand(ti).getReg();
450 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
451 /// use, return the use instruction if it's a copy or a two-address use.
453 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
454 MachineRegisterInfo *MRI,
455 const TargetInstrInfo *TII,
457 unsigned &DstReg, bool &IsDstPhys) {
458 MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg);
459 if (UI == MRI->use_end())
461 MachineInstr &UseMI = *UI;
462 if (++UI != MRI->use_end())
463 // More than one use.
465 if (UseMI.getParent() != MBB)
469 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
474 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
475 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
481 /// getMappedReg - Return the physical register the specified virtual register
482 /// might be mapped to.
484 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
485 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
486 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
487 if (SI == RegMap.end())
491 if (TargetRegisterInfo::isPhysicalRegister(Reg))
496 /// regsAreCompatible - Return true if the two registers are equal or aliased.
499 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
504 return TRI->regsOverlap(RegA, RegB);
508 /// isProfitableToReMat - Return true if it's potentially profitable to commute
509 /// the two-address instruction that's being processed.
511 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
512 MachineInstr *MI, MachineBasicBlock *MBB,
514 // Determine if it's profitable to commute this two address instruction. In
515 // general, we want no uses between this instruction and the definition of
516 // the two-address register.
518 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
519 // %reg1029<def> = MOV8rr %reg1028
520 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
521 // insert => %reg1030<def> = MOV8rr %reg1028
522 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
523 // In this case, it might not be possible to coalesce the second MOV8rr
524 // instruction if the first one is coalesced. So it would be profitable to
526 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
527 // %reg1029<def> = MOV8rr %reg1028
528 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
529 // insert => %reg1030<def> = MOV8rr %reg1029
530 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
532 if (!MI->killsRegister(regC))
535 // Ok, we have something like:
536 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
537 // let's see if it's worth commuting it.
539 // Look for situations like this:
540 // %reg1024<def> = MOV r1
541 // %reg1025<def> = MOV r0
542 // %reg1026<def> = ADD %reg1024, %reg1025
544 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
545 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
546 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
547 unsigned ToRegB = getMappedReg(regB, DstRegMap);
548 unsigned ToRegC = getMappedReg(regC, DstRegMap);
549 if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
550 (regsAreCompatible(FromRegB, ToRegC, TRI) ||
551 regsAreCompatible(FromRegC, ToRegB, TRI)))
554 // If there is a use of regC between its last def (could be livein) and this
555 // instruction, then bail.
556 unsigned LastDefC = 0;
557 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
560 // If there is a use of regB between its last def (could be livein) and this
561 // instruction, then go ahead and make this transformation.
562 unsigned LastDefB = 0;
563 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
566 // Since there are no intervening uses for both registers, then commute
567 // if the def of regC is closer. Its live interval is shorter.
568 return LastDefB && LastDefC && LastDefC > LastDefB;
571 /// CommuteInstruction - Commute a two-address instruction and update the basic
572 /// block, distance map, and live variables if needed. Return true if it is
575 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
576 MachineFunction::iterator &mbbi,
577 unsigned RegB, unsigned RegC, unsigned Dist) {
578 MachineInstr *MI = mi;
579 DEBUG(errs() << "2addr: COMMUTING : " << *MI);
580 MachineInstr *NewMI = TII->commuteInstruction(MI);
583 DEBUG(errs() << "2addr: COMMUTING FAILED!\n");
587 DEBUG(errs() << "2addr: COMMUTED TO: " << *NewMI);
588 // If the instruction changed to commute it, update livevar.
591 // Update live variables
592 LV->replaceKillInstruction(RegC, MI, NewMI);
594 mbbi->insert(mi, NewMI); // Insert the new inst
595 mbbi->erase(mi); // Nuke the old inst.
597 DistanceMap.insert(std::make_pair(NewMI, Dist));
600 // Update source register map.
601 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
603 unsigned RegA = MI->getOperand(0).getReg();
604 SrcRegMap[RegA] = FromRegC;
610 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
611 /// given 2-address instruction to a 3-address one.
613 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
614 // Look for situations like this:
615 // %reg1024<def> = MOV r1
616 // %reg1025<def> = MOV r0
617 // %reg1026<def> = ADD %reg1024, %reg1025
619 // Turn ADD into a 3-address instruction to avoid a copy.
620 unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
621 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
622 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
625 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
626 /// three address one. Return true if this transformation was successful.
628 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
629 MachineBasicBlock::iterator &nmi,
630 MachineFunction::iterator &mbbi,
631 unsigned RegB, unsigned Dist) {
632 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
634 DEBUG(errs() << "2addr: CONVERTING 2-ADDR: " << *mi);
635 DEBUG(errs() << "2addr: TO 3-ADDR: " << *NewMI);
638 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
639 // FIXME: Temporary workaround. If the new instruction doesn't
640 // uses RegB, convertToThreeAddress must have created more
641 // then one instruction.
642 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
644 mbbi->erase(mi); // Nuke the old inst.
647 DistanceMap.insert(std::make_pair(NewMI, Dist));
657 /// ProcessCopy - If the specified instruction is not yet processed, process it
658 /// if it's a copy. For a copy instruction, we find the physical registers the
659 /// source and destination registers might be mapped to. These are kept in
660 /// point-to maps used to determine future optimizations. e.g.
663 /// v1026 = add v1024, v1025
665 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
666 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
667 /// potentially joined with r1 on the output side. It's worthwhile to commute
668 /// 'add' to eliminate a copy.
669 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
670 MachineBasicBlock *MBB,
671 SmallPtrSet<MachineInstr*, 8> &Processed) {
672 if (Processed.count(MI))
675 bool IsSrcPhys, IsDstPhys;
676 unsigned SrcReg, DstReg;
677 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
680 if (IsDstPhys && !IsSrcPhys)
681 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
682 else if (!IsDstPhys && IsSrcPhys) {
683 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
685 assert(SrcRegMap[DstReg] == SrcReg &&
686 "Can't map to two src physical registers!");
688 SmallVector<unsigned, 4> VirtRegPairs;
691 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
692 IsCopy, NewReg, IsDstPhys)) {
694 if (!Processed.insert(UseMI))
698 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
699 if (DI != DistanceMap.end())
700 // Earlier in the same MBB.Reached via a back edge.
704 VirtRegPairs.push_back(NewReg);
707 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
709 assert(SrcRegMap[NewReg] == DstReg &&
710 "Can't map to two src physical registers!");
711 VirtRegPairs.push_back(NewReg);
715 if (!VirtRegPairs.empty()) {
716 unsigned ToReg = VirtRegPairs.back();
717 VirtRegPairs.pop_back();
718 while (!VirtRegPairs.empty()) {
719 unsigned FromReg = VirtRegPairs.back();
720 VirtRegPairs.pop_back();
721 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
723 assert(DstRegMap[FromReg] == ToReg &&
724 "Can't map to two dst physical registers!");
730 Processed.insert(MI);
733 /// isSafeToDelete - If the specified instruction does not produce any side
734 /// effects and all of its defs are dead, then it's safe to delete.
735 static bool isSafeToDelete(MachineInstr *MI, unsigned Reg,
736 const TargetInstrInfo *TII,
737 SmallVector<unsigned, 4> &Kills) {
738 const TargetInstrDesc &TID = MI->getDesc();
739 if (TID.mayStore() || TID.isCall())
741 if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
744 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
745 MachineOperand &MO = MI->getOperand(i);
748 if (MO.isDef() && !MO.isDead())
750 if (MO.isUse() && MO.getReg() != Reg && MO.isKill())
751 Kills.push_back(MO.getReg());
757 /// canUpdateDeletedKills - Check if all the registers listed in Kills are
758 /// killed by instructions in MBB preceding the current instruction at
759 /// position Dist. If so, return true and record information about the
760 /// preceding kills in NewKills.
761 bool TwoAddressInstructionPass::
762 canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
763 SmallVector<NewKill, 4> &NewKills,
764 MachineBasicBlock *MBB, unsigned Dist) {
765 while (!Kills.empty()) {
766 unsigned Kill = Kills.back();
768 if (TargetRegisterInfo::isPhysicalRegister(Kill))
771 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
775 bool isModRef = LastKill->modifiesRegister(Kill);
776 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
782 /// DeleteUnusedInstr - If an instruction with a tied register operand can
783 /// be safely deleted, just delete it.
785 TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
786 MachineBasicBlock::iterator &nmi,
787 MachineFunction::iterator &mbbi,
788 unsigned regB, unsigned regBIdx,
790 // Check if the instruction has no side effects and if all its defs are dead.
791 SmallVector<unsigned, 4> Kills;
792 if (!isSafeToDelete(mi, regB, TII, Kills))
795 // If this instruction kills some virtual registers, we need to
796 // update the kill information. If it's not possible to do so,
798 SmallVector<NewKill, 4> NewKills;
799 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
803 while (!NewKills.empty()) {
804 MachineInstr *NewKill = NewKills.back().second;
805 unsigned Kill = NewKills.back().first.first;
806 bool isDead = NewKills.back().first.second;
808 if (LV->removeVirtualRegisterKilled(Kill, mi)) {
810 LV->addVirtualRegisterDead(Kill, NewKill);
812 LV->addVirtualRegisterKilled(Kill, NewKill);
816 // If regB was marked as a kill, update its Kills list.
817 if (mi->getOperand(regBIdx).isKill())
818 LV->removeVirtualRegisterKilled(regB, mi);
821 mbbi->erase(mi); // Nuke the old inst.
826 /// TryInstructionTransform - For the case where an instruction has a single
827 /// pair of tied register operands, attempt some transformations that may
828 /// either eliminate the tied operands or improve the opportunities for
829 /// coalescing away the register copy. Returns true if the tied operands
830 /// are eliminated altogether.
831 bool TwoAddressInstructionPass::
832 TryInstructionTransform(MachineBasicBlock::iterator &mi,
833 MachineBasicBlock::iterator &nmi,
834 MachineFunction::iterator &mbbi,
835 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
836 const TargetInstrDesc &TID = mi->getDesc();
837 unsigned regA = mi->getOperand(DstIdx).getReg();
838 unsigned regB = mi->getOperand(SrcIdx).getReg();
840 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
841 "cannot make instruction into two-address form");
843 // If regA is dead and the instruction can be deleted, just delete
844 // it so it doesn't clobber regB.
845 bool regBKilled = isKilled(*mi, regB, MRI, TII);
846 if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
847 DeleteUnusedInstr(mi, nmi, mbbi, regB, SrcIdx, Dist)) {
849 return true; // Done with this instruction.
852 // Check if it is profitable to commute the operands.
853 unsigned SrcOp1, SrcOp2;
855 unsigned regCIdx = ~0U;
856 bool TryCommute = false;
857 bool AggressiveCommute = false;
858 if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
859 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
860 if (SrcIdx == SrcOp1)
862 else if (SrcIdx == SrcOp2)
865 if (regCIdx != ~0U) {
866 regC = mi->getOperand(regCIdx).getReg();
867 if (!regBKilled && isKilled(*mi, regC, MRI, TII))
868 // If C dies but B does not, swap the B and C operands.
869 // This makes the live ranges of A and C joinable.
871 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
873 AggressiveCommute = true;
878 // If it's profitable to commute, try to do so.
879 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
881 if (AggressiveCommute)
886 if (TID.isConvertibleTo3Addr()) {
887 // This instruction is potentially convertible to a true
888 // three-address instruction. Check if it is profitable.
889 if (!regBKilled || isProfitableToConv3Addr(regA)) {
890 // Try to convert it.
891 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
892 ++NumConvertedTo3Addr;
893 return true; // Done with this instruction.
900 /// runOnMachineFunction - Reduce two-address instructions to two operands.
902 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
903 DEBUG(errs() << "Machine Function\n");
904 const TargetMachine &TM = MF.getTarget();
905 MRI = &MF.getRegInfo();
906 TII = TM.getInstrInfo();
907 TRI = TM.getRegisterInfo();
908 LV = getAnalysisIfAvailable<LiveVariables>();
909 AA = &getAnalysis<AliasAnalysis>();
911 bool MadeChange = false;
913 DEBUG(errs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
914 DEBUG(errs() << "********** Function: "
915 << MF.getFunction()->getName() << '\n');
917 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
919 ReMatRegs.resize(MRI->getLastVirtReg()+1);
921 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
923 TiedOperandMap TiedOperands(4);
925 SmallPtrSet<MachineInstr*, 8> Processed;
926 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
927 mbbi != mbbe; ++mbbi) {
933 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
935 MachineBasicBlock::iterator nmi = next(mi);
936 const TargetInstrDesc &TID = mi->getDesc();
937 bool FirstTied = true;
939 DistanceMap.insert(std::make_pair(mi, ++Dist));
941 ProcessCopy(&*mi, &*mbbi, Processed);
943 // First scan through all the tied register uses in this instruction
944 // and record a list of pairs of tied operands for each register.
945 unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM)
946 ? mi->getNumOperands() : TID.getNumOperands();
947 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
949 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
954 ++NumTwoAddressInstrs;
955 DEBUG(errs() << '\t' << *mi);
958 assert(mi->getOperand(SrcIdx).isReg() &&
959 mi->getOperand(SrcIdx).getReg() &&
960 mi->getOperand(SrcIdx).isUse() &&
961 "two address instruction invalid");
963 unsigned regB = mi->getOperand(SrcIdx).getReg();
964 TiedOperandMap::iterator OI = TiedOperands.find(regB);
965 if (OI == TiedOperands.end()) {
966 SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
967 OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
969 OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
972 // Now iterate over the information collected above.
973 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
974 OE = TiedOperands.end(); OI != OE; ++OI) {
975 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
977 // If the instruction has a single pair of tied operands, try some
978 // transformations that may either eliminate the tied operands or
979 // improve the opportunities for coalescing away the register copy.
980 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
981 unsigned SrcIdx = TiedPairs[0].first;
982 unsigned DstIdx = TiedPairs[0].second;
984 // If the registers are already equal, nothing needs to be done.
985 if (mi->getOperand(SrcIdx).getReg() ==
986 mi->getOperand(DstIdx).getReg())
987 break; // Done with this instruction.
989 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
990 break; // The tied operands have been eliminated.
993 bool RemovedKillFlag = false;
994 bool AllUsesCopied = true;
995 unsigned LastCopiedReg = 0;
996 unsigned regB = OI->first;
997 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
998 unsigned SrcIdx = TiedPairs[tpi].first;
999 unsigned DstIdx = TiedPairs[tpi].second;
1000 unsigned regA = mi->getOperand(DstIdx).getReg();
1001 // Grab regB from the instruction because it may have changed if the
1002 // instruction was commuted.
1003 regB = mi->getOperand(SrcIdx).getReg();
1006 // The register is tied to multiple destinations (or else we would
1007 // not have continued this far), but this use of the register
1008 // already matches the tied destination. Leave it.
1009 AllUsesCopied = false;
1012 LastCopiedReg = regA;
1014 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1015 "cannot make instruction into two-address form");
1018 // First, verify that we don't have a use of "a" in the instruction
1019 // (a = b + a for example) because our transformation will not
1020 // work. This should never occur because we are in SSA form.
1021 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1022 assert(i == DstIdx ||
1023 !mi->getOperand(i).isReg() ||
1024 mi->getOperand(i).getReg() != regA);
1027 // Emit a copy or rematerialize the definition.
1028 const TargetRegisterClass *rc = MRI->getRegClass(regB);
1029 MachineInstr *DefMI = MRI->getVRegDef(regB);
1030 // If it's safe and profitable, remat the definition instead of
1033 DefMI->getDesc().isAsCheapAsAMove() &&
1034 DefMI->isSafeToReMat(TII, regB, AA) &&
1035 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1036 DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
1037 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1038 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
1039 ReMatRegs.set(regB);
1042 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
1044 assert(Emitted && "Unable to issue a copy instruction!\n");
1047 MachineBasicBlock::iterator prevMI = prior(mi);
1048 // Update DistanceMap.
1049 DistanceMap.insert(std::make_pair(prevMI, Dist));
1050 DistanceMap[mi] = ++Dist;
1052 DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
1054 MachineOperand &MO = mi->getOperand(SrcIdx);
1055 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1056 "inconsistent operand info for 2-reg pass");
1058 MO.setIsKill(false);
1059 RemovedKillFlag = true;
1064 if (AllUsesCopied) {
1065 // Replace other (un-tied) uses of regB with LastCopiedReg.
1066 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1067 MachineOperand &MO = mi->getOperand(i);
1068 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1070 MO.setIsKill(false);
1071 RemovedKillFlag = true;
1073 MO.setReg(LastCopiedReg);
1077 // Update live variables for regB.
1078 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1079 LV->addVirtualRegisterKilled(regB, prior(mi));
1081 } else if (RemovedKillFlag) {
1082 // Some tied uses of regB matched their destination registers, so
1083 // regB is still used in this instruction, but a kill flag was
1084 // removed from a different tied use of regB, so now we need to add
1085 // a kill flag to one of the remaining uses of regB.
1086 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1087 MachineOperand &MO = mi->getOperand(i);
1088 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1097 DEBUG(errs() << "\t\trewrite to:\t" << *mi);
1100 // Clear TiedOperands here instead of at the top of the loop
1101 // since most instructions do not have tied operands.
1102 TiedOperands.clear();
1107 // Some remat'ed instructions are dead.
1108 int VReg = ReMatRegs.find_first();
1109 while (VReg != -1) {
1110 if (MRI->use_empty(VReg)) {
1111 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1112 DefMI->eraseFromParent();
1114 VReg = ReMatRegs.find_next(VReg);