1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/Analysis/AliasAnalysis.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/ADT/BitVector.h"
46 #include "llvm/ADT/DenseMap.h"
47 #include "llvm/ADT/SmallSet.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/ADT/STLExtras.h"
52 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
53 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
54 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
55 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
56 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
57 STATISTIC(NumReMats, "Number of instructions re-materialized");
58 STATISTIC(NumDeletes, "Number of dead instructions deleted");
61 class TwoAddressInstructionPass : public MachineFunctionPass {
62 const TargetInstrInfo *TII;
63 const TargetRegisterInfo *TRI;
64 MachineRegisterInfo *MRI;
68 // DistanceMap - Keep track the distance of a MI from the start of the
69 // current basic block.
70 DenseMap<MachineInstr*, unsigned> DistanceMap;
72 // SrcRegMap - A map from virtual registers to physical registers which
73 // are likely targets to be coalesced to due to copies from physical
74 // registers to virtual registers. e.g. v1024 = move r0.
75 DenseMap<unsigned, unsigned> SrcRegMap;
77 // DstRegMap - A map from virtual registers to physical registers which
78 // are likely targets to be coalesced to due to copies to physical
79 // registers from virtual registers. e.g. r1 = move v1024.
80 DenseMap<unsigned, unsigned> DstRegMap;
82 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
83 /// during the initial walk of the machine function.
84 SmallVector<MachineInstr*, 16> RegSequences;
86 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
88 MachineBasicBlock::iterator OldPos);
90 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
91 MachineInstr *MI, MachineInstr *DefMI,
92 MachineBasicBlock *MBB, unsigned Loc);
94 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
97 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
100 bool isProfitableToCommute(unsigned regB, unsigned regC,
101 MachineInstr *MI, MachineBasicBlock *MBB,
104 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
105 MachineFunction::iterator &mbbi,
106 unsigned RegB, unsigned RegC, unsigned Dist);
108 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
110 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
111 MachineBasicBlock::iterator &nmi,
112 MachineFunction::iterator &mbbi,
113 unsigned RegA, unsigned RegB, unsigned Dist);
115 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
116 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
117 SmallVector<NewKill, 4> &NewKills,
118 MachineBasicBlock *MBB, unsigned Dist);
119 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
120 MachineBasicBlock::iterator &nmi,
121 MachineFunction::iterator &mbbi, unsigned Dist);
123 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
124 MachineBasicBlock::iterator &nmi,
125 MachineFunction::iterator &mbbi,
126 unsigned SrcIdx, unsigned DstIdx,
128 SmallPtrSet<MachineInstr*, 8> &Processed);
130 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
131 SmallPtrSet<MachineInstr*, 8> &Processed);
133 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
134 SmallPtrSet<MachineInstr*, 8> &Processed);
136 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
138 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
139 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
140 /// sub-register references of the register defined by REG_SEQUENCE.
141 bool EliminateRegSequences();
144 static char ID; // Pass identification, replacement for typeid
145 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
146 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
149 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
150 AU.setPreservesCFG();
151 AU.addRequired<AliasAnalysis>();
152 AU.addPreserved<LiveVariables>();
153 AU.addPreservedID(MachineLoopInfoID);
154 AU.addPreservedID(MachineDominatorsID);
155 AU.addPreservedID(PHIEliminationID);
156 MachineFunctionPass::getAnalysisUsage(AU);
159 /// runOnMachineFunction - Pass entry point.
160 bool runOnMachineFunction(MachineFunction&);
164 char TwoAddressInstructionPass::ID = 0;
165 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
166 "Two-Address instruction pass", false, false)
167 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
168 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
169 "Two-Address instruction pass", false, false)
171 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
173 /// Sink3AddrInstruction - A two-address instruction has been converted to a
174 /// three-address instruction to avoid clobbering a register. Try to sink it
175 /// past the instruction that would kill the above mentioned register to reduce
176 /// register pressure.
177 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
178 MachineInstr *MI, unsigned SavedReg,
179 MachineBasicBlock::iterator OldPos) {
180 // FIXME: Shouldn't we be trying to do this before we three-addressify the
181 // instruction? After this transformation is done, we no longer need
182 // the instruction to be in three-address form.
184 // Check if it's safe to move this instruction.
185 bool SeenStore = true; // Be conservative.
186 if (!MI->isSafeToMove(TII, AA, SeenStore))
190 SmallSet<unsigned, 4> UseRegs;
192 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
193 const MachineOperand &MO = MI->getOperand(i);
196 unsigned MOReg = MO.getReg();
199 if (MO.isUse() && MOReg != SavedReg)
200 UseRegs.insert(MO.getReg());
204 // Don't try to move it if it implicitly defines a register.
207 // For now, don't move any instructions that define multiple registers.
209 DefReg = MO.getReg();
212 // Find the instruction that kills SavedReg.
213 MachineInstr *KillMI = NULL;
214 for (MachineRegisterInfo::use_nodbg_iterator
215 UI = MRI->use_nodbg_begin(SavedReg),
216 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
217 MachineOperand &UseMO = UI.getOperand();
220 KillMI = UseMO.getParent();
224 // If we find the instruction that kills SavedReg, and it is in an
225 // appropriate location, we can try to sink the current instruction
227 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
228 KillMI->getDesc().isTerminator())
231 // If any of the definitions are used by another instruction between the
232 // position and the kill use, then it's not safe to sink it.
234 // FIXME: This can be sped up if there is an easy way to query whether an
235 // instruction is before or after another instruction. Then we can use
236 // MachineRegisterInfo def / use instead.
237 MachineOperand *KillMO = NULL;
238 MachineBasicBlock::iterator KillPos = KillMI;
241 unsigned NumVisited = 0;
242 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
243 MachineInstr *OtherMI = I;
244 // DBG_VALUE cannot be counted against the limit.
245 if (OtherMI->isDebugValue())
247 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
250 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
251 MachineOperand &MO = OtherMI->getOperand(i);
254 unsigned MOReg = MO.getReg();
261 if (OtherMI == KillMI && MOReg == SavedReg)
262 // Save the operand that kills the register. We want to unset the kill
263 // marker if we can sink MI past it.
265 else if (UseRegs.count(MOReg))
266 // One of the uses is killed before the destination.
272 // Update kill and LV information.
273 KillMO->setIsKill(false);
274 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
275 KillMO->setIsKill(true);
278 LV->replaceKillInstruction(SavedReg, KillMI, MI);
280 // Move instruction to its destination.
282 MBB->insert(KillPos, MI);
288 /// isTwoAddrUse - Return true if the specified MI is using the specified
289 /// register as a two-address operand.
290 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
291 const MCInstrDesc &MCID = UseMI->getDesc();
292 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
293 MachineOperand &MO = UseMI->getOperand(i);
294 if (MO.isReg() && MO.getReg() == Reg &&
295 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
296 // Earlier use is a two-address one.
302 /// isProfitableToReMat - Return true if the heuristics determines it is likely
303 /// to be profitable to re-materialize the definition of Reg rather than copy
306 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
307 const TargetRegisterClass *RC,
308 MachineInstr *MI, MachineInstr *DefMI,
309 MachineBasicBlock *MBB, unsigned Loc) {
310 bool OtherUse = false;
311 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
312 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
313 MachineOperand &UseMO = UI.getOperand();
314 MachineInstr *UseMI = UseMO.getParent();
315 MachineBasicBlock *UseMBB = UseMI->getParent();
317 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
318 if (DI != DistanceMap.end() && DI->second == Loc)
319 continue; // Current use.
321 // There is at least one other use in the MBB that will clobber the
323 if (isTwoAddrUse(UseMI, Reg))
328 // If other uses in MBB are not two-address uses, then don't remat.
332 // No other uses in the same block, remat if it's defined in the same
333 // block so it does not unnecessarily extend the live range.
334 return MBB == DefMI->getParent();
337 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
338 /// last instruction in the MBB that defines the specified register and the
339 /// two-address instruction which is being processed. It also returns the last
340 /// def location by reference
341 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
342 MachineBasicBlock *MBB, unsigned Dist,
345 unsigned LastUse = Dist;
346 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
347 E = MRI->reg_end(); I != E; ++I) {
348 MachineOperand &MO = I.getOperand();
349 MachineInstr *MI = MO.getParent();
350 if (MI->getParent() != MBB || MI->isDebugValue())
352 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
353 if (DI == DistanceMap.end())
355 if (MO.isUse() && DI->second < LastUse)
356 LastUse = DI->second;
357 if (MO.isDef() && DI->second > LastDef)
358 LastDef = DI->second;
361 return !(LastUse > LastDef && LastUse < Dist);
364 MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
365 MachineBasicBlock *MBB,
367 unsigned LastUseDist = 0;
368 MachineInstr *LastUse = 0;
369 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
370 E = MRI->reg_end(); I != E; ++I) {
371 MachineOperand &MO = I.getOperand();
372 MachineInstr *MI = MO.getParent();
373 if (MI->getParent() != MBB || MI->isDebugValue())
375 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
376 if (DI == DistanceMap.end())
378 if (DI->second >= Dist)
381 if (MO.isUse() && DI->second > LastUseDist) {
383 LastUseDist = DI->second;
389 /// isCopyToReg - Return true if the specified MI is a copy instruction or
390 /// a extract_subreg instruction. It also returns the source and destination
391 /// registers and whether they are physical registers by reference.
392 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
393 unsigned &SrcReg, unsigned &DstReg,
394 bool &IsSrcPhys, bool &IsDstPhys) {
398 DstReg = MI.getOperand(0).getReg();
399 SrcReg = MI.getOperand(1).getReg();
400 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
401 DstReg = MI.getOperand(0).getReg();
402 SrcReg = MI.getOperand(2).getReg();
406 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
407 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
411 /// isKilled - Test if the given register value, which is used by the given
412 /// instruction, is killed by the given instruction. This looks through
413 /// coalescable copies to see if the original value is potentially not killed.
415 /// For example, in this code:
417 /// %reg1034 = copy %reg1024
418 /// %reg1035 = copy %reg1025<kill>
419 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
421 /// %reg1034 is not considered to be killed, since it is copied from a
422 /// register which is not killed. Treating it as not killed lets the
423 /// normal heuristics commute the (two-address) add, which lets
424 /// coalescing eliminate the extra copy.
426 static bool isKilled(MachineInstr &MI, unsigned Reg,
427 const MachineRegisterInfo *MRI,
428 const TargetInstrInfo *TII) {
429 MachineInstr *DefMI = &MI;
431 if (!DefMI->killsRegister(Reg))
433 if (TargetRegisterInfo::isPhysicalRegister(Reg))
435 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
436 // If there are multiple defs, we can't do a simple analysis, so just
437 // go with what the kill flag says.
438 if (llvm::next(Begin) != MRI->def_end())
441 bool IsSrcPhys, IsDstPhys;
442 unsigned SrcReg, DstReg;
443 // If the def is something other than a copy, then it isn't going to
444 // be coalesced, so follow the kill flag.
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
451 /// isTwoAddrUse - Return true if the specified MI uses the specified register
452 /// as a two-address use. If so, return the destination register by reference.
453 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
454 const MCInstrDesc &MCID = MI.getDesc();
455 unsigned NumOps = MI.isInlineAsm()
456 ? MI.getNumOperands() : MCID.getNumOperands();
457 for (unsigned i = 0; i != NumOps; ++i) {
458 const MachineOperand &MO = MI.getOperand(i);
459 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
462 if (MI.isRegTiedToDefOperand(i, &ti)) {
463 DstReg = MI.getOperand(ti).getReg();
470 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
471 /// use, return the use instruction if it's a copy or a two-address use.
473 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
474 MachineRegisterInfo *MRI,
475 const TargetInstrInfo *TII,
477 unsigned &DstReg, bool &IsDstPhys) {
478 if (!MRI->hasOneNonDBGUse(Reg))
479 // None or more than one use.
481 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
482 if (UseMI.getParent() != MBB)
486 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
491 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
492 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
498 /// getMappedReg - Return the physical register the specified virtual register
499 /// might be mapped to.
501 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
502 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
503 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
504 if (SI == RegMap.end())
508 if (TargetRegisterInfo::isPhysicalRegister(Reg))
513 /// regsAreCompatible - Return true if the two registers are equal or aliased.
516 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
521 return TRI->regsOverlap(RegA, RegB);
525 /// isProfitableToReMat - Return true if it's potentially profitable to commute
526 /// the two-address instruction that's being processed.
528 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
529 MachineInstr *MI, MachineBasicBlock *MBB,
531 // Determine if it's profitable to commute this two address instruction. In
532 // general, we want no uses between this instruction and the definition of
533 // the two-address register.
535 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
536 // %reg1029<def> = MOV8rr %reg1028
537 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
538 // insert => %reg1030<def> = MOV8rr %reg1028
539 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
540 // In this case, it might not be possible to coalesce the second MOV8rr
541 // instruction if the first one is coalesced. So it would be profitable to
543 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
544 // %reg1029<def> = MOV8rr %reg1028
545 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
546 // insert => %reg1030<def> = MOV8rr %reg1029
547 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
549 if (!MI->killsRegister(regC))
552 // Ok, we have something like:
553 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
554 // let's see if it's worth commuting it.
556 // Look for situations like this:
557 // %reg1024<def> = MOV r1
558 // %reg1025<def> = MOV r0
559 // %reg1026<def> = ADD %reg1024, %reg1025
561 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
562 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
563 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
564 unsigned ToRegB = getMappedReg(regB, DstRegMap);
565 unsigned ToRegC = getMappedReg(regC, DstRegMap);
566 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) &&
567 ((!FromRegC && !ToRegC) ||
568 regsAreCompatible(FromRegB, ToRegC, TRI) ||
569 regsAreCompatible(FromRegC, ToRegB, TRI)))
572 // If there is a use of regC between its last def (could be livein) and this
573 // instruction, then bail.
574 unsigned LastDefC = 0;
575 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
578 // If there is a use of regB between its last def (could be livein) and this
579 // instruction, then go ahead and make this transformation.
580 unsigned LastDefB = 0;
581 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
584 // Since there are no intervening uses for both registers, then commute
585 // if the def of regC is closer. Its live interval is shorter.
586 return LastDefB && LastDefC && LastDefC > LastDefB;
589 /// CommuteInstruction - Commute a two-address instruction and update the basic
590 /// block, distance map, and live variables if needed. Return true if it is
593 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
594 MachineFunction::iterator &mbbi,
595 unsigned RegB, unsigned RegC, unsigned Dist) {
596 MachineInstr *MI = mi;
597 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
598 MachineInstr *NewMI = TII->commuteInstruction(MI);
601 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
605 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
606 // If the instruction changed to commute it, update livevar.
609 // Update live variables
610 LV->replaceKillInstruction(RegC, MI, NewMI);
612 mbbi->insert(mi, NewMI); // Insert the new inst
613 mbbi->erase(mi); // Nuke the old inst.
615 DistanceMap.insert(std::make_pair(NewMI, Dist));
618 // Update source register map.
619 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
621 unsigned RegA = MI->getOperand(0).getReg();
622 SrcRegMap[RegA] = FromRegC;
628 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
629 /// given 2-address instruction to a 3-address one.
631 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
632 // Look for situations like this:
633 // %reg1024<def> = MOV r1
634 // %reg1025<def> = MOV r0
635 // %reg1026<def> = ADD %reg1024, %reg1025
637 // Turn ADD into a 3-address instruction to avoid a copy.
638 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
641 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
642 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
645 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
646 /// three address one. Return true if this transformation was successful.
648 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
649 MachineBasicBlock::iterator &nmi,
650 MachineFunction::iterator &mbbi,
651 unsigned RegA, unsigned RegB,
653 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
655 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
656 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
659 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
660 // FIXME: Temporary workaround. If the new instruction doesn't
661 // uses RegB, convertToThreeAddress must have created more
662 // then one instruction.
663 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
665 mbbi->erase(mi); // Nuke the old inst.
668 DistanceMap.insert(std::make_pair(NewMI, Dist));
670 nmi = llvm::next(mi);
673 // Update source and destination register maps.
674 SrcRegMap.erase(RegA);
675 DstRegMap.erase(RegB);
682 /// ScanUses - Scan forward recursively for only uses, update maps if the use
683 /// is a copy or a two-address instruction.
685 TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
686 SmallPtrSet<MachineInstr*, 8> &Processed) {
687 SmallVector<unsigned, 4> VirtRegPairs;
691 unsigned Reg = DstReg;
692 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
693 NewReg, IsDstPhys)) {
694 if (IsCopy && !Processed.insert(UseMI))
697 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
698 if (DI != DistanceMap.end())
699 // Earlier in the same MBB.Reached via a back edge.
703 VirtRegPairs.push_back(NewReg);
706 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
708 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
709 VirtRegPairs.push_back(NewReg);
713 if (!VirtRegPairs.empty()) {
714 unsigned ToReg = VirtRegPairs.back();
715 VirtRegPairs.pop_back();
716 while (!VirtRegPairs.empty()) {
717 unsigned FromReg = VirtRegPairs.back();
718 VirtRegPairs.pop_back();
719 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
721 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
724 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
726 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
730 /// ProcessCopy - If the specified instruction is not yet processed, process it
731 /// if it's a copy. For a copy instruction, we find the physical registers the
732 /// source and destination registers might be mapped to. These are kept in
733 /// point-to maps used to determine future optimizations. e.g.
736 /// v1026 = add v1024, v1025
738 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
739 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
740 /// potentially joined with r1 on the output side. It's worthwhile to commute
741 /// 'add' to eliminate a copy.
742 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
743 MachineBasicBlock *MBB,
744 SmallPtrSet<MachineInstr*, 8> &Processed) {
745 if (Processed.count(MI))
748 bool IsSrcPhys, IsDstPhys;
749 unsigned SrcReg, DstReg;
750 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
753 if (IsDstPhys && !IsSrcPhys)
754 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
755 else if (!IsDstPhys && IsSrcPhys) {
756 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
758 assert(SrcRegMap[DstReg] == SrcReg &&
759 "Can't map to two src physical registers!");
761 ScanUses(DstReg, MBB, Processed);
764 Processed.insert(MI);
768 /// isSafeToDelete - If the specified instruction does not produce any side
769 /// effects and all of its defs are dead, then it's safe to delete.
770 static bool isSafeToDelete(MachineInstr *MI,
771 const TargetInstrInfo *TII,
772 SmallVector<unsigned, 4> &Kills) {
773 const MCInstrDesc &MCID = MI->getDesc();
774 if (MCID.mayStore() || MCID.isCall())
776 if (MCID.isTerminator() || MI->hasUnmodeledSideEffects())
779 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
780 MachineOperand &MO = MI->getOperand(i);
783 if (MO.isDef() && !MO.isDead())
785 if (MO.isUse() && MO.isKill())
786 Kills.push_back(MO.getReg());
791 /// canUpdateDeletedKills - Check if all the registers listed in Kills are
792 /// killed by instructions in MBB preceding the current instruction at
793 /// position Dist. If so, return true and record information about the
794 /// preceding kills in NewKills.
795 bool TwoAddressInstructionPass::
796 canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
797 SmallVector<NewKill, 4> &NewKills,
798 MachineBasicBlock *MBB, unsigned Dist) {
799 while (!Kills.empty()) {
800 unsigned Kill = Kills.back();
802 if (TargetRegisterInfo::isPhysicalRegister(Kill))
805 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
809 bool isModRef = LastKill->definesRegister(Kill);
810 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
816 /// DeleteUnusedInstr - If an instruction with a tied register operand can
817 /// be safely deleted, just delete it.
819 TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
820 MachineBasicBlock::iterator &nmi,
821 MachineFunction::iterator &mbbi,
823 // Check if the instruction has no side effects and if all its defs are dead.
824 SmallVector<unsigned, 4> Kills;
825 if (!isSafeToDelete(mi, TII, Kills))
828 // If this instruction kills some virtual registers, we need to
829 // update the kill information. If it's not possible to do so,
831 SmallVector<NewKill, 4> NewKills;
832 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
836 while (!NewKills.empty()) {
837 MachineInstr *NewKill = NewKills.back().second;
838 unsigned Kill = NewKills.back().first.first;
839 bool isDead = NewKills.back().first.second;
841 if (LV->removeVirtualRegisterKilled(Kill, mi)) {
843 LV->addVirtualRegisterDead(Kill, NewKill);
845 LV->addVirtualRegisterKilled(Kill, NewKill);
850 mbbi->erase(mi); // Nuke the old inst.
855 /// TryInstructionTransform - For the case where an instruction has a single
856 /// pair of tied register operands, attempt some transformations that may
857 /// either eliminate the tied operands or improve the opportunities for
858 /// coalescing away the register copy. Returns true if the tied operands
859 /// are eliminated altogether.
860 bool TwoAddressInstructionPass::
861 TryInstructionTransform(MachineBasicBlock::iterator &mi,
862 MachineBasicBlock::iterator &nmi,
863 MachineFunction::iterator &mbbi,
864 unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
865 SmallPtrSet<MachineInstr*, 8> &Processed) {
866 const MCInstrDesc &MCID = mi->getDesc();
867 unsigned regA = mi->getOperand(DstIdx).getReg();
868 unsigned regB = mi->getOperand(SrcIdx).getReg();
870 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
871 "cannot make instruction into two-address form");
873 // If regA is dead and the instruction can be deleted, just delete
874 // it so it doesn't clobber regB.
875 bool regBKilled = isKilled(*mi, regB, MRI, TII);
876 if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
877 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
879 return true; // Done with this instruction.
882 // Check if it is profitable to commute the operands.
883 unsigned SrcOp1, SrcOp2;
885 unsigned regCIdx = ~0U;
886 bool TryCommute = false;
887 bool AggressiveCommute = false;
888 if (MCID.isCommutable() && mi->getNumOperands() >= 3 &&
889 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
890 if (SrcIdx == SrcOp1)
892 else if (SrcIdx == SrcOp2)
895 if (regCIdx != ~0U) {
896 regC = mi->getOperand(regCIdx).getReg();
897 if (!regBKilled && isKilled(*mi, regC, MRI, TII))
898 // If C dies but B does not, swap the B and C operands.
899 // This makes the live ranges of A and C joinable.
901 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
903 AggressiveCommute = true;
908 // If it's profitable to commute, try to do so.
909 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
911 if (AggressiveCommute)
916 if (TargetRegisterInfo::isVirtualRegister(regA))
917 ScanUses(regA, &*mbbi, Processed);
919 if (MCID.isConvertibleTo3Addr()) {
920 // This instruction is potentially convertible to a true
921 // three-address instruction. Check if it is profitable.
922 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
923 // Try to convert it.
924 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) {
925 ++NumConvertedTo3Addr;
926 return true; // Done with this instruction.
931 // If this is an instruction with a load folded into it, try unfolding
932 // the load, e.g. avoid this:
938 // because it's preferable to schedule a load than a register copy.
939 if (MCID.mayLoad() && !regBKilled) {
940 // Determine if a load can be unfolded.
941 unsigned LoadRegIndex;
943 TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(),
945 /*UnfoldStore=*/false,
948 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
949 if (UnfoldMCID.getNumDefs() == 1) {
950 MachineFunction &MF = *mbbi->getParent();
953 DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
954 const TargetRegisterClass *RC =
955 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
956 unsigned Reg = MRI->createVirtualRegister(RC);
957 SmallVector<MachineInstr *, 2> NewMIs;
958 if (!TII->unfoldMemoryOperand(MF, mi, Reg,
959 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
961 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
964 assert(NewMIs.size() == 2 &&
965 "Unfolded a load into multiple instructions!");
966 // The load was previously folded, so this is the only use.
967 NewMIs[1]->addRegisterKilled(Reg, TRI);
969 // Tentatively insert the instructions into the block so that they
970 // look "normal" to the transformation logic.
971 mbbi->insert(mi, NewMIs[0]);
972 mbbi->insert(mi, NewMIs[1]);
974 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
975 << "2addr: NEW INST: " << *NewMIs[1]);
977 // Transform the instruction, now that it no longer has a load.
978 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
979 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
980 MachineBasicBlock::iterator NewMI = NewMIs[1];
981 bool TransformSuccess =
982 TryInstructionTransform(NewMI, mi, mbbi,
983 NewSrcIdx, NewDstIdx, Dist, Processed);
984 if (TransformSuccess ||
985 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
986 // Success, or at least we made an improvement. Keep the unfolded
987 // instructions and discard the original.
989 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
990 MachineOperand &MO = mi->getOperand(i);
992 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
995 if (NewMIs[0]->killsRegister(MO.getReg()))
996 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]);
998 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
999 "Kill missing after load unfold!");
1000 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]);
1003 } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) {
1004 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1005 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1007 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1008 "Dead flag missing after load unfold!");
1009 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1014 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1016 mi->eraseFromParent();
1018 if (TransformSuccess)
1021 // Transforming didn't eliminate the tie and didn't lead to an
1022 // improvement. Clean up the unfolded instructions and keep the
1024 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1025 NewMIs[0]->eraseFromParent();
1026 NewMIs[1]->eraseFromParent();
1035 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1037 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
1038 DEBUG(dbgs() << "Machine Function\n");
1039 const TargetMachine &TM = MF.getTarget();
1040 MRI = &MF.getRegInfo();
1041 TII = TM.getInstrInfo();
1042 TRI = TM.getRegisterInfo();
1043 LV = getAnalysisIfAvailable<LiveVariables>();
1044 AA = &getAnalysis<AliasAnalysis>();
1046 bool MadeChange = false;
1048 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1049 DEBUG(dbgs() << "********** Function: "
1050 << MF.getFunction()->getName() << '\n');
1052 // This pass takes the function out of SSA form.
1055 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
1056 BitVector ReMatRegs(MRI->getNumVirtRegs());
1058 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
1060 TiedOperandMap TiedOperands(4);
1062 SmallPtrSet<MachineInstr*, 8> Processed;
1063 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
1064 mbbi != mbbe; ++mbbi) {
1066 DistanceMap.clear();
1070 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
1072 MachineBasicBlock::iterator nmi = llvm::next(mi);
1073 if (mi->isDebugValue()) {
1078 // Remember REG_SEQUENCE instructions, we'll deal with them later.
1079 if (mi->isRegSequence())
1080 RegSequences.push_back(&*mi);
1082 const MCInstrDesc &MCID = mi->getDesc();
1083 bool FirstTied = true;
1085 DistanceMap.insert(std::make_pair(mi, ++Dist));
1087 ProcessCopy(&*mi, &*mbbi, Processed);
1089 // First scan through all the tied register uses in this instruction
1090 // and record a list of pairs of tied operands for each register.
1091 unsigned NumOps = mi->isInlineAsm()
1092 ? mi->getNumOperands() : MCID.getNumOperands();
1093 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1094 unsigned DstIdx = 0;
1095 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1100 ++NumTwoAddressInstrs;
1101 DEBUG(dbgs() << '\t' << *mi);
1104 assert(mi->getOperand(SrcIdx).isReg() &&
1105 mi->getOperand(SrcIdx).getReg() &&
1106 mi->getOperand(SrcIdx).isUse() &&
1107 "two address instruction invalid");
1109 unsigned regB = mi->getOperand(SrcIdx).getReg();
1110 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx));
1113 // Now iterate over the information collected above.
1114 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1115 OE = TiedOperands.end(); OI != OE; ++OI) {
1116 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
1118 // If the instruction has a single pair of tied operands, try some
1119 // transformations that may either eliminate the tied operands or
1120 // improve the opportunities for coalescing away the register copy.
1121 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
1122 unsigned SrcIdx = TiedPairs[0].first;
1123 unsigned DstIdx = TiedPairs[0].second;
1125 // If the registers are already equal, nothing needs to be done.
1126 if (mi->getOperand(SrcIdx).getReg() ==
1127 mi->getOperand(DstIdx).getReg())
1128 break; // Done with this instruction.
1130 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist,
1132 break; // The tied operands have been eliminated.
1135 bool IsEarlyClobber = false;
1136 bool RemovedKillFlag = false;
1137 bool AllUsesCopied = true;
1138 unsigned LastCopiedReg = 0;
1139 unsigned regB = OI->first;
1140 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1141 unsigned SrcIdx = TiedPairs[tpi].first;
1142 unsigned DstIdx = TiedPairs[tpi].second;
1144 const MachineOperand &DstMO = mi->getOperand(DstIdx);
1145 unsigned regA = DstMO.getReg();
1146 IsEarlyClobber |= DstMO.isEarlyClobber();
1148 // Grab regB from the instruction because it may have changed if the
1149 // instruction was commuted.
1150 regB = mi->getOperand(SrcIdx).getReg();
1153 // The register is tied to multiple destinations (or else we would
1154 // not have continued this far), but this use of the register
1155 // already matches the tied destination. Leave it.
1156 AllUsesCopied = false;
1159 LastCopiedReg = regA;
1161 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1162 "cannot make instruction into two-address form");
1165 // First, verify that we don't have a use of "a" in the instruction
1166 // (a = b + a for example) because our transformation will not
1167 // work. This should never occur because we are in SSA form.
1168 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1169 assert(i == DstIdx ||
1170 !mi->getOperand(i).isReg() ||
1171 mi->getOperand(i).getReg() != regA);
1174 // Emit a copy or rematerialize the definition.
1175 const TargetRegisterClass *rc = MRI->getRegClass(regB);
1176 MachineInstr *DefMI = MRI->getVRegDef(regB);
1177 // If it's safe and profitable, remat the definition instead of
1180 DefMI->getDesc().isAsCheapAsAMove() &&
1181 DefMI->isSafeToReMat(TII, AA, regB) &&
1182 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1183 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
1184 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1185 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
1186 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
1189 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
1193 MachineBasicBlock::iterator prevMI = prior(mi);
1194 // Update DistanceMap.
1195 DistanceMap.insert(std::make_pair(prevMI, Dist));
1196 DistanceMap[mi] = ++Dist;
1198 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
1200 MachineOperand &MO = mi->getOperand(SrcIdx);
1201 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1202 "inconsistent operand info for 2-reg pass");
1204 MO.setIsKill(false);
1205 RemovedKillFlag = true;
1210 if (AllUsesCopied) {
1211 if (!IsEarlyClobber) {
1212 // Replace other (un-tied) uses of regB with LastCopiedReg.
1213 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1214 MachineOperand &MO = mi->getOperand(i);
1215 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1217 MO.setIsKill(false);
1218 RemovedKillFlag = true;
1220 MO.setReg(LastCopiedReg);
1225 // Update live variables for regB.
1226 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1227 LV->addVirtualRegisterKilled(regB, prior(mi));
1229 } else if (RemovedKillFlag) {
1230 // Some tied uses of regB matched their destination registers, so
1231 // regB is still used in this instruction, but a kill flag was
1232 // removed from a different tied use of regB, so now we need to add
1233 // a kill flag to one of the remaining uses of regB.
1234 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1235 MachineOperand &MO = mi->getOperand(i);
1236 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1243 // Schedule the source copy / remat inserted to form two-address
1244 // instruction. FIXME: Does it matter the distance map may not be
1245 // accurate after it's scheduled?
1246 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
1250 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1253 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1254 if (mi->isInsertSubreg()) {
1255 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1256 // To %reg:subidx = COPY %subreg
1257 unsigned SubIdx = mi->getOperand(3).getImm();
1258 mi->RemoveOperand(3);
1259 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1260 mi->getOperand(0).setSubReg(SubIdx);
1261 mi->RemoveOperand(1);
1262 mi->setDesc(TII->get(TargetOpcode::COPY));
1263 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1266 // Clear TiedOperands here instead of at the top of the loop
1267 // since most instructions do not have tied operands.
1268 TiedOperands.clear();
1273 // Some remat'ed instructions are dead.
1274 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
1275 unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
1276 if (MRI->use_nodbg_empty(VReg)) {
1277 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1278 DefMI->eraseFromParent();
1282 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1283 // SSA form. It's now safe to de-SSA.
1284 MadeChange |= EliminateRegSequences();
1289 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1290 unsigned DstReg, unsigned SubIdx,
1291 MachineRegisterInfo *MRI,
1292 const TargetRegisterInfo &TRI) {
1293 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1294 RE = MRI->reg_end(); RI != RE; ) {
1295 MachineOperand &MO = RI.getOperand();
1297 MO.substVirtReg(DstReg, SubIdx, TRI);
1301 /// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
1302 /// EXTRACT_SUBREG from the same register and to the same virtual register
1303 /// with different sub-register indices, attempt to combine the
1304 /// EXTRACT_SUBREGs and pre-coalesce them. e.g.
1305 /// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
1306 /// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
1307 /// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
1308 /// Since D subregs 5, 6 can combine to a Q register, we can coalesce
1309 /// reg1026 to reg1029.
1311 TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
1313 SmallSet<unsigned, 4> Seen;
1314 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
1315 unsigned SrcReg = Srcs[i];
1316 if (!Seen.insert(SrcReg))
1319 // Check that the instructions are all in the same basic block.
1320 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg);
1321 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg);
1322 if (SrcDefMI->getParent() != DstDefMI->getParent())
1325 // If there are no other uses than copies which feed into
1326 // the reg_sequence, then we might be able to coalesce them.
1327 bool CanCoalesce = true;
1328 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
1329 for (MachineRegisterInfo::use_nodbg_iterator
1330 UI = MRI->use_nodbg_begin(SrcReg),
1331 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1332 MachineInstr *UseMI = &*UI;
1333 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
1334 CanCoalesce = false;
1337 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
1338 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
1341 if (!CanCoalesce || SrcSubIndices.size() < 2)
1344 // Check that the source subregisters can be combined.
1345 std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
1346 unsigned NewSrcSubIdx = 0;
1347 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
1351 // Check that the destination subregisters can also be combined.
1352 std::sort(DstSubIndices.begin(), DstSubIndices.end());
1353 unsigned NewDstSubIdx = 0;
1354 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
1358 // If neither source nor destination can be combined to the full register,
1359 // just give up. This could be improved if it ever matters.
1360 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
1363 // Now that we know that all the uses are extract_subregs and that those
1364 // subregs can somehow be combined, scan all the extract_subregs again to
1365 // make sure the subregs are in the right order and can be composed.
1366 MachineInstr *SomeMI = 0;
1368 for (MachineRegisterInfo::use_nodbg_iterator
1369 UI = MRI->use_nodbg_begin(SrcReg),
1370 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1371 MachineInstr *UseMI = &*UI;
1372 assert(UseMI->isCopy());
1373 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
1374 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
1375 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
1376 if ((NewDstSubIdx == 0 &&
1377 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
1378 (NewSrcSubIdx == 0 &&
1379 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
1380 CanCoalesce = false;
1383 // Keep track of one of the uses.
1389 // Insert a copy to replace the original.
1390 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
1391 SomeMI->getDebugLoc(),
1392 TII->get(TargetOpcode::COPY))
1393 .addReg(DstReg, RegState::Define, NewDstSubIdx)
1394 .addReg(SrcReg, 0, NewSrcSubIdx);
1396 // Remove all the old extract instructions.
1397 for (MachineRegisterInfo::use_nodbg_iterator
1398 UI = MRI->use_nodbg_begin(SrcReg),
1399 UE = MRI->use_nodbg_end(); UI != UE; ) {
1400 MachineInstr *UseMI = &*UI;
1402 if (UseMI == CopyMI)
1404 assert(UseMI->isCopy());
1405 // Move any kills to the new copy or extract instruction.
1406 if (UseMI->getOperand(1).isKill()) {
1407 CopyMI->getOperand(1).setIsKill();
1409 // Update live variables
1410 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
1412 UseMI->eraseFromParent();
1417 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
1418 MachineRegisterInfo *MRI) {
1419 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
1420 UE = MRI->use_end(); UI != UE; ++UI) {
1421 MachineInstr *UseMI = &*UI;
1422 if (UseMI != RegSeq && UseMI->isRegSequence())
1428 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1429 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1430 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1432 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1433 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1435 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1436 bool TwoAddressInstructionPass::EliminateRegSequences() {
1437 if (RegSequences.empty())
1440 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1441 MachineInstr *MI = RegSequences[i];
1442 unsigned DstReg = MI->getOperand(0).getReg();
1443 if (MI->getOperand(0).getSubReg() ||
1444 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1445 !(MI->getNumOperands() & 1)) {
1446 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1447 llvm_unreachable(0);
1450 bool IsImpDef = true;
1451 SmallVector<unsigned, 4> RealSrcs;
1452 SmallSet<unsigned, 4> Seen;
1453 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1454 unsigned SrcReg = MI->getOperand(i).getReg();
1455 unsigned SubIdx = MI->getOperand(i+1).getImm();
1456 if (MI->getOperand(i).getSubReg() ||
1457 TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1458 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1459 llvm_unreachable(0);
1462 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
1463 if (DefMI->isImplicitDef()) {
1464 DefMI->eraseFromParent();
1469 // Remember COPY sources. These might be candidate for coalescing.
1470 if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
1471 RealSrcs.push_back(DefMI->getOperand(1).getReg());
1473 bool isKill = MI->getOperand(i).isKill();
1474 if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() ||
1475 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
1476 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
1477 MRI->getRegClass(SrcReg), SubIdx)) {
1478 // REG_SEQUENCE cannot have duplicated operands, add a copy.
1479 // Also add an copy if the source is live-in the block. We don't want
1480 // to end up with a partial-redef of a livein, e.g.
1482 // reg1051:10<def> =
1488 // LiveIntervalAnalysis won't like it.
1490 // If the REG_SEQUENCE doesn't kill its source, keeping live variables
1491 // correctly up to date becomes very difficult. Insert a copy.
1493 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1494 // might insert a COPY that uses SrcReg after is was killed.
1496 for (unsigned j = i + 2; j < e; j += 2)
1497 if (MI->getOperand(j).getReg() == SrcReg) {
1498 MI->getOperand(j).setIsKill();
1503 MachineBasicBlock::iterator InsertLoc = MI;
1504 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
1505 MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
1506 .addReg(DstReg, RegState::Define, SubIdx)
1507 .addReg(SrcReg, getKillRegState(isKill));
1508 MI->getOperand(i).setReg(0);
1510 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1511 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1515 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1516 unsigned SrcReg = MI->getOperand(i).getReg();
1517 if (!SrcReg) continue;
1518 unsigned SubIdx = MI->getOperand(i+1).getImm();
1519 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1523 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1524 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1525 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1526 MI->RemoveOperand(j);
1528 DEBUG(dbgs() << "Eliminated: " << *MI);
1529 MI->eraseFromParent();
1532 // Try coalescing some EXTRACT_SUBREG instructions. This can create
1533 // INSERT_SUBREG instructions that must have <undef> flags added by
1534 // LiveIntervalAnalysis, so only run it when LiveVariables is available.
1536 CoalesceExtSubRegs(RealSrcs, DstReg);
1539 RegSequences.clear();