1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
34 #include "llvm/CodeGen/LiveVariables.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstr.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/Analysis/AliasAnalysis.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/ADT/BitVector.h"
48 #include "llvm/ADT/DenseMap.h"
49 #include "llvm/ADT/SmallSet.h"
50 #include "llvm/ADT/Statistic.h"
51 #include "llvm/ADT/STLExtras.h"
54 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
55 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
56 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
57 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
58 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
59 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
60 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
63 class TwoAddressInstructionPass : public MachineFunctionPass {
65 const TargetInstrInfo *TII;
66 const TargetRegisterInfo *TRI;
67 const InstrItineraryData *InstrItins;
68 MachineRegisterInfo *MRI;
73 CodeGenOpt::Level OptLevel;
75 // The current basic block being processed.
76 MachineBasicBlock *MBB;
78 // DistanceMap - Keep track the distance of a MI from the start of the
79 // current basic block.
80 DenseMap<MachineInstr*, unsigned> DistanceMap;
82 // Set of already processed instructions in the current block.
83 SmallPtrSet<MachineInstr*, 8> Processed;
85 // SrcRegMap - A map from virtual registers to physical registers which are
86 // likely targets to be coalesced to due to copies from physical registers to
87 // virtual registers. e.g. v1024 = move r0.
88 DenseMap<unsigned, unsigned> SrcRegMap;
90 // DstRegMap - A map from virtual registers to physical registers which are
91 // likely targets to be coalesced to due to copies to physical registers from
92 // virtual registers. e.g. r1 = move v1024.
93 DenseMap<unsigned, unsigned> DstRegMap;
95 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
96 /// during the initial walk of the machine function.
97 SmallVector<MachineInstr*, 16> RegSequences;
99 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
100 MachineBasicBlock::iterator OldPos);
102 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
104 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
105 MachineInstr *MI, unsigned Dist);
107 bool commuteInstruction(MachineBasicBlock::iterator &mi,
108 unsigned RegB, unsigned RegC, unsigned Dist);
110 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
112 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
113 MachineBasicBlock::iterator &nmi,
114 unsigned RegA, unsigned RegB, unsigned Dist);
116 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
118 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
119 MachineBasicBlock::iterator &nmi,
121 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
122 MachineBasicBlock::iterator &nmi,
125 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
126 MachineBasicBlock::iterator &nmi,
127 unsigned SrcIdx, unsigned DstIdx,
130 void scanUses(unsigned DstReg);
132 void processCopy(MachineInstr *MI);
134 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
135 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
136 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
137 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
139 /// eliminateRegSequences - Eliminate REG_SEQUENCE instructions as part of
140 /// the de-ssa process. This replaces sources of REG_SEQUENCE as sub-register
141 /// references of the register defined by REG_SEQUENCE.
142 bool eliminateRegSequences();
145 static char ID; // Pass identification, replacement for typeid
146 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
147 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
150 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
151 AU.setPreservesCFG();
152 AU.addRequired<AliasAnalysis>();
153 AU.addPreserved<LiveVariables>();
154 AU.addPreserved<SlotIndexes>();
155 AU.addPreserved<LiveIntervals>();
156 AU.addPreservedID(MachineLoopInfoID);
157 AU.addPreservedID(MachineDominatorsID);
158 MachineFunctionPass::getAnalysisUsage(AU);
161 /// runOnMachineFunction - Pass entry point.
162 bool runOnMachineFunction(MachineFunction&);
164 } // end anonymous namespace
166 char TwoAddressInstructionPass::ID = 0;
167 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
168 "Two-Address instruction pass", false, false)
169 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
170 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
171 "Two-Address instruction pass", false, false)
173 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
175 /// sink3AddrInstruction - A two-address instruction has been converted to a
176 /// three-address instruction to avoid clobbering a register. Try to sink it
177 /// past the instruction that would kill the above mentioned register to reduce
178 /// register pressure.
179 bool TwoAddressInstructionPass::
180 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
181 MachineBasicBlock::iterator OldPos) {
182 // FIXME: Shouldn't we be trying to do this before we three-addressify the
183 // instruction? After this transformation is done, we no longer need
184 // the instruction to be in three-address form.
186 // Check if it's safe to move this instruction.
187 bool SeenStore = true; // Be conservative.
188 if (!MI->isSafeToMove(TII, AA, SeenStore))
192 SmallSet<unsigned, 4> UseRegs;
194 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
195 const MachineOperand &MO = MI->getOperand(i);
198 unsigned MOReg = MO.getReg();
201 if (MO.isUse() && MOReg != SavedReg)
202 UseRegs.insert(MO.getReg());
206 // Don't try to move it if it implicitly defines a register.
209 // For now, don't move any instructions that define multiple registers.
211 DefReg = MO.getReg();
214 // Find the instruction that kills SavedReg.
215 MachineInstr *KillMI = NULL;
216 for (MachineRegisterInfo::use_nodbg_iterator
217 UI = MRI->use_nodbg_begin(SavedReg),
218 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
219 MachineOperand &UseMO = UI.getOperand();
222 KillMI = UseMO.getParent();
226 // If we find the instruction that kills SavedReg, and it is in an
227 // appropriate location, we can try to sink the current instruction
229 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
230 KillMI == OldPos || KillMI->isTerminator())
233 // If any of the definitions are used by another instruction between the
234 // position and the kill use, then it's not safe to sink it.
236 // FIXME: This can be sped up if there is an easy way to query whether an
237 // instruction is before or after another instruction. Then we can use
238 // MachineRegisterInfo def / use instead.
239 MachineOperand *KillMO = NULL;
240 MachineBasicBlock::iterator KillPos = KillMI;
243 unsigned NumVisited = 0;
244 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
245 MachineInstr *OtherMI = I;
246 // DBG_VALUE cannot be counted against the limit.
247 if (OtherMI->isDebugValue())
249 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
252 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
253 MachineOperand &MO = OtherMI->getOperand(i);
256 unsigned MOReg = MO.getReg();
263 if (OtherMI == KillMI && MOReg == SavedReg)
264 // Save the operand that kills the register. We want to unset the kill
265 // marker if we can sink MI past it.
267 else if (UseRegs.count(MOReg))
268 // One of the uses is killed before the destination.
273 assert(KillMO && "Didn't find kill");
275 // Update kill and LV information.
276 KillMO->setIsKill(false);
277 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
278 KillMO->setIsKill(true);
281 LV->replaceKillInstruction(SavedReg, KillMI, MI);
283 // Move instruction to its destination.
285 MBB->insert(KillPos, MI);
294 /// noUseAfterLastDef - Return true if there are no intervening uses between the
295 /// last instruction in the MBB that defines the specified register and the
296 /// two-address instruction which is being processed. It also returns the last
297 /// def location by reference
298 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
301 unsigned LastUse = Dist;
302 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
303 E = MRI->reg_end(); I != E; ++I) {
304 MachineOperand &MO = I.getOperand();
305 MachineInstr *MI = MO.getParent();
306 if (MI->getParent() != MBB || MI->isDebugValue())
308 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
309 if (DI == DistanceMap.end())
311 if (MO.isUse() && DI->second < LastUse)
312 LastUse = DI->second;
313 if (MO.isDef() && DI->second > LastDef)
314 LastDef = DI->second;
317 return !(LastUse > LastDef && LastUse < Dist);
320 /// isCopyToReg - Return true if the specified MI is a copy instruction or
321 /// a extract_subreg instruction. It also returns the source and destination
322 /// registers and whether they are physical registers by reference.
323 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
324 unsigned &SrcReg, unsigned &DstReg,
325 bool &IsSrcPhys, bool &IsDstPhys) {
329 DstReg = MI.getOperand(0).getReg();
330 SrcReg = MI.getOperand(1).getReg();
331 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
332 DstReg = MI.getOperand(0).getReg();
333 SrcReg = MI.getOperand(2).getReg();
337 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
338 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
342 /// isKilled - Test if the given register value, which is used by the given
343 /// instruction, is killed by the given instruction. This looks through
344 /// coalescable copies to see if the original value is potentially not killed.
346 /// For example, in this code:
348 /// %reg1034 = copy %reg1024
349 /// %reg1035 = copy %reg1025<kill>
350 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
352 /// %reg1034 is not considered to be killed, since it is copied from a
353 /// register which is not killed. Treating it as not killed lets the
354 /// normal heuristics commute the (two-address) add, which lets
355 /// coalescing eliminate the extra copy.
357 static bool isKilled(MachineInstr &MI, unsigned Reg,
358 const MachineRegisterInfo *MRI,
359 const TargetInstrInfo *TII) {
360 MachineInstr *DefMI = &MI;
362 if (!DefMI->killsRegister(Reg))
364 if (TargetRegisterInfo::isPhysicalRegister(Reg))
366 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
367 // If there are multiple defs, we can't do a simple analysis, so just
368 // go with what the kill flag says.
369 if (llvm::next(Begin) != MRI->def_end())
372 bool IsSrcPhys, IsDstPhys;
373 unsigned SrcReg, DstReg;
374 // If the def is something other than a copy, then it isn't going to
375 // be coalesced, so follow the kill flag.
376 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
382 /// isTwoAddrUse - Return true if the specified MI uses the specified register
383 /// as a two-address use. If so, return the destination register by reference.
384 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
385 const MCInstrDesc &MCID = MI.getDesc();
386 unsigned NumOps = MI.isInlineAsm()
387 ? MI.getNumOperands() : MCID.getNumOperands();
388 for (unsigned i = 0; i != NumOps; ++i) {
389 const MachineOperand &MO = MI.getOperand(i);
390 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
393 if (MI.isRegTiedToDefOperand(i, &ti)) {
394 DstReg = MI.getOperand(ti).getReg();
401 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
402 /// use, return the use instruction if it's a copy or a two-address use.
404 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
405 MachineRegisterInfo *MRI,
406 const TargetInstrInfo *TII,
408 unsigned &DstReg, bool &IsDstPhys) {
409 if (!MRI->hasOneNonDBGUse(Reg))
410 // None or more than one use.
412 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
413 if (UseMI.getParent() != MBB)
417 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
422 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
429 /// getMappedReg - Return the physical register the specified virtual register
430 /// might be mapped to.
432 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
433 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
434 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
435 if (SI == RegMap.end())
439 if (TargetRegisterInfo::isPhysicalRegister(Reg))
444 /// regsAreCompatible - Return true if the two registers are equal or aliased.
447 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
452 return TRI->regsOverlap(RegA, RegB);
456 /// isProfitableToCommute - Return true if it's potentially profitable to commute
457 /// the two-address instruction that's being processed.
459 TwoAddressInstructionPass::
460 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
461 MachineInstr *MI, unsigned Dist) {
462 if (OptLevel == CodeGenOpt::None)
465 // Determine if it's profitable to commute this two address instruction. In
466 // general, we want no uses between this instruction and the definition of
467 // the two-address register.
469 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
470 // %reg1029<def> = MOV8rr %reg1028
471 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
472 // insert => %reg1030<def> = MOV8rr %reg1028
473 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
474 // In this case, it might not be possible to coalesce the second MOV8rr
475 // instruction if the first one is coalesced. So it would be profitable to
477 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
478 // %reg1029<def> = MOV8rr %reg1028
479 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
480 // insert => %reg1030<def> = MOV8rr %reg1029
481 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
483 if (!MI->killsRegister(regC))
486 // Ok, we have something like:
487 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
488 // let's see if it's worth commuting it.
490 // Look for situations like this:
491 // %reg1024<def> = MOV r1
492 // %reg1025<def> = MOV r0
493 // %reg1026<def> = ADD %reg1024, %reg1025
495 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
496 unsigned ToRegA = getMappedReg(regA, DstRegMap);
498 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
499 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
500 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
501 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
503 return !BComp && CComp;
506 // If there is a use of regC between its last def (could be livein) and this
507 // instruction, then bail.
508 unsigned LastDefC = 0;
509 if (!noUseAfterLastDef(regC, Dist, LastDefC))
512 // If there is a use of regB between its last def (could be livein) and this
513 // instruction, then go ahead and make this transformation.
514 unsigned LastDefB = 0;
515 if (!noUseAfterLastDef(regB, Dist, LastDefB))
518 // Since there are no intervening uses for both registers, then commute
519 // if the def of regC is closer. Its live interval is shorter.
520 return LastDefB && LastDefC && LastDefC > LastDefB;
523 /// commuteInstruction - Commute a two-address instruction and update the basic
524 /// block, distance map, and live variables if needed. Return true if it is
526 bool TwoAddressInstructionPass::
527 commuteInstruction(MachineBasicBlock::iterator &mi,
528 unsigned RegB, unsigned RegC, unsigned Dist) {
529 MachineInstr *MI = mi;
530 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
531 MachineInstr *NewMI = TII->commuteInstruction(MI);
534 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
538 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
539 // If the instruction changed to commute it, update livevar.
542 // Update live variables
543 LV->replaceKillInstruction(RegC, MI, NewMI);
545 Indexes->replaceMachineInstrInMaps(MI, NewMI);
547 MBB->insert(mi, NewMI); // Insert the new inst
548 MBB->erase(mi); // Nuke the old inst.
550 DistanceMap.insert(std::make_pair(NewMI, Dist));
553 // Update source register map.
554 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
556 unsigned RegA = MI->getOperand(0).getReg();
557 SrcRegMap[RegA] = FromRegC;
563 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
564 /// given 2-address instruction to a 3-address one.
566 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
567 // Look for situations like this:
568 // %reg1024<def> = MOV r1
569 // %reg1025<def> = MOV r0
570 // %reg1026<def> = ADD %reg1024, %reg1025
572 // Turn ADD into a 3-address instruction to avoid a copy.
573 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
576 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
577 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
580 /// convertInstTo3Addr - Convert the specified two-address instruction into a
581 /// three address one. Return true if this transformation was successful.
583 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
584 MachineBasicBlock::iterator &nmi,
585 unsigned RegA, unsigned RegB,
587 // FIXME: Why does convertToThreeAddress() need an iterator reference?
588 MachineFunction::iterator MFI = MBB;
589 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
590 assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
592 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
593 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
597 Indexes->replaceMachineInstrInMaps(mi, NewMI);
599 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
600 // FIXME: Temporary workaround. If the new instruction doesn't
601 // uses RegB, convertToThreeAddress must have created more
602 // then one instruction.
603 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
605 MBB->erase(mi); // Nuke the old inst.
608 DistanceMap.insert(std::make_pair(NewMI, Dist));
610 nmi = llvm::next(mi);
613 // Update source and destination register maps.
614 SrcRegMap.erase(RegA);
615 DstRegMap.erase(RegB);
622 /// scanUses - Scan forward recursively for only uses, update maps if the use
623 /// is a copy or a two-address instruction.
625 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
626 SmallVector<unsigned, 4> VirtRegPairs;
630 unsigned Reg = DstReg;
631 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
632 NewReg, IsDstPhys)) {
633 if (IsCopy && !Processed.insert(UseMI))
636 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
637 if (DI != DistanceMap.end())
638 // Earlier in the same MBB.Reached via a back edge.
642 VirtRegPairs.push_back(NewReg);
645 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
647 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
648 VirtRegPairs.push_back(NewReg);
652 if (!VirtRegPairs.empty()) {
653 unsigned ToReg = VirtRegPairs.back();
654 VirtRegPairs.pop_back();
655 while (!VirtRegPairs.empty()) {
656 unsigned FromReg = VirtRegPairs.back();
657 VirtRegPairs.pop_back();
658 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
660 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
663 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
665 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
669 /// processCopy - If the specified instruction is not yet processed, process it
670 /// if it's a copy. For a copy instruction, we find the physical registers the
671 /// source and destination registers might be mapped to. These are kept in
672 /// point-to maps used to determine future optimizations. e.g.
675 /// v1026 = add v1024, v1025
677 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
678 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
679 /// potentially joined with r1 on the output side. It's worthwhile to commute
680 /// 'add' to eliminate a copy.
681 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
682 if (Processed.count(MI))
685 bool IsSrcPhys, IsDstPhys;
686 unsigned SrcReg, DstReg;
687 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
690 if (IsDstPhys && !IsSrcPhys)
691 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
692 else if (!IsDstPhys && IsSrcPhys) {
693 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
695 assert(SrcRegMap[DstReg] == SrcReg &&
696 "Can't map to two src physical registers!");
701 Processed.insert(MI);
705 /// rescheduleMIBelowKill - If there is one more local instruction that reads
706 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
707 /// instruction in order to eliminate the need for the copy.
708 bool TwoAddressInstructionPass::
709 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
710 MachineBasicBlock::iterator &nmi,
712 // Bail immediately if we don't have LV available. We use it to find kills
717 MachineInstr *MI = &*mi;
718 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
719 if (DI == DistanceMap.end())
720 // Must be created from unfolded load. Don't waste time trying this.
723 MachineInstr *KillMI = LV->getVarInfo(Reg).findKill(MBB);
724 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
725 // Don't mess with copies, they may be coalesced later.
728 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
729 KillMI->isBranch() || KillMI->isTerminator())
730 // Don't move pass calls, etc.
734 if (isTwoAddrUse(*KillMI, Reg, DstReg))
737 bool SeenStore = true;
738 if (!MI->isSafeToMove(TII, AA, SeenStore))
741 if (TII->getInstrLatency(InstrItins, MI) > 1)
742 // FIXME: Needs more sophisticated heuristics.
745 SmallSet<unsigned, 2> Uses;
746 SmallSet<unsigned, 2> Kills;
747 SmallSet<unsigned, 2> Defs;
748 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
749 const MachineOperand &MO = MI->getOperand(i);
752 unsigned MOReg = MO.getReg();
759 if (MO.isKill() && MOReg != Reg)
764 // Move the copies connected to MI down as well.
765 MachineBasicBlock::iterator From = MI;
766 MachineBasicBlock::iterator To = llvm::next(From);
767 while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) {
768 Defs.insert(To->getOperand(0).getReg());
772 // Check if the reschedule will not break depedencies.
773 unsigned NumVisited = 0;
774 MachineBasicBlock::iterator KillPos = KillMI;
776 for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) {
777 MachineInstr *OtherMI = I;
778 // DBG_VALUE cannot be counted against the limit.
779 if (OtherMI->isDebugValue())
781 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
784 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
785 OtherMI->isBranch() || OtherMI->isTerminator())
786 // Don't move pass calls, etc.
788 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
789 const MachineOperand &MO = OtherMI->getOperand(i);
792 unsigned MOReg = MO.getReg();
796 if (Uses.count(MOReg))
797 // Physical register use would be clobbered.
799 if (!MO.isDead() && Defs.count(MOReg))
800 // May clobber a physical register def.
801 // FIXME: This may be too conservative. It's ok if the instruction
802 // is sunken completely below the use.
805 if (Defs.count(MOReg))
808 ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg)))
809 // Don't want to extend other live ranges and update kills.
811 if (MOReg == Reg && !MO.isKill())
812 // We can't schedule across a use of the register in question.
814 // Ensure that if this is register in question, its the kill we expect.
815 assert((MOReg != Reg || OtherMI == KillMI) &&
816 "Found multiple kills of a register in a basic block");
821 // Move debug info as well.
822 while (From != MBB->begin() && llvm::prior(From)->isDebugValue())
825 // Copies following MI may have been moved as well.
827 MBB->splice(KillPos, MBB, From, To);
828 DistanceMap.erase(DI);
830 // Update live variables
831 LV->removeVirtualRegisterKilled(Reg, KillMI);
832 LV->addVirtualRegisterKilled(Reg, MI);
836 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
840 /// isDefTooClose - Return true if the re-scheduling will put the given
841 /// instruction too close to the defs of its register dependencies.
842 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
844 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
845 DE = MRI->def_end(); DI != DE; ++DI) {
846 MachineInstr *DefMI = &*DI;
847 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
850 return true; // MI is defining something KillMI uses
851 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
852 if (DDI == DistanceMap.end())
853 return true; // Below MI
854 unsigned DefDist = DDI->second;
855 assert(Dist > DefDist && "Visited def already?");
856 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
862 /// rescheduleKillAboveMI - If there is one more local instruction that reads
863 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
864 /// current two-address instruction in order to eliminate the need for the
866 bool TwoAddressInstructionPass::
867 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
868 MachineBasicBlock::iterator &nmi,
870 // Bail immediately if we don't have LV available. We use it to find kills
875 MachineInstr *MI = &*mi;
876 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
877 if (DI == DistanceMap.end())
878 // Must be created from unfolded load. Don't waste time trying this.
881 MachineInstr *KillMI = LV->getVarInfo(Reg).findKill(MBB);
882 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
883 // Don't mess with copies, they may be coalesced later.
887 if (isTwoAddrUse(*KillMI, Reg, DstReg))
890 bool SeenStore = true;
891 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
894 SmallSet<unsigned, 2> Uses;
895 SmallSet<unsigned, 2> Kills;
896 SmallSet<unsigned, 2> Defs;
897 SmallSet<unsigned, 2> LiveDefs;
898 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
899 const MachineOperand &MO = KillMI->getOperand(i);
902 unsigned MOReg = MO.getReg();
906 if (isDefTooClose(MOReg, DI->second, MI))
908 if (MOReg == Reg && !MO.isKill())
911 if (MO.isKill() && MOReg != Reg)
913 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
916 LiveDefs.insert(MOReg);
920 // Check if the reschedule will not break depedencies.
921 unsigned NumVisited = 0;
922 MachineBasicBlock::iterator KillPos = KillMI;
923 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
924 MachineInstr *OtherMI = I;
925 // DBG_VALUE cannot be counted against the limit.
926 if (OtherMI->isDebugValue())
928 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
931 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
932 OtherMI->isBranch() || OtherMI->isTerminator())
933 // Don't move pass calls, etc.
935 SmallVector<unsigned, 2> OtherDefs;
936 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
937 const MachineOperand &MO = OtherMI->getOperand(i);
940 unsigned MOReg = MO.getReg();
944 if (Defs.count(MOReg))
945 // Moving KillMI can clobber the physical register if the def has
948 if (Kills.count(MOReg))
949 // Don't want to extend other live ranges and update kills.
951 if (OtherMI != MI && MOReg == Reg && !MO.isKill())
952 // We can't schedule across a use of the register in question.
955 OtherDefs.push_back(MOReg);
959 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
960 unsigned MOReg = OtherDefs[i];
961 if (Uses.count(MOReg))
963 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
964 LiveDefs.count(MOReg))
966 // Physical register def is seen.
971 // Move the old kill above MI, don't forget to move debug info as well.
972 MachineBasicBlock::iterator InsertPos = mi;
973 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
975 MachineBasicBlock::iterator From = KillMI;
976 MachineBasicBlock::iterator To = llvm::next(From);
977 while (llvm::prior(From)->isDebugValue())
979 MBB->splice(InsertPos, MBB, From, To);
981 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
982 DistanceMap.erase(DI);
984 // Update live variables
985 LV->removeVirtualRegisterKilled(Reg, KillMI);
986 LV->addVirtualRegisterKilled(Reg, MI);
988 LIS->handleMove(KillMI);
990 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
994 /// tryInstructionTransform - For the case where an instruction has a single
995 /// pair of tied register operands, attempt some transformations that may
996 /// either eliminate the tied operands or improve the opportunities for
997 /// coalescing away the register copy. Returns true if no copy needs to be
998 /// inserted to untie mi's operands (either because they were untied, or
999 /// because mi was rescheduled, and will be visited again later).
1000 bool TwoAddressInstructionPass::
1001 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1002 MachineBasicBlock::iterator &nmi,
1003 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
1004 if (OptLevel == CodeGenOpt::None)
1007 MachineInstr &MI = *mi;
1008 unsigned regA = MI.getOperand(DstIdx).getReg();
1009 unsigned regB = MI.getOperand(SrcIdx).getReg();
1011 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1012 "cannot make instruction into two-address form");
1013 bool regBKilled = isKilled(MI, regB, MRI, TII);
1015 if (TargetRegisterInfo::isVirtualRegister(regA))
1018 // Check if it is profitable to commute the operands.
1019 unsigned SrcOp1, SrcOp2;
1021 unsigned regCIdx = ~0U;
1022 bool TryCommute = false;
1023 bool AggressiveCommute = false;
1024 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1025 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1026 if (SrcIdx == SrcOp1)
1028 else if (SrcIdx == SrcOp2)
1031 if (regCIdx != ~0U) {
1032 regC = MI.getOperand(regCIdx).getReg();
1033 if (!regBKilled && isKilled(MI, regC, MRI, TII))
1034 // If C dies but B does not, swap the B and C operands.
1035 // This makes the live ranges of A and C joinable.
1037 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1039 AggressiveCommute = true;
1044 // If it's profitable to commute, try to do so.
1045 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1047 if (AggressiveCommute)
1052 // If there is one more use of regB later in the same MBB, consider
1053 // re-schedule this MI below it.
1054 if (rescheduleMIBelowKill(mi, nmi, regB)) {
1059 if (MI.isConvertibleTo3Addr()) {
1060 // This instruction is potentially convertible to a true
1061 // three-address instruction. Check if it is profitable.
1062 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1063 // Try to convert it.
1064 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1065 ++NumConvertedTo3Addr;
1066 return true; // Done with this instruction.
1071 // If there is one more use of regB later in the same MBB, consider
1072 // re-schedule it before this MI if it's legal.
1073 if (rescheduleKillAboveMI(mi, nmi, regB)) {
1078 // If this is an instruction with a load folded into it, try unfolding
1079 // the load, e.g. avoid this:
1081 // addq (%rax), %rcx
1082 // in favor of this:
1083 // movq (%rax), %rcx
1085 // because it's preferable to schedule a load than a register copy.
1086 if (MI.mayLoad() && !regBKilled) {
1087 // Determine if a load can be unfolded.
1088 unsigned LoadRegIndex;
1090 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1091 /*UnfoldLoad=*/true,
1092 /*UnfoldStore=*/false,
1095 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1096 if (UnfoldMCID.getNumDefs() == 1) {
1098 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1099 const TargetRegisterClass *RC =
1100 TRI->getAllocatableClass(
1101 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1102 unsigned Reg = MRI->createVirtualRegister(RC);
1103 SmallVector<MachineInstr *, 2> NewMIs;
1104 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1105 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1107 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1110 assert(NewMIs.size() == 2 &&
1111 "Unfolded a load into multiple instructions!");
1112 // The load was previously folded, so this is the only use.
1113 NewMIs[1]->addRegisterKilled(Reg, TRI);
1115 // Tentatively insert the instructions into the block so that they
1116 // look "normal" to the transformation logic.
1117 MBB->insert(mi, NewMIs[0]);
1118 MBB->insert(mi, NewMIs[1]);
1120 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1121 << "2addr: NEW INST: " << *NewMIs[1]);
1123 // Transform the instruction, now that it no longer has a load.
1124 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1125 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1126 MachineBasicBlock::iterator NewMI = NewMIs[1];
1127 bool TransformSuccess =
1128 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist);
1129 if (TransformSuccess ||
1130 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1131 // Success, or at least we made an improvement. Keep the unfolded
1132 // instructions and discard the original.
1134 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1135 MachineOperand &MO = MI.getOperand(i);
1137 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1140 if (NewMIs[0]->killsRegister(MO.getReg()))
1141 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1143 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1144 "Kill missing after load unfold!");
1145 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1148 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1149 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1150 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1152 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1153 "Dead flag missing after load unfold!");
1154 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1159 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1161 MI.eraseFromParent();
1163 if (TransformSuccess)
1166 // Transforming didn't eliminate the tie and didn't lead to an
1167 // improvement. Clean up the unfolded instructions and keep the
1169 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1170 NewMIs[0]->eraseFromParent();
1171 NewMIs[1]->eraseFromParent();
1180 // Collect tied operands of MI that need to be handled.
1181 // Rewrite trivial cases immediately.
1182 // Return true if any tied operands where found, including the trivial ones.
1183 bool TwoAddressInstructionPass::
1184 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1185 const MCInstrDesc &MCID = MI->getDesc();
1186 bool AnyOps = false;
1187 unsigned NumOps = MI->getNumOperands();
1189 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1190 unsigned DstIdx = 0;
1191 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1194 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1195 MachineOperand &DstMO = MI->getOperand(DstIdx);
1196 unsigned SrcReg = SrcMO.getReg();
1197 unsigned DstReg = DstMO.getReg();
1198 // Tied constraint already satisfied?
1199 if (SrcReg == DstReg)
1202 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1204 // Deal with <undef> uses immediately - simply rewrite the src operand.
1205 if (SrcMO.isUndef()) {
1206 // Constrain the DstReg register class if required.
1207 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1208 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1210 MRI->constrainRegClass(DstReg, RC);
1211 SrcMO.setReg(DstReg);
1212 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1215 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1220 // Process a list of tied MI operands that all use the same source register.
1221 // The tied pairs are of the form (SrcIdx, DstIdx).
1223 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1224 TiedPairList &TiedPairs,
1226 bool IsEarlyClobber = false;
1227 bool RemovedKillFlag = false;
1228 bool AllUsesCopied = true;
1229 unsigned LastCopiedReg = 0;
1231 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1232 unsigned SrcIdx = TiedPairs[tpi].first;
1233 unsigned DstIdx = TiedPairs[tpi].second;
1235 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1236 unsigned RegA = DstMO.getReg();
1237 IsEarlyClobber |= DstMO.isEarlyClobber();
1239 // Grab RegB from the instruction because it may have changed if the
1240 // instruction was commuted.
1241 RegB = MI->getOperand(SrcIdx).getReg();
1244 // The register is tied to multiple destinations (or else we would
1245 // not have continued this far), but this use of the register
1246 // already matches the tied destination. Leave it.
1247 AllUsesCopied = false;
1250 LastCopiedReg = RegA;
1252 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1253 "cannot make instruction into two-address form");
1256 // First, verify that we don't have a use of "a" in the instruction
1257 // (a = b + a for example) because our transformation will not
1258 // work. This should never occur because we are in SSA form.
1259 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1260 assert(i == DstIdx ||
1261 !MI->getOperand(i).isReg() ||
1262 MI->getOperand(i).getReg() != RegA);
1266 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1267 TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
1269 // Update DistanceMap.
1270 MachineBasicBlock::iterator PrevMI = MI;
1272 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1273 DistanceMap[MI] = ++Dist;
1277 CopyIdx = Indexes->insertMachineInstrInMaps(PrevMI).getRegSlot();
1279 DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
1281 MachineOperand &MO = MI->getOperand(SrcIdx);
1282 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1283 "inconsistent operand info for 2-reg pass");
1285 MO.setIsKill(false);
1286 RemovedKillFlag = true;
1289 // Make sure regA is a legal regclass for the SrcIdx operand.
1290 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1291 TargetRegisterInfo::isVirtualRegister(RegB))
1292 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
1296 // Propagate SrcRegMap.
1297 SrcRegMap[RegA] = RegB;
1301 if (AllUsesCopied) {
1302 if (!IsEarlyClobber) {
1303 // Replace other (un-tied) uses of regB with LastCopiedReg.
1304 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1305 MachineOperand &MO = MI->getOperand(i);
1306 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1308 MO.setIsKill(false);
1309 RemovedKillFlag = true;
1311 MO.setReg(LastCopiedReg);
1316 // Update live variables for regB.
1317 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1318 MachineBasicBlock::iterator PrevMI = MI;
1320 LV->addVirtualRegisterKilled(RegB, PrevMI);
1323 } else if (RemovedKillFlag) {
1324 // Some tied uses of regB matched their destination registers, so
1325 // regB is still used in this instruction, but a kill flag was
1326 // removed from a different tied use of regB, so now we need to add
1327 // a kill flag to one of the remaining uses of regB.
1328 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1329 MachineOperand &MO = MI->getOperand(i);
1330 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1338 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1340 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1342 const TargetMachine &TM = MF->getTarget();
1343 MRI = &MF->getRegInfo();
1344 TII = TM.getInstrInfo();
1345 TRI = TM.getRegisterInfo();
1346 InstrItins = TM.getInstrItineraryData();
1347 Indexes = getAnalysisIfAvailable<SlotIndexes>();
1348 LV = getAnalysisIfAvailable<LiveVariables>();
1349 LIS = getAnalysisIfAvailable<LiveIntervals>();
1350 AA = &getAnalysis<AliasAnalysis>();
1351 OptLevel = TM.getOptLevel();
1353 bool MadeChange = false;
1355 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1356 DEBUG(dbgs() << "********** Function: "
1357 << MF->getName() << '\n');
1359 // This pass takes the function out of SSA form.
1362 TiedOperandMap TiedOperands;
1363 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1364 MBBI != MBBE; ++MBBI) {
1367 DistanceMap.clear();
1371 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1373 MachineBasicBlock::iterator nmi = llvm::next(mi);
1374 if (mi->isDebugValue()) {
1379 // Remember REG_SEQUENCE instructions, we'll deal with them later.
1380 if (mi->isRegSequence())
1381 RegSequences.push_back(&*mi);
1383 DistanceMap.insert(std::make_pair(mi, ++Dist));
1387 // First scan through all the tied register uses in this instruction
1388 // and record a list of pairs of tied operands for each register.
1389 if (!collectTiedOperands(mi, TiedOperands)) {
1394 ++NumTwoAddressInstrs;
1396 DEBUG(dbgs() << '\t' << *mi);
1398 // If the instruction has a single pair of tied operands, try some
1399 // transformations that may either eliminate the tied operands or
1400 // improve the opportunities for coalescing away the register copy.
1401 if (TiedOperands.size() == 1) {
1402 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs
1403 = TiedOperands.begin()->second;
1404 if (TiedPairs.size() == 1) {
1405 unsigned SrcIdx = TiedPairs[0].first;
1406 unsigned DstIdx = TiedPairs[0].second;
1407 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1408 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1409 if (SrcReg != DstReg &&
1410 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist)) {
1411 // The tied operands have been eliminated or shifted further down the
1412 // block to ease elimination. Continue processing with 'nmi'.
1413 TiedOperands.clear();
1420 // Now iterate over the information collected above.
1421 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1422 OE = TiedOperands.end(); OI != OE; ++OI) {
1423 processTiedPairs(mi, OI->second, Dist);
1424 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1427 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1428 if (mi->isInsertSubreg()) {
1429 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1430 // To %reg:subidx = COPY %subreg
1431 unsigned SubIdx = mi->getOperand(3).getImm();
1432 mi->RemoveOperand(3);
1433 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1434 mi->getOperand(0).setSubReg(SubIdx);
1435 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1436 mi->RemoveOperand(1);
1437 mi->setDesc(TII->get(TargetOpcode::COPY));
1438 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1441 // Clear TiedOperands here instead of at the top of the loop
1442 // since most instructions do not have tied operands.
1443 TiedOperands.clear();
1448 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1449 // SSA form. It's now safe to de-SSA.
1450 MadeChange |= eliminateRegSequences();
1455 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1456 unsigned DstReg, unsigned SubIdx,
1457 MachineRegisterInfo *MRI,
1458 const TargetRegisterInfo &TRI) {
1459 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1460 RE = MRI->reg_end(); RI != RE; ) {
1461 MachineOperand &MO = RI.getOperand();
1463 MO.substVirtReg(DstReg, SubIdx, TRI);
1467 // Find the first def of Reg, assuming they are all in the same basic block.
1468 static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) {
1469 SmallPtrSet<MachineInstr*, 8> Defs;
1470 MachineInstr *First = 0;
1471 for (MachineRegisterInfo::def_iterator RI = MRI->def_begin(Reg);
1472 MachineInstr *MI = RI.skipInstruction(); Defs.insert(MI))
1477 MachineBasicBlock *MBB = First->getParent();
1478 MachineBasicBlock::iterator A = First, B = First;
1482 if (A != MBB->begin()) {
1485 if (Defs.erase(A)) First = A;
1487 if (B != MBB->end()) {
1492 } while (Moving && !Defs.empty());
1493 assert(Defs.empty() && "Instructions outside basic block!");
1497 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
1498 MachineRegisterInfo *MRI) {
1499 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
1500 UE = MRI->use_end(); UI != UE; ++UI) {
1501 MachineInstr *UseMI = &*UI;
1502 if (UseMI != RegSeq && UseMI->isRegSequence())
1508 /// eliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1509 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1510 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1512 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1513 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1515 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1516 bool TwoAddressInstructionPass::eliminateRegSequences() {
1517 if (RegSequences.empty())
1520 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1521 MachineInstr *MI = RegSequences[i];
1522 unsigned DstReg = MI->getOperand(0).getReg();
1523 if (MI->getOperand(0).getSubReg() ||
1524 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1525 !(MI->getNumOperands() & 1)) {
1526 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1527 llvm_unreachable(0);
1530 bool IsImpDef = true;
1531 SmallVector<unsigned, 4> RealSrcs;
1532 SmallSet<unsigned, 4> Seen;
1533 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1534 // Nothing needs to be inserted for <undef> operands.
1535 if (MI->getOperand(i).isUndef()) {
1536 MI->getOperand(i).setReg(0);
1539 unsigned SrcReg = MI->getOperand(i).getReg();
1540 unsigned SrcSubIdx = MI->getOperand(i).getSubReg();
1541 unsigned SubIdx = MI->getOperand(i+1).getImm();
1542 // DefMI of NULL means the value does not have a vreg in this block
1543 // i.e., its a physical register or a subreg.
1544 // In either case we force a copy to be generated.
1545 MachineInstr *DefMI = NULL;
1546 if (!MI->getOperand(i).getSubReg() &&
1547 !TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1548 DefMI = MRI->getUniqueVRegDef(SrcReg);
1551 if (DefMI && DefMI->isImplicitDef()) {
1552 DefMI->eraseFromParent();
1557 // Remember COPY sources. These might be candidate for coalescing.
1558 if (DefMI && DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
1559 RealSrcs.push_back(DefMI->getOperand(1).getReg());
1561 bool isKill = MI->getOperand(i).isKill();
1562 if (!DefMI || !Seen.insert(SrcReg) ||
1563 MI->getParent() != DefMI->getParent() ||
1564 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
1565 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
1566 MRI->getRegClass(SrcReg), SubIdx)) {
1567 // REG_SEQUENCE cannot have duplicated operands, add a copy.
1568 // Also add an copy if the source is live-in the block. We don't want
1569 // to end up with a partial-redef of a livein, e.g.
1571 // reg1051:10<def> =
1577 // LiveIntervalAnalysis won't like it.
1579 // If the REG_SEQUENCE doesn't kill its source, keeping live variables
1580 // correctly up to date becomes very difficult. Insert a copy.
1582 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1583 // might insert a COPY that uses SrcReg after is was killed.
1585 for (unsigned j = i + 2; j < e; j += 2)
1586 if (MI->getOperand(j).getReg() == SrcReg) {
1587 MI->getOperand(j).setIsKill();
1592 MachineBasicBlock::iterator InsertLoc = MI;
1593 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
1594 MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
1595 .addReg(DstReg, RegState::Define, SubIdx)
1596 .addReg(SrcReg, getKillRegState(isKill), SrcSubIdx);
1597 MI->getOperand(i).setReg(0);
1598 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1599 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1600 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1604 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1605 unsigned SrcReg = MI->getOperand(i).getReg();
1606 if (!SrcReg) continue;
1607 unsigned SubIdx = MI->getOperand(i+1).getImm();
1608 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1611 // Set <def,undef> flags on the first DstReg def in the basic block.
1612 // It marks the beginning of the live range. All the other defs are
1613 // read-modify-write.
1614 if (MachineInstr *Def = findFirstDef(DstReg, MRI)) {
1615 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
1616 MachineOperand &MO = Def->getOperand(i);
1617 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1620 DEBUG(dbgs() << "First def: " << *Def);
1624 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1625 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1626 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1627 MI->RemoveOperand(j);
1629 DEBUG(dbgs() << "Eliminated: " << *MI);
1630 MI->eraseFromParent();
1634 RegSequences.clear();