1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveVariables.h"
39 #include "llvm/CodeGen/MachineFunctionPass.h"
40 #include "llvm/CodeGen/MachineInstr.h"
41 #include "llvm/CodeGen/MachineInstrBuilder.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/MC/MCInstrItineraries.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetMachine.h"
50 #include "llvm/Target/TargetRegisterInfo.h"
51 #include "llvm/Target/TargetSubtargetInfo.h"
54 #define DEBUG_TYPE "twoaddrinstr"
56 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
57 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
58 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
59 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
60 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
61 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
62 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
64 // Temporary flag to disable rescheduling.
66 EnableRescheduling("twoaddr-reschedule",
67 cl::desc("Coalesce copies by rescheduling (default=true)"),
68 cl::init(true), cl::Hidden);
71 class TwoAddressInstructionPass : public MachineFunctionPass {
73 const TargetInstrInfo *TII;
74 const TargetRegisterInfo *TRI;
75 const InstrItineraryData *InstrItins;
76 MachineRegisterInfo *MRI;
80 CodeGenOpt::Level OptLevel;
82 // The current basic block being processed.
83 MachineBasicBlock *MBB;
85 // DistanceMap - Keep track the distance of a MI from the start of the
86 // current basic block.
87 DenseMap<MachineInstr*, unsigned> DistanceMap;
89 // Set of already processed instructions in the current block.
90 SmallPtrSet<MachineInstr*, 8> Processed;
92 // SrcRegMap - A map from virtual registers to physical registers which are
93 // likely targets to be coalesced to due to copies from physical registers to
94 // virtual registers. e.g. v1024 = move r0.
95 DenseMap<unsigned, unsigned> SrcRegMap;
97 // DstRegMap - A map from virtual registers to physical registers which are
98 // likely targets to be coalesced to due to copies to physical registers from
99 // virtual registers. e.g. r1 = move v1024.
100 DenseMap<unsigned, unsigned> DstRegMap;
102 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
103 MachineBasicBlock::iterator OldPos);
105 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
107 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
108 MachineInstr *MI, unsigned Dist);
110 bool commuteInstruction(MachineBasicBlock::iterator &mi,
111 unsigned RegB, unsigned RegC, unsigned Dist);
113 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
115 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
116 MachineBasicBlock::iterator &nmi,
117 unsigned RegA, unsigned RegB, unsigned Dist);
119 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
121 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
122 MachineBasicBlock::iterator &nmi,
124 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
125 MachineBasicBlock::iterator &nmi,
128 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
129 MachineBasicBlock::iterator &nmi,
130 unsigned SrcIdx, unsigned DstIdx,
131 unsigned Dist, bool shouldOnlyCommute);
133 void scanUses(unsigned DstReg);
135 void processCopy(MachineInstr *MI);
137 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
138 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
139 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
140 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
141 void eliminateRegSequence(MachineBasicBlock::iterator&);
144 static char ID; // Pass identification, replacement for typeid
145 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
146 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
149 void getAnalysisUsage(AnalysisUsage &AU) const override {
150 AU.setPreservesCFG();
151 AU.addRequired<AliasAnalysis>();
152 AU.addPreserved<LiveVariables>();
153 AU.addPreserved<SlotIndexes>();
154 AU.addPreserved<LiveIntervals>();
155 AU.addPreservedID(MachineLoopInfoID);
156 AU.addPreservedID(MachineDominatorsID);
157 MachineFunctionPass::getAnalysisUsage(AU);
160 /// runOnMachineFunction - Pass entry point.
161 bool runOnMachineFunction(MachineFunction&) override;
163 } // end anonymous namespace
165 char TwoAddressInstructionPass::ID = 0;
166 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
167 "Two-Address instruction pass", false, false)
168 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
169 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
170 "Two-Address instruction pass", false, false)
172 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
174 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
176 /// sink3AddrInstruction - A two-address instruction has been converted to a
177 /// three-address instruction to avoid clobbering a register. Try to sink it
178 /// past the instruction that would kill the above mentioned register to reduce
179 /// register pressure.
180 bool TwoAddressInstructionPass::
181 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
182 MachineBasicBlock::iterator OldPos) {
183 // FIXME: Shouldn't we be trying to do this before we three-addressify the
184 // instruction? After this transformation is done, we no longer need
185 // the instruction to be in three-address form.
187 // Check if it's safe to move this instruction.
188 bool SeenStore = true; // Be conservative.
189 if (!MI->isSafeToMove(TII, AA, SeenStore))
193 SmallSet<unsigned, 4> UseRegs;
195 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
196 const MachineOperand &MO = MI->getOperand(i);
199 unsigned MOReg = MO.getReg();
202 if (MO.isUse() && MOReg != SavedReg)
203 UseRegs.insert(MO.getReg());
207 // Don't try to move it if it implicitly defines a register.
210 // For now, don't move any instructions that define multiple registers.
212 DefReg = MO.getReg();
215 // Find the instruction that kills SavedReg.
216 MachineInstr *KillMI = nullptr;
218 LiveInterval &LI = LIS->getInterval(SavedReg);
219 assert(LI.end() != LI.begin() &&
220 "Reg should not have empty live interval.");
222 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
223 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
224 if (I != LI.end() && I->start < MBBEndIdx)
228 KillMI = LIS->getInstructionFromIndex(I->end);
231 for (MachineRegisterInfo::use_nodbg_iterator
232 UI = MRI->use_nodbg_begin(SavedReg),
233 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
234 MachineOperand &UseMO = *UI;
237 KillMI = UseMO.getParent();
242 // If we find the instruction that kills SavedReg, and it is in an
243 // appropriate location, we can try to sink the current instruction
245 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
246 KillMI == OldPos || KillMI->isTerminator())
249 // If any of the definitions are used by another instruction between the
250 // position and the kill use, then it's not safe to sink it.
252 // FIXME: This can be sped up if there is an easy way to query whether an
253 // instruction is before or after another instruction. Then we can use
254 // MachineRegisterInfo def / use instead.
255 MachineOperand *KillMO = nullptr;
256 MachineBasicBlock::iterator KillPos = KillMI;
259 unsigned NumVisited = 0;
260 for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) {
261 MachineInstr *OtherMI = I;
262 // DBG_VALUE cannot be counted against the limit.
263 if (OtherMI->isDebugValue())
265 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
268 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
269 MachineOperand &MO = OtherMI->getOperand(i);
272 unsigned MOReg = MO.getReg();
278 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
279 if (OtherMI == KillMI && MOReg == SavedReg)
280 // Save the operand that kills the register. We want to unset the kill
281 // marker if we can sink MI past it.
283 else if (UseRegs.count(MOReg))
284 // One of the uses is killed before the destination.
289 assert(KillMO && "Didn't find kill");
292 // Update kill and LV information.
293 KillMO->setIsKill(false);
294 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
295 KillMO->setIsKill(true);
298 LV->replaceKillInstruction(SavedReg, KillMI, MI);
301 // Move instruction to its destination.
303 MBB->insert(KillPos, MI);
312 /// noUseAfterLastDef - Return true if there are no intervening uses between the
313 /// last instruction in the MBB that defines the specified register and the
314 /// two-address instruction which is being processed. It also returns the last
315 /// def location by reference
316 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
319 unsigned LastUse = Dist;
320 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
321 MachineInstr *MI = MO.getParent();
322 if (MI->getParent() != MBB || MI->isDebugValue())
324 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
325 if (DI == DistanceMap.end())
327 if (MO.isUse() && DI->second < LastUse)
328 LastUse = DI->second;
329 if (MO.isDef() && DI->second > LastDef)
330 LastDef = DI->second;
333 return !(LastUse > LastDef && LastUse < Dist);
336 /// isCopyToReg - Return true if the specified MI is a copy instruction or
337 /// a extract_subreg instruction. It also returns the source and destination
338 /// registers and whether they are physical registers by reference.
339 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
340 unsigned &SrcReg, unsigned &DstReg,
341 bool &IsSrcPhys, bool &IsDstPhys) {
345 DstReg = MI.getOperand(0).getReg();
346 SrcReg = MI.getOperand(1).getReg();
347 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
348 DstReg = MI.getOperand(0).getReg();
349 SrcReg = MI.getOperand(2).getReg();
353 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
354 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
358 /// isPLainlyKilled - Test if the given register value, which is used by the
359 // given instruction, is killed by the given instruction.
360 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
361 LiveIntervals *LIS) {
362 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
363 !LIS->isNotInMIMap(MI)) {
364 // FIXME: Sometimes tryInstructionTransform() will add instructions and
365 // test whether they can be folded before keeping them. In this case it
366 // sets a kill before recursively calling tryInstructionTransform() again.
367 // If there is no interval available, we assume that this instruction is
368 // one of those. A kill flag is manually inserted on the operand so the
369 // check below will handle it.
370 LiveInterval &LI = LIS->getInterval(Reg);
371 // This is to match the kill flag version where undefs don't have kill
373 if (!LI.hasAtLeastOneValue())
376 SlotIndex useIdx = LIS->getInstructionIndex(MI);
377 LiveInterval::const_iterator I = LI.find(useIdx);
378 assert(I != LI.end() && "Reg must be live-in to use.");
379 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
382 return MI->killsRegister(Reg);
385 /// isKilled - Test if the given register value, which is used by the given
386 /// instruction, is killed by the given instruction. This looks through
387 /// coalescable copies to see if the original value is potentially not killed.
389 /// For example, in this code:
391 /// %reg1034 = copy %reg1024
392 /// %reg1035 = copy %reg1025<kill>
393 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
395 /// %reg1034 is not considered to be killed, since it is copied from a
396 /// register which is not killed. Treating it as not killed lets the
397 /// normal heuristics commute the (two-address) add, which lets
398 /// coalescing eliminate the extra copy.
400 /// If allowFalsePositives is true then likely kills are treated as kills even
401 /// if it can't be proven that they are kills.
402 static bool isKilled(MachineInstr &MI, unsigned Reg,
403 const MachineRegisterInfo *MRI,
404 const TargetInstrInfo *TII,
406 bool allowFalsePositives) {
407 MachineInstr *DefMI = &MI;
409 // All uses of physical registers are likely to be kills.
410 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
411 (allowFalsePositives || MRI->hasOneUse(Reg)))
413 if (!isPlainlyKilled(DefMI, Reg, LIS))
415 if (TargetRegisterInfo::isPhysicalRegister(Reg))
417 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
418 // If there are multiple defs, we can't do a simple analysis, so just
419 // go with what the kill flag says.
420 if (std::next(Begin) != MRI->def_end())
422 DefMI = Begin->getParent();
423 bool IsSrcPhys, IsDstPhys;
424 unsigned SrcReg, DstReg;
425 // If the def is something other than a copy, then it isn't going to
426 // be coalesced, so follow the kill flag.
427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
433 /// isTwoAddrUse - Return true if the specified MI uses the specified register
434 /// as a two-address use. If so, return the destination register by reference.
435 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
436 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
437 const MachineOperand &MO = MI.getOperand(i);
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
441 if (MI.isRegTiedToDefOperand(i, &ti)) {
442 DstReg = MI.getOperand(ti).getReg();
449 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
450 /// use, return the use instruction if it's a copy or a two-address use.
452 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
453 MachineRegisterInfo *MRI,
454 const TargetInstrInfo *TII,
456 unsigned &DstReg, bool &IsDstPhys) {
457 if (!MRI->hasOneNonDBGUse(Reg))
458 // None or more than one use.
460 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
461 if (UseMI.getParent() != MBB)
465 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
470 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
471 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
477 /// getMappedReg - Return the physical register the specified virtual register
478 /// might be mapped to.
480 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
481 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
482 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
483 if (SI == RegMap.end())
487 if (TargetRegisterInfo::isPhysicalRegister(Reg))
492 /// regsAreCompatible - Return true if the two registers are equal or aliased.
495 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
500 return TRI->regsOverlap(RegA, RegB);
504 /// isProfitableToCommute - Return true if it's potentially profitable to commute
505 /// the two-address instruction that's being processed.
507 TwoAddressInstructionPass::
508 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
509 MachineInstr *MI, unsigned Dist) {
510 if (OptLevel == CodeGenOpt::None)
513 // Determine if it's profitable to commute this two address instruction. In
514 // general, we want no uses between this instruction and the definition of
515 // the two-address register.
517 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
518 // %reg1029<def> = MOV8rr %reg1028
519 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
520 // insert => %reg1030<def> = MOV8rr %reg1028
521 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
522 // In this case, it might not be possible to coalesce the second MOV8rr
523 // instruction if the first one is coalesced. So it would be profitable to
525 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
526 // %reg1029<def> = MOV8rr %reg1028
527 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
528 // insert => %reg1030<def> = MOV8rr %reg1029
529 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
531 if (!isPlainlyKilled(MI, regC, LIS))
534 // Ok, we have something like:
535 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
536 // let's see if it's worth commuting it.
538 // Look for situations like this:
539 // %reg1024<def> = MOV r1
540 // %reg1025<def> = MOV r0
541 // %reg1026<def> = ADD %reg1024, %reg1025
543 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
544 unsigned ToRegA = getMappedReg(regA, DstRegMap);
546 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
547 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
548 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
549 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
551 // Compute if any of the following are true:
552 // -RegB is not tied to a register and RegC is compatible with RegA.
553 // -RegB is tied to the wrong physical register, but RegC is.
554 // -RegB is tied to the wrong physical register, and RegC isn't tied.
555 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
557 // Don't compute if any of the following are true:
558 // -RegC is not tied to a register and RegB is compatible with RegA.
559 // -RegC is tied to the wrong physical register, but RegB is.
560 // -RegC is tied to the wrong physical register, and RegB isn't tied.
561 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
565 // If there is a use of regC between its last def (could be livein) and this
566 // instruction, then bail.
567 unsigned LastDefC = 0;
568 if (!noUseAfterLastDef(regC, Dist, LastDefC))
571 // If there is a use of regB between its last def (could be livein) and this
572 // instruction, then go ahead and make this transformation.
573 unsigned LastDefB = 0;
574 if (!noUseAfterLastDef(regB, Dist, LastDefB))
577 // Since there are no intervening uses for both registers, then commute
578 // if the def of regC is closer. Its live interval is shorter.
579 return LastDefB && LastDefC && LastDefC > LastDefB;
582 /// commuteInstruction - Commute a two-address instruction and update the basic
583 /// block, distance map, and live variables if needed. Return true if it is
585 bool TwoAddressInstructionPass::
586 commuteInstruction(MachineBasicBlock::iterator &mi,
587 unsigned RegB, unsigned RegC, unsigned Dist) {
588 MachineInstr *MI = mi;
589 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
590 MachineInstr *NewMI = TII->commuteInstruction(MI);
592 if (NewMI == nullptr) {
593 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
597 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
598 assert(NewMI == MI &&
599 "TargetInstrInfo::commuteInstruction() should not return a new "
600 "instruction unless it was requested.");
602 // Update source register map.
603 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
605 unsigned RegA = MI->getOperand(0).getReg();
606 SrcRegMap[RegA] = FromRegC;
612 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
613 /// given 2-address instruction to a 3-address one.
615 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
616 // Look for situations like this:
617 // %reg1024<def> = MOV r1
618 // %reg1025<def> = MOV r0
619 // %reg1026<def> = ADD %reg1024, %reg1025
621 // Turn ADD into a 3-address instruction to avoid a copy.
622 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
625 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
626 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
629 /// convertInstTo3Addr - Convert the specified two-address instruction into a
630 /// three address one. Return true if this transformation was successful.
632 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
633 MachineBasicBlock::iterator &nmi,
634 unsigned RegA, unsigned RegB,
636 // FIXME: Why does convertToThreeAddress() need an iterator reference?
637 MachineFunction::iterator MFI = MBB;
638 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
639 assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
643 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
644 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
648 LIS->ReplaceMachineInstrInMaps(mi, NewMI);
650 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
651 // FIXME: Temporary workaround. If the new instruction doesn't
652 // uses RegB, convertToThreeAddress must have created more
653 // then one instruction.
654 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
656 MBB->erase(mi); // Nuke the old inst.
659 DistanceMap.insert(std::make_pair(NewMI, Dist));
664 // Update source and destination register maps.
665 SrcRegMap.erase(RegA);
666 DstRegMap.erase(RegB);
670 /// scanUses - Scan forward recursively for only uses, update maps if the use
671 /// is a copy or a two-address instruction.
673 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
674 SmallVector<unsigned, 4> VirtRegPairs;
678 unsigned Reg = DstReg;
679 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
680 NewReg, IsDstPhys)) {
681 if (IsCopy && !Processed.insert(UseMI).second)
684 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
685 if (DI != DistanceMap.end())
686 // Earlier in the same MBB.Reached via a back edge.
690 VirtRegPairs.push_back(NewReg);
693 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
695 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
696 VirtRegPairs.push_back(NewReg);
700 if (!VirtRegPairs.empty()) {
701 unsigned ToReg = VirtRegPairs.back();
702 VirtRegPairs.pop_back();
703 while (!VirtRegPairs.empty()) {
704 unsigned FromReg = VirtRegPairs.back();
705 VirtRegPairs.pop_back();
706 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
708 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
711 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
713 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
717 /// processCopy - If the specified instruction is not yet processed, process it
718 /// if it's a copy. For a copy instruction, we find the physical registers the
719 /// source and destination registers might be mapped to. These are kept in
720 /// point-to maps used to determine future optimizations. e.g.
723 /// v1026 = add v1024, v1025
725 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
726 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
727 /// potentially joined with r1 on the output side. It's worthwhile to commute
728 /// 'add' to eliminate a copy.
729 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
730 if (Processed.count(MI))
733 bool IsSrcPhys, IsDstPhys;
734 unsigned SrcReg, DstReg;
735 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
738 if (IsDstPhys && !IsSrcPhys)
739 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
740 else if (!IsDstPhys && IsSrcPhys) {
741 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
743 assert(SrcRegMap[DstReg] == SrcReg &&
744 "Can't map to two src physical registers!");
749 Processed.insert(MI);
753 /// rescheduleMIBelowKill - If there is one more local instruction that reads
754 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
755 /// instruction in order to eliminate the need for the copy.
756 bool TwoAddressInstructionPass::
757 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
758 MachineBasicBlock::iterator &nmi,
760 // Bail immediately if we don't have LV or LIS available. We use them to find
761 // kills efficiently.
765 MachineInstr *MI = &*mi;
766 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
767 if (DI == DistanceMap.end())
768 // Must be created from unfolded load. Don't waste time trying this.
771 MachineInstr *KillMI = nullptr;
773 LiveInterval &LI = LIS->getInterval(Reg);
774 assert(LI.end() != LI.begin() &&
775 "Reg should not have empty live interval.");
777 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
778 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
779 if (I != LI.end() && I->start < MBBEndIdx)
783 KillMI = LIS->getInstructionFromIndex(I->end);
785 KillMI = LV->getVarInfo(Reg).findKill(MBB);
787 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
788 // Don't mess with copies, they may be coalesced later.
791 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
792 KillMI->isBranch() || KillMI->isTerminator())
793 // Don't move pass calls, etc.
797 if (isTwoAddrUse(*KillMI, Reg, DstReg))
800 bool SeenStore = true;
801 if (!MI->isSafeToMove(TII, AA, SeenStore))
804 if (TII->getInstrLatency(InstrItins, MI) > 1)
805 // FIXME: Needs more sophisticated heuristics.
808 SmallSet<unsigned, 2> Uses;
809 SmallSet<unsigned, 2> Kills;
810 SmallSet<unsigned, 2> Defs;
811 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
812 const MachineOperand &MO = MI->getOperand(i);
815 unsigned MOReg = MO.getReg();
822 if (MOReg != Reg && (MO.isKill() ||
823 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
828 // Move the copies connected to MI down as well.
829 MachineBasicBlock::iterator Begin = MI;
830 MachineBasicBlock::iterator AfterMI = std::next(Begin);
832 MachineBasicBlock::iterator End = AfterMI;
833 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
834 Defs.insert(End->getOperand(0).getReg());
838 // Check if the reschedule will not break depedencies.
839 unsigned NumVisited = 0;
840 MachineBasicBlock::iterator KillPos = KillMI;
842 for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
843 MachineInstr *OtherMI = I;
844 // DBG_VALUE cannot be counted against the limit.
845 if (OtherMI->isDebugValue())
847 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
850 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
851 OtherMI->isBranch() || OtherMI->isTerminator())
852 // Don't move pass calls, etc.
854 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
855 const MachineOperand &MO = OtherMI->getOperand(i);
858 unsigned MOReg = MO.getReg();
862 if (Uses.count(MOReg))
863 // Physical register use would be clobbered.
865 if (!MO.isDead() && Defs.count(MOReg))
866 // May clobber a physical register def.
867 // FIXME: This may be too conservative. It's ok if the instruction
868 // is sunken completely below the use.
871 if (Defs.count(MOReg))
873 bool isKill = MO.isKill() ||
874 (LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
876 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
877 // Don't want to extend other live ranges and update kills.
879 if (MOReg == Reg && !isKill)
880 // We can't schedule across a use of the register in question.
882 // Ensure that if this is register in question, its the kill we expect.
883 assert((MOReg != Reg || OtherMI == KillMI) &&
884 "Found multiple kills of a register in a basic block");
889 // Move debug info as well.
890 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
894 MachineBasicBlock::iterator InsertPos = KillPos;
896 // We have to move the copies first so that the MBB is still well-formed
897 // when calling handleMove().
898 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
899 MachineInstr *CopyMI = MBBI;
901 MBB->splice(InsertPos, MBB, CopyMI);
902 LIS->handleMove(CopyMI);
905 End = std::next(MachineBasicBlock::iterator(MI));
908 // Copies following MI may have been moved as well.
909 MBB->splice(InsertPos, MBB, Begin, End);
910 DistanceMap.erase(DI);
912 // Update live variables
916 LV->removeVirtualRegisterKilled(Reg, KillMI);
917 LV->addVirtualRegisterKilled(Reg, MI);
920 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
924 /// isDefTooClose - Return true if the re-scheduling will put the given
925 /// instruction too close to the defs of its register dependencies.
926 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
928 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
929 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
932 return true; // MI is defining something KillMI uses
933 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
934 if (DDI == DistanceMap.end())
935 return true; // Below MI
936 unsigned DefDist = DDI->second;
937 assert(Dist > DefDist && "Visited def already?");
938 if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
944 /// rescheduleKillAboveMI - If there is one more local instruction that reads
945 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
946 /// current two-address instruction in order to eliminate the need for the
948 bool TwoAddressInstructionPass::
949 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
950 MachineBasicBlock::iterator &nmi,
952 // Bail immediately if we don't have LV or LIS available. We use them to find
953 // kills efficiently.
957 MachineInstr *MI = &*mi;
958 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
959 if (DI == DistanceMap.end())
960 // Must be created from unfolded load. Don't waste time trying this.
963 MachineInstr *KillMI = nullptr;
965 LiveInterval &LI = LIS->getInterval(Reg);
966 assert(LI.end() != LI.begin() &&
967 "Reg should not have empty live interval.");
969 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
970 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
971 if (I != LI.end() && I->start < MBBEndIdx)
975 KillMI = LIS->getInstructionFromIndex(I->end);
977 KillMI = LV->getVarInfo(Reg).findKill(MBB);
979 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
980 // Don't mess with copies, they may be coalesced later.
984 if (isTwoAddrUse(*KillMI, Reg, DstReg))
987 bool SeenStore = true;
988 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
991 SmallSet<unsigned, 2> Uses;
992 SmallSet<unsigned, 2> Kills;
993 SmallSet<unsigned, 2> Defs;
994 SmallSet<unsigned, 2> LiveDefs;
995 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
996 const MachineOperand &MO = KillMI->getOperand(i);
999 unsigned MOReg = MO.getReg();
1003 if (isDefTooClose(MOReg, DI->second, MI))
1005 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1006 if (MOReg == Reg && !isKill)
1009 if (isKill && MOReg != Reg)
1010 Kills.insert(MOReg);
1011 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1014 LiveDefs.insert(MOReg);
1018 // Check if the reschedule will not break depedencies.
1019 unsigned NumVisited = 0;
1020 MachineBasicBlock::iterator KillPos = KillMI;
1021 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1022 MachineInstr *OtherMI = I;
1023 // DBG_VALUE cannot be counted against the limit.
1024 if (OtherMI->isDebugValue())
1026 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1029 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
1030 OtherMI->isBranch() || OtherMI->isTerminator())
1031 // Don't move pass calls, etc.
1033 SmallVector<unsigned, 2> OtherDefs;
1034 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
1035 const MachineOperand &MO = OtherMI->getOperand(i);
1038 unsigned MOReg = MO.getReg();
1042 if (Defs.count(MOReg))
1043 // Moving KillMI can clobber the physical register if the def has
1046 if (Kills.count(MOReg))
1047 // Don't want to extend other live ranges and update kills.
1049 if (OtherMI != MI && MOReg == Reg &&
1050 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
1051 // We can't schedule across a use of the register in question.
1054 OtherDefs.push_back(MOReg);
1058 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1059 unsigned MOReg = OtherDefs[i];
1060 if (Uses.count(MOReg))
1062 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1063 LiveDefs.count(MOReg))
1065 // Physical register def is seen.
1070 // Move the old kill above MI, don't forget to move debug info as well.
1071 MachineBasicBlock::iterator InsertPos = mi;
1072 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
1074 MachineBasicBlock::iterator From = KillMI;
1075 MachineBasicBlock::iterator To = std::next(From);
1076 while (std::prev(From)->isDebugValue())
1078 MBB->splice(InsertPos, MBB, From, To);
1080 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
1081 DistanceMap.erase(DI);
1083 // Update live variables
1085 LIS->handleMove(KillMI);
1087 LV->removeVirtualRegisterKilled(Reg, KillMI);
1088 LV->addVirtualRegisterKilled(Reg, MI);
1091 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1095 /// tryInstructionTransform - For the case where an instruction has a single
1096 /// pair of tied register operands, attempt some transformations that may
1097 /// either eliminate the tied operands or improve the opportunities for
1098 /// coalescing away the register copy. Returns true if no copy needs to be
1099 /// inserted to untie mi's operands (either because they were untied, or
1100 /// because mi was rescheduled, and will be visited again later). If the
1101 /// shouldOnlyCommute flag is true, only instruction commutation is attempted.
1102 bool TwoAddressInstructionPass::
1103 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1104 MachineBasicBlock::iterator &nmi,
1105 unsigned SrcIdx, unsigned DstIdx,
1106 unsigned Dist, bool shouldOnlyCommute) {
1107 if (OptLevel == CodeGenOpt::None)
1110 MachineInstr &MI = *mi;
1111 unsigned regA = MI.getOperand(DstIdx).getReg();
1112 unsigned regB = MI.getOperand(SrcIdx).getReg();
1114 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1115 "cannot make instruction into two-address form");
1116 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1118 if (TargetRegisterInfo::isVirtualRegister(regA))
1121 // Check if it is profitable to commute the operands.
1122 unsigned SrcOp1, SrcOp2;
1124 unsigned regCIdx = ~0U;
1125 bool TryCommute = false;
1126 bool AggressiveCommute = false;
1127 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1128 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1129 if (SrcIdx == SrcOp1)
1131 else if (SrcIdx == SrcOp2)
1134 if (regCIdx != ~0U) {
1135 regC = MI.getOperand(regCIdx).getReg();
1136 if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false))
1137 // If C dies but B does not, swap the B and C operands.
1138 // This makes the live ranges of A and C joinable.
1140 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1142 AggressiveCommute = true;
1147 // If it's profitable to commute, try to do so.
1148 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1150 if (AggressiveCommute)
1155 if (shouldOnlyCommute)
1158 // If there is one more use of regB later in the same MBB, consider
1159 // re-schedule this MI below it.
1160 if (EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1165 if (MI.isConvertibleTo3Addr()) {
1166 // This instruction is potentially convertible to a true
1167 // three-address instruction. Check if it is profitable.
1168 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1169 // Try to convert it.
1170 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1171 ++NumConvertedTo3Addr;
1172 return true; // Done with this instruction.
1177 // If there is one more use of regB later in the same MBB, consider
1178 // re-schedule it before this MI if it's legal.
1179 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1184 // If this is an instruction with a load folded into it, try unfolding
1185 // the load, e.g. avoid this:
1187 // addq (%rax), %rcx
1188 // in favor of this:
1189 // movq (%rax), %rcx
1191 // because it's preferable to schedule a load than a register copy.
1192 if (MI.mayLoad() && !regBKilled) {
1193 // Determine if a load can be unfolded.
1194 unsigned LoadRegIndex;
1196 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1197 /*UnfoldLoad=*/true,
1198 /*UnfoldStore=*/false,
1201 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1202 if (UnfoldMCID.getNumDefs() == 1) {
1204 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1205 const TargetRegisterClass *RC =
1206 TRI->getAllocatableClass(
1207 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1208 unsigned Reg = MRI->createVirtualRegister(RC);
1209 SmallVector<MachineInstr *, 2> NewMIs;
1210 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1211 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1213 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1216 assert(NewMIs.size() == 2 &&
1217 "Unfolded a load into multiple instructions!");
1218 // The load was previously folded, so this is the only use.
1219 NewMIs[1]->addRegisterKilled(Reg, TRI);
1221 // Tentatively insert the instructions into the block so that they
1222 // look "normal" to the transformation logic.
1223 MBB->insert(mi, NewMIs[0]);
1224 MBB->insert(mi, NewMIs[1]);
1226 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1227 << "2addr: NEW INST: " << *NewMIs[1]);
1229 // Transform the instruction, now that it no longer has a load.
1230 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1231 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1232 MachineBasicBlock::iterator NewMI = NewMIs[1];
1233 bool TransformResult =
1234 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1235 (void)TransformResult;
1236 assert(!TransformResult &&
1237 "tryInstructionTransform() should return false.");
1238 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1239 // Success, or at least we made an improvement. Keep the unfolded
1240 // instructions and discard the original.
1242 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1243 MachineOperand &MO = MI.getOperand(i);
1245 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1248 if (NewMIs[0]->killsRegister(MO.getReg()))
1249 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1251 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1252 "Kill missing after load unfold!");
1253 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1256 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1257 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1258 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1260 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1261 "Dead flag missing after load unfold!");
1262 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1267 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1270 SmallVector<unsigned, 4> OrigRegs;
1272 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
1273 MOE = MI.operands_end(); MOI != MOE; ++MOI) {
1275 OrigRegs.push_back(MOI->getReg());
1279 MI.eraseFromParent();
1281 // Update LiveIntervals.
1283 MachineBasicBlock::iterator Begin(NewMIs[0]);
1284 MachineBasicBlock::iterator End(NewMIs[1]);
1285 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1290 // Transforming didn't eliminate the tie and didn't lead to an
1291 // improvement. Clean up the unfolded instructions and keep the
1293 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1294 NewMIs[0]->eraseFromParent();
1295 NewMIs[1]->eraseFromParent();
1304 // Collect tied operands of MI that need to be handled.
1305 // Rewrite trivial cases immediately.
1306 // Return true if any tied operands where found, including the trivial ones.
1307 bool TwoAddressInstructionPass::
1308 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1309 const MCInstrDesc &MCID = MI->getDesc();
1310 bool AnyOps = false;
1311 unsigned NumOps = MI->getNumOperands();
1313 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1314 unsigned DstIdx = 0;
1315 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1318 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1319 MachineOperand &DstMO = MI->getOperand(DstIdx);
1320 unsigned SrcReg = SrcMO.getReg();
1321 unsigned DstReg = DstMO.getReg();
1322 // Tied constraint already satisfied?
1323 if (SrcReg == DstReg)
1326 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1328 // Deal with <undef> uses immediately - simply rewrite the src operand.
1329 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1330 // Constrain the DstReg register class if required.
1331 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1332 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1334 MRI->constrainRegClass(DstReg, RC);
1335 SrcMO.setReg(DstReg);
1337 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1340 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1345 // Process a list of tied MI operands that all use the same source register.
1346 // The tied pairs are of the form (SrcIdx, DstIdx).
1348 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1349 TiedPairList &TiedPairs,
1351 bool IsEarlyClobber = false;
1352 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1353 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1354 IsEarlyClobber |= DstMO.isEarlyClobber();
1357 bool RemovedKillFlag = false;
1358 bool AllUsesCopied = true;
1359 unsigned LastCopiedReg = 0;
1360 SlotIndex LastCopyIdx;
1362 unsigned SubRegB = 0;
1363 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1364 unsigned SrcIdx = TiedPairs[tpi].first;
1365 unsigned DstIdx = TiedPairs[tpi].second;
1367 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1368 unsigned RegA = DstMO.getReg();
1370 // Grab RegB from the instruction because it may have changed if the
1371 // instruction was commuted.
1372 RegB = MI->getOperand(SrcIdx).getReg();
1373 SubRegB = MI->getOperand(SrcIdx).getSubReg();
1376 // The register is tied to multiple destinations (or else we would
1377 // not have continued this far), but this use of the register
1378 // already matches the tied destination. Leave it.
1379 AllUsesCopied = false;
1382 LastCopiedReg = RegA;
1384 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1385 "cannot make instruction into two-address form");
1388 // First, verify that we don't have a use of "a" in the instruction
1389 // (a = b + a for example) because our transformation will not
1390 // work. This should never occur because we are in SSA form.
1391 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1392 assert(i == DstIdx ||
1393 !MI->getOperand(i).isReg() ||
1394 MI->getOperand(i).getReg() != RegA);
1398 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1399 TII->get(TargetOpcode::COPY), RegA);
1400 // If this operand is folding a truncation, the truncation now moves to the
1401 // copy so that the register classes remain valid for the operands.
1402 MIB.addReg(RegB, 0, SubRegB);
1403 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1405 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1406 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1408 "tied subregister must be a truncation");
1409 // The superreg class will not be used to constrain the subreg class.
1413 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1414 && "tied subregister must be a truncation");
1418 // Update DistanceMap.
1419 MachineBasicBlock::iterator PrevMI = MI;
1421 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1422 DistanceMap[MI] = ++Dist;
1425 LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
1427 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1428 LiveInterval &LI = LIS->getInterval(RegA);
1429 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1431 LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
1432 LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1436 DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1438 MachineOperand &MO = MI->getOperand(SrcIdx);
1439 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1440 "inconsistent operand info for 2-reg pass");
1442 MO.setIsKill(false);
1443 RemovedKillFlag = true;
1446 // Make sure regA is a legal regclass for the SrcIdx operand.
1447 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1448 TargetRegisterInfo::isVirtualRegister(RegB))
1449 MRI->constrainRegClass(RegA, RC);
1451 // The getMatchingSuper asserts guarantee that the register class projected
1452 // by SubRegB is compatible with RegA with no subregister. So regardless of
1453 // whether the dest oper writes a subreg, the source oper should not.
1456 // Propagate SrcRegMap.
1457 SrcRegMap[RegA] = RegB;
1461 if (AllUsesCopied) {
1462 if (!IsEarlyClobber) {
1463 // Replace other (un-tied) uses of regB with LastCopiedReg.
1464 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1465 MachineOperand &MO = MI->getOperand(i);
1466 if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
1469 MO.setIsKill(false);
1470 RemovedKillFlag = true;
1472 MO.setReg(LastCopiedReg);
1478 // Update live variables for regB.
1479 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1480 MachineBasicBlock::iterator PrevMI = MI;
1482 LV->addVirtualRegisterKilled(RegB, PrevMI);
1485 // Update LiveIntervals.
1487 LiveInterval &LI = LIS->getInterval(RegB);
1488 SlotIndex MIIdx = LIS->getInstructionIndex(MI);
1489 LiveInterval::const_iterator I = LI.find(MIIdx);
1490 assert(I != LI.end() && "RegB must be live-in to use.");
1492 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1493 if (I->end == UseIdx)
1494 LI.removeSegment(LastCopyIdx, UseIdx);
1497 } else if (RemovedKillFlag) {
1498 // Some tied uses of regB matched their destination registers, so
1499 // regB is still used in this instruction, but a kill flag was
1500 // removed from a different tied use of regB, so now we need to add
1501 // a kill flag to one of the remaining uses of regB.
1502 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1503 MachineOperand &MO = MI->getOperand(i);
1504 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1512 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1514 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1516 const TargetMachine &TM = MF->getTarget();
1517 MRI = &MF->getRegInfo();
1518 TII = TM.getSubtargetImpl()->getInstrInfo();
1519 TRI = TM.getSubtargetImpl()->getRegisterInfo();
1520 InstrItins = TM.getSubtargetImpl()->getInstrItineraryData();
1521 LV = getAnalysisIfAvailable<LiveVariables>();
1522 LIS = getAnalysisIfAvailable<LiveIntervals>();
1523 AA = &getAnalysis<AliasAnalysis>();
1524 OptLevel = TM.getOptLevel();
1526 bool MadeChange = false;
1528 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1529 DEBUG(dbgs() << "********** Function: "
1530 << MF->getName() << '\n');
1532 // This pass takes the function out of SSA form.
1535 TiedOperandMap TiedOperands;
1536 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1537 MBBI != MBBE; ++MBBI) {
1540 DistanceMap.clear();
1544 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1546 MachineBasicBlock::iterator nmi = std::next(mi);
1547 if (mi->isDebugValue()) {
1552 // Expand REG_SEQUENCE instructions. This will position mi at the first
1553 // expanded instruction.
1554 if (mi->isRegSequence())
1555 eliminateRegSequence(mi);
1557 DistanceMap.insert(std::make_pair(mi, ++Dist));
1561 // First scan through all the tied register uses in this instruction
1562 // and record a list of pairs of tied operands for each register.
1563 if (!collectTiedOperands(mi, TiedOperands)) {
1568 ++NumTwoAddressInstrs;
1570 DEBUG(dbgs() << '\t' << *mi);
1572 // If the instruction has a single pair of tied operands, try some
1573 // transformations that may either eliminate the tied operands or
1574 // improve the opportunities for coalescing away the register copy.
1575 if (TiedOperands.size() == 1) {
1576 SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs
1577 = TiedOperands.begin()->second;
1578 if (TiedPairs.size() == 1) {
1579 unsigned SrcIdx = TiedPairs[0].first;
1580 unsigned DstIdx = TiedPairs[0].second;
1581 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1582 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1583 if (SrcReg != DstReg &&
1584 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1585 // The tied operands have been eliminated or shifted further down the
1586 // block to ease elimination. Continue processing with 'nmi'.
1587 TiedOperands.clear();
1594 // Now iterate over the information collected above.
1595 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1596 OE = TiedOperands.end(); OI != OE; ++OI) {
1597 processTiedPairs(mi, OI->second, Dist);
1598 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1601 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1602 if (mi->isInsertSubreg()) {
1603 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1604 // To %reg:subidx = COPY %subreg
1605 unsigned SubIdx = mi->getOperand(3).getImm();
1606 mi->RemoveOperand(3);
1607 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1608 mi->getOperand(0).setSubReg(SubIdx);
1609 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1610 mi->RemoveOperand(1);
1611 mi->setDesc(TII->get(TargetOpcode::COPY));
1612 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1615 // Clear TiedOperands here instead of at the top of the loop
1616 // since most instructions do not have tied operands.
1617 TiedOperands.clear();
1623 MF->verify(this, "After two-address instruction pass");
1628 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1630 /// The instruction is turned into a sequence of sub-register copies:
1632 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1636 /// %dst:ssub0<def,undef> = COPY %v1
1637 /// %dst:ssub1<def> = COPY %v2
1639 void TwoAddressInstructionPass::
1640 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1641 MachineInstr *MI = MBBI;
1642 unsigned DstReg = MI->getOperand(0).getReg();
1643 if (MI->getOperand(0).getSubReg() ||
1644 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1645 !(MI->getNumOperands() & 1)) {
1646 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1647 llvm_unreachable(nullptr);
1650 SmallVector<unsigned, 4> OrigRegs;
1652 OrigRegs.push_back(MI->getOperand(0).getReg());
1653 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
1654 OrigRegs.push_back(MI->getOperand(i).getReg());
1657 bool DefEmitted = false;
1658 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1659 MachineOperand &UseMO = MI->getOperand(i);
1660 unsigned SrcReg = UseMO.getReg();
1661 unsigned SubIdx = MI->getOperand(i+1).getImm();
1662 // Nothing needs to be inserted for <undef> operands.
1663 if (UseMO.isUndef())
1666 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1667 // might insert a COPY that uses SrcReg after is was killed.
1668 bool isKill = UseMO.isKill();
1670 for (unsigned j = i + 2; j < e; j += 2)
1671 if (MI->getOperand(j).getReg() == SrcReg) {
1672 MI->getOperand(j).setIsKill();
1673 UseMO.setIsKill(false);
1678 // Insert the sub-register copy.
1679 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1680 TII->get(TargetOpcode::COPY))
1681 .addReg(DstReg, RegState::Define, SubIdx)
1684 // The first def needs an <undef> flag because there is no live register
1687 CopyMI->getOperand(0).setIsUndef(true);
1688 // Return an iterator pointing to the first inserted instr.
1693 // Update LiveVariables' kill info.
1694 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1695 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1697 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1700 MachineBasicBlock::iterator EndMBBI =
1701 std::next(MachineBasicBlock::iterator(MI));
1704 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1705 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1706 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1707 MI->RemoveOperand(j);
1709 DEBUG(dbgs() << "Eliminated: " << *MI);
1710 MI->eraseFromParent();
1713 // Udpate LiveIntervals.
1715 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);