1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Analysis/AliasAnalysis.h"
38 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
39 #include "llvm/CodeGen/LiveVariables.h"
40 #include "llvm/CodeGen/MachineFunctionPass.h"
41 #include "llvm/CodeGen/MachineInstr.h"
42 #include "llvm/CodeGen/MachineInstrBuilder.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCInstrItineraries.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetMachine.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Target/TargetRegisterInfo.h"
54 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
55 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
56 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
57 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
58 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
59 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
60 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
63 class TwoAddressInstructionPass : public MachineFunctionPass {
65 const TargetInstrInfo *TII;
66 const TargetRegisterInfo *TRI;
67 const InstrItineraryData *InstrItins;
68 MachineRegisterInfo *MRI;
72 CodeGenOpt::Level OptLevel;
74 // The current basic block being processed.
75 MachineBasicBlock *MBB;
77 // DistanceMap - Keep track the distance of a MI from the start of the
78 // current basic block.
79 DenseMap<MachineInstr*, unsigned> DistanceMap;
81 // Set of already processed instructions in the current block.
82 SmallPtrSet<MachineInstr*, 8> Processed;
84 // SrcRegMap - A map from virtual registers to physical registers which are
85 // likely targets to be coalesced to due to copies from physical registers to
86 // virtual registers. e.g. v1024 = move r0.
87 DenseMap<unsigned, unsigned> SrcRegMap;
89 // DstRegMap - A map from virtual registers to physical registers which are
90 // likely targets to be coalesced to due to copies to physical registers from
91 // virtual registers. e.g. r1 = move v1024.
92 DenseMap<unsigned, unsigned> DstRegMap;
94 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
95 MachineBasicBlock::iterator OldPos);
97 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
99 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
100 MachineInstr *MI, unsigned Dist);
102 bool commuteInstruction(MachineBasicBlock::iterator &mi,
103 unsigned RegB, unsigned RegC, unsigned Dist);
105 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
107 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
108 MachineBasicBlock::iterator &nmi,
109 unsigned RegA, unsigned RegB, unsigned Dist);
111 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
113 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
114 MachineBasicBlock::iterator &nmi,
116 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
117 MachineBasicBlock::iterator &nmi,
120 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
121 MachineBasicBlock::iterator &nmi,
122 unsigned SrcIdx, unsigned DstIdx,
123 unsigned Dist, bool shouldOnlyCommute);
125 void scanUses(unsigned DstReg);
127 void processCopy(MachineInstr *MI);
129 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
130 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
131 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
132 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
133 void eliminateRegSequence(MachineBasicBlock::iterator&);
136 static char ID; // Pass identification, replacement for typeid
137 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
138 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
141 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
142 AU.setPreservesCFG();
143 AU.addRequired<AliasAnalysis>();
144 AU.addPreserved<LiveVariables>();
145 AU.addPreserved<SlotIndexes>();
146 AU.addPreserved<LiveIntervals>();
147 AU.addPreservedID(MachineLoopInfoID);
148 AU.addPreservedID(MachineDominatorsID);
149 MachineFunctionPass::getAnalysisUsage(AU);
152 /// runOnMachineFunction - Pass entry point.
153 bool runOnMachineFunction(MachineFunction&);
155 } // end anonymous namespace
157 char TwoAddressInstructionPass::ID = 0;
158 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
159 "Two-Address instruction pass", false, false)
160 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
161 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
162 "Two-Address instruction pass", false, false)
164 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
166 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
168 /// sink3AddrInstruction - A two-address instruction has been converted to a
169 /// three-address instruction to avoid clobbering a register. Try to sink it
170 /// past the instruction that would kill the above mentioned register to reduce
171 /// register pressure.
172 bool TwoAddressInstructionPass::
173 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
174 MachineBasicBlock::iterator OldPos) {
175 // FIXME: Shouldn't we be trying to do this before we three-addressify the
176 // instruction? After this transformation is done, we no longer need
177 // the instruction to be in three-address form.
179 // Check if it's safe to move this instruction.
180 bool SeenStore = true; // Be conservative.
181 if (!MI->isSafeToMove(TII, AA, SeenStore))
185 SmallSet<unsigned, 4> UseRegs;
187 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
188 const MachineOperand &MO = MI->getOperand(i);
191 unsigned MOReg = MO.getReg();
194 if (MO.isUse() && MOReg != SavedReg)
195 UseRegs.insert(MO.getReg());
199 // Don't try to move it if it implicitly defines a register.
202 // For now, don't move any instructions that define multiple registers.
204 DefReg = MO.getReg();
207 // Find the instruction that kills SavedReg.
208 MachineInstr *KillMI = NULL;
210 LiveInterval &LI = LIS->getInterval(SavedReg);
211 assert(LI.end() != LI.begin() &&
212 "Reg should not have empty live interval.");
214 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
215 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
216 if (I != LI.end() && I->start < MBBEndIdx)
220 KillMI = LIS->getInstructionFromIndex(I->end);
223 for (MachineRegisterInfo::use_nodbg_iterator
224 UI = MRI->use_nodbg_begin(SavedReg),
225 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
226 MachineOperand &UseMO = UI.getOperand();
229 KillMI = UseMO.getParent();
234 // If we find the instruction that kills SavedReg, and it is in an
235 // appropriate location, we can try to sink the current instruction
237 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
238 KillMI == OldPos || KillMI->isTerminator())
241 // If any of the definitions are used by another instruction between the
242 // position and the kill use, then it's not safe to sink it.
244 // FIXME: This can be sped up if there is an easy way to query whether an
245 // instruction is before or after another instruction. Then we can use
246 // MachineRegisterInfo def / use instead.
247 MachineOperand *KillMO = NULL;
248 MachineBasicBlock::iterator KillPos = KillMI;
251 unsigned NumVisited = 0;
252 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
253 MachineInstr *OtherMI = I;
254 // DBG_VALUE cannot be counted against the limit.
255 if (OtherMI->isDebugValue())
257 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
260 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
261 MachineOperand &MO = OtherMI->getOperand(i);
264 unsigned MOReg = MO.getReg();
270 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
271 if (OtherMI == KillMI && MOReg == SavedReg)
272 // Save the operand that kills the register. We want to unset the kill
273 // marker if we can sink MI past it.
275 else if (UseRegs.count(MOReg))
276 // One of the uses is killed before the destination.
281 assert(KillMO && "Didn't find kill");
284 // Update kill and LV information.
285 KillMO->setIsKill(false);
286 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
287 KillMO->setIsKill(true);
290 LV->replaceKillInstruction(SavedReg, KillMI, MI);
293 // Move instruction to its destination.
295 MBB->insert(KillPos, MI);
304 /// noUseAfterLastDef - Return true if there are no intervening uses between the
305 /// last instruction in the MBB that defines the specified register and the
306 /// two-address instruction which is being processed. It also returns the last
307 /// def location by reference
308 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
311 unsigned LastUse = Dist;
312 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
313 E = MRI->reg_end(); I != E; ++I) {
314 MachineOperand &MO = I.getOperand();
315 MachineInstr *MI = MO.getParent();
316 if (MI->getParent() != MBB || MI->isDebugValue())
318 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
319 if (DI == DistanceMap.end())
321 if (MO.isUse() && DI->second < LastUse)
322 LastUse = DI->second;
323 if (MO.isDef() && DI->second > LastDef)
324 LastDef = DI->second;
327 return !(LastUse > LastDef && LastUse < Dist);
330 /// isCopyToReg - Return true if the specified MI is a copy instruction or
331 /// a extract_subreg instruction. It also returns the source and destination
332 /// registers and whether they are physical registers by reference.
333 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
334 unsigned &SrcReg, unsigned &DstReg,
335 bool &IsSrcPhys, bool &IsDstPhys) {
339 DstReg = MI.getOperand(0).getReg();
340 SrcReg = MI.getOperand(1).getReg();
341 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
342 DstReg = MI.getOperand(0).getReg();
343 SrcReg = MI.getOperand(2).getReg();
347 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
348 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
352 /// isPLainlyKilled - Test if the given register value, which is used by the
353 // given instruction, is killed by the given instruction.
354 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
355 LiveIntervals *LIS) {
356 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
357 !LIS->isNotInMIMap(MI)) {
358 // FIXME: Sometimes tryInstructionTransform() will add instructions and
359 // test whether they can be folded before keeping them. In this case it
360 // sets a kill before recursively calling tryInstructionTransform() again.
361 // If there is no interval available, we assume that this instruction is
362 // one of those. A kill flag is manually inserted on the operand so the
363 // check below will handle it.
364 LiveInterval &LI = LIS->getInterval(Reg);
365 // This is to match the kill flag version where undefs don't have kill
367 if (!LI.hasAtLeastOneValue())
370 SlotIndex useIdx = LIS->getInstructionIndex(MI);
371 LiveInterval::const_iterator I = LI.find(useIdx);
372 assert(I != LI.end() && "Reg must be live-in to use.");
373 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
376 return MI->killsRegister(Reg);
379 /// isKilled - Test if the given register value, which is used by the given
380 /// instruction, is killed by the given instruction. This looks through
381 /// coalescable copies to see if the original value is potentially not killed.
383 /// For example, in this code:
385 /// %reg1034 = copy %reg1024
386 /// %reg1035 = copy %reg1025<kill>
387 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
389 /// %reg1034 is not considered to be killed, since it is copied from a
390 /// register which is not killed. Treating it as not killed lets the
391 /// normal heuristics commute the (two-address) add, which lets
392 /// coalescing eliminate the extra copy.
394 /// If allowFalsePositives is true then likely kills are treated as kills even
395 /// if it can't be proven that they are kills.
396 static bool isKilled(MachineInstr &MI, unsigned Reg,
397 const MachineRegisterInfo *MRI,
398 const TargetInstrInfo *TII,
400 bool allowFalsePositives) {
401 MachineInstr *DefMI = &MI;
403 // All uses of physical registers are likely to be kills.
404 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
405 (allowFalsePositives || MRI->hasOneUse(Reg)))
407 if (!isPlainlyKilled(DefMI, Reg, LIS))
409 if (TargetRegisterInfo::isPhysicalRegister(Reg))
411 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
412 // If there are multiple defs, we can't do a simple analysis, so just
413 // go with what the kill flag says.
414 if (llvm::next(Begin) != MRI->def_end())
417 bool IsSrcPhys, IsDstPhys;
418 unsigned SrcReg, DstReg;
419 // If the def is something other than a copy, then it isn't going to
420 // be coalesced, so follow the kill flag.
421 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
427 /// isTwoAddrUse - Return true if the specified MI uses the specified register
428 /// as a two-address use. If so, return the destination register by reference.
429 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
430 const MCInstrDesc &MCID = MI.getDesc();
431 unsigned NumOps = MI.isInlineAsm()
432 ? MI.getNumOperands() : MCID.getNumOperands();
433 for (unsigned i = 0; i != NumOps; ++i) {
434 const MachineOperand &MO = MI.getOperand(i);
435 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
438 if (MI.isRegTiedToDefOperand(i, &ti)) {
439 DstReg = MI.getOperand(ti).getReg();
446 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
447 /// use, return the use instruction if it's a copy or a two-address use.
449 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
450 MachineRegisterInfo *MRI,
451 const TargetInstrInfo *TII,
453 unsigned &DstReg, bool &IsDstPhys) {
454 if (!MRI->hasOneNonDBGUse(Reg))
455 // None or more than one use.
457 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
458 if (UseMI.getParent() != MBB)
462 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
467 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
468 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
474 /// getMappedReg - Return the physical register the specified virtual register
475 /// might be mapped to.
477 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
478 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
479 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
480 if (SI == RegMap.end())
484 if (TargetRegisterInfo::isPhysicalRegister(Reg))
489 /// regsAreCompatible - Return true if the two registers are equal or aliased.
492 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
497 return TRI->regsOverlap(RegA, RegB);
501 /// isProfitableToCommute - Return true if it's potentially profitable to commute
502 /// the two-address instruction that's being processed.
504 TwoAddressInstructionPass::
505 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
506 MachineInstr *MI, unsigned Dist) {
507 if (OptLevel == CodeGenOpt::None)
510 // Determine if it's profitable to commute this two address instruction. In
511 // general, we want no uses between this instruction and the definition of
512 // the two-address register.
514 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
515 // %reg1029<def> = MOV8rr %reg1028
516 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
517 // insert => %reg1030<def> = MOV8rr %reg1028
518 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
519 // In this case, it might not be possible to coalesce the second MOV8rr
520 // instruction if the first one is coalesced. So it would be profitable to
522 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
523 // %reg1029<def> = MOV8rr %reg1028
524 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
525 // insert => %reg1030<def> = MOV8rr %reg1029
526 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
528 if (!isPlainlyKilled(MI, regC, LIS))
531 // Ok, we have something like:
532 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
533 // let's see if it's worth commuting it.
535 // Look for situations like this:
536 // %reg1024<def> = MOV r1
537 // %reg1025<def> = MOV r0
538 // %reg1026<def> = ADD %reg1024, %reg1025
540 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
541 unsigned ToRegA = getMappedReg(regA, DstRegMap);
543 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
544 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
545 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
546 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
548 return !BComp && CComp;
551 // If there is a use of regC between its last def (could be livein) and this
552 // instruction, then bail.
553 unsigned LastDefC = 0;
554 if (!noUseAfterLastDef(regC, Dist, LastDefC))
557 // If there is a use of regB between its last def (could be livein) and this
558 // instruction, then go ahead and make this transformation.
559 unsigned LastDefB = 0;
560 if (!noUseAfterLastDef(regB, Dist, LastDefB))
563 // Since there are no intervening uses for both registers, then commute
564 // if the def of regC is closer. Its live interval is shorter.
565 return LastDefB && LastDefC && LastDefC > LastDefB;
568 /// commuteInstruction - Commute a two-address instruction and update the basic
569 /// block, distance map, and live variables if needed. Return true if it is
571 bool TwoAddressInstructionPass::
572 commuteInstruction(MachineBasicBlock::iterator &mi,
573 unsigned RegB, unsigned RegC, unsigned Dist) {
574 MachineInstr *MI = mi;
575 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
576 MachineInstr *NewMI = TII->commuteInstruction(MI);
579 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
583 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
584 assert(NewMI == MI &&
585 "TargetInstrInfo::commuteInstruction() should not return a new "
586 "instruction unless it was requested.");
588 // Update source register map.
589 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
591 unsigned RegA = MI->getOperand(0).getReg();
592 SrcRegMap[RegA] = FromRegC;
598 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
599 /// given 2-address instruction to a 3-address one.
601 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
602 // Look for situations like this:
603 // %reg1024<def> = MOV r1
604 // %reg1025<def> = MOV r0
605 // %reg1026<def> = ADD %reg1024, %reg1025
607 // Turn ADD into a 3-address instruction to avoid a copy.
608 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
611 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
612 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
615 /// convertInstTo3Addr - Convert the specified two-address instruction into a
616 /// three address one. Return true if this transformation was successful.
618 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
619 MachineBasicBlock::iterator &nmi,
620 unsigned RegA, unsigned RegB,
622 // FIXME: Why does convertToThreeAddress() need an iterator reference?
623 MachineFunction::iterator MFI = MBB;
624 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
625 assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
629 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
630 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
634 LIS->ReplaceMachineInstrInMaps(mi, NewMI);
636 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
637 // FIXME: Temporary workaround. If the new instruction doesn't
638 // uses RegB, convertToThreeAddress must have created more
639 // then one instruction.
640 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
642 MBB->erase(mi); // Nuke the old inst.
645 DistanceMap.insert(std::make_pair(NewMI, Dist));
647 nmi = llvm::next(mi);
650 // Update source and destination register maps.
651 SrcRegMap.erase(RegA);
652 DstRegMap.erase(RegB);
656 /// scanUses - Scan forward recursively for only uses, update maps if the use
657 /// is a copy or a two-address instruction.
659 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
660 SmallVector<unsigned, 4> VirtRegPairs;
664 unsigned Reg = DstReg;
665 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
666 NewReg, IsDstPhys)) {
667 if (IsCopy && !Processed.insert(UseMI))
670 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
671 if (DI != DistanceMap.end())
672 // Earlier in the same MBB.Reached via a back edge.
676 VirtRegPairs.push_back(NewReg);
679 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
681 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
682 VirtRegPairs.push_back(NewReg);
686 if (!VirtRegPairs.empty()) {
687 unsigned ToReg = VirtRegPairs.back();
688 VirtRegPairs.pop_back();
689 while (!VirtRegPairs.empty()) {
690 unsigned FromReg = VirtRegPairs.back();
691 VirtRegPairs.pop_back();
692 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
694 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
697 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
699 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
703 /// processCopy - If the specified instruction is not yet processed, process it
704 /// if it's a copy. For a copy instruction, we find the physical registers the
705 /// source and destination registers might be mapped to. These are kept in
706 /// point-to maps used to determine future optimizations. e.g.
709 /// v1026 = add v1024, v1025
711 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
712 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
713 /// potentially joined with r1 on the output side. It's worthwhile to commute
714 /// 'add' to eliminate a copy.
715 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
716 if (Processed.count(MI))
719 bool IsSrcPhys, IsDstPhys;
720 unsigned SrcReg, DstReg;
721 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
724 if (IsDstPhys && !IsSrcPhys)
725 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
726 else if (!IsDstPhys && IsSrcPhys) {
727 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
729 assert(SrcRegMap[DstReg] == SrcReg &&
730 "Can't map to two src physical registers!");
735 Processed.insert(MI);
739 /// rescheduleMIBelowKill - If there is one more local instruction that reads
740 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
741 /// instruction in order to eliminate the need for the copy.
742 bool TwoAddressInstructionPass::
743 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
744 MachineBasicBlock::iterator &nmi,
746 // Bail immediately if we don't have LV or LIS available. We use them to find
747 // kills efficiently.
751 MachineInstr *MI = &*mi;
752 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
753 if (DI == DistanceMap.end())
754 // Must be created from unfolded load. Don't waste time trying this.
757 MachineInstr *KillMI = 0;
759 LiveInterval &LI = LIS->getInterval(Reg);
760 assert(LI.end() != LI.begin() &&
761 "Reg should not have empty live interval.");
763 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
764 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
765 if (I != LI.end() && I->start < MBBEndIdx)
769 KillMI = LIS->getInstructionFromIndex(I->end);
771 KillMI = LV->getVarInfo(Reg).findKill(MBB);
773 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
774 // Don't mess with copies, they may be coalesced later.
777 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
778 KillMI->isBranch() || KillMI->isTerminator())
779 // Don't move pass calls, etc.
783 if (isTwoAddrUse(*KillMI, Reg, DstReg))
786 bool SeenStore = true;
787 if (!MI->isSafeToMove(TII, AA, SeenStore))
790 if (TII->getInstrLatency(InstrItins, MI) > 1)
791 // FIXME: Needs more sophisticated heuristics.
794 SmallSet<unsigned, 2> Uses;
795 SmallSet<unsigned, 2> Kills;
796 SmallSet<unsigned, 2> Defs;
797 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
798 const MachineOperand &MO = MI->getOperand(i);
801 unsigned MOReg = MO.getReg();
808 if (MOReg != Reg && (MO.isKill() ||
809 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
814 // Move the copies connected to MI down as well.
815 MachineBasicBlock::iterator Begin = MI;
816 MachineBasicBlock::iterator AfterMI = llvm::next(Begin);
818 MachineBasicBlock::iterator End = AfterMI;
819 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
820 Defs.insert(End->getOperand(0).getReg());
824 // Check if the reschedule will not break depedencies.
825 unsigned NumVisited = 0;
826 MachineBasicBlock::iterator KillPos = KillMI;
828 for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
829 MachineInstr *OtherMI = I;
830 // DBG_VALUE cannot be counted against the limit.
831 if (OtherMI->isDebugValue())
833 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
836 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
837 OtherMI->isBranch() || OtherMI->isTerminator())
838 // Don't move pass calls, etc.
840 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
841 const MachineOperand &MO = OtherMI->getOperand(i);
844 unsigned MOReg = MO.getReg();
848 if (Uses.count(MOReg))
849 // Physical register use would be clobbered.
851 if (!MO.isDead() && Defs.count(MOReg))
852 // May clobber a physical register def.
853 // FIXME: This may be too conservative. It's ok if the instruction
854 // is sunken completely below the use.
857 if (Defs.count(MOReg))
859 bool isKill = MO.isKill() ||
860 (LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
862 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
863 // Don't want to extend other live ranges and update kills.
865 if (MOReg == Reg && !isKill)
866 // We can't schedule across a use of the register in question.
868 // Ensure that if this is register in question, its the kill we expect.
869 assert((MOReg != Reg || OtherMI == KillMI) &&
870 "Found multiple kills of a register in a basic block");
875 // Move debug info as well.
876 while (Begin != MBB->begin() && llvm::prior(Begin)->isDebugValue())
880 MachineBasicBlock::iterator InsertPos = KillPos;
882 // We have to move the copies first so that the MBB is still well-formed
883 // when calling handleMove().
884 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
885 MachineInstr *CopyMI = MBBI;
887 MBB->splice(InsertPos, MBB, CopyMI);
888 LIS->handleMove(CopyMI);
891 End = llvm::next(MachineBasicBlock::iterator(MI));
894 // Copies following MI may have been moved as well.
895 MBB->splice(InsertPos, MBB, Begin, End);
896 DistanceMap.erase(DI);
898 // Update live variables
902 LV->removeVirtualRegisterKilled(Reg, KillMI);
903 LV->addVirtualRegisterKilled(Reg, MI);
906 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
910 /// isDefTooClose - Return true if the re-scheduling will put the given
911 /// instruction too close to the defs of its register dependencies.
912 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
914 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
915 DE = MRI->def_end(); DI != DE; ++DI) {
916 MachineInstr *DefMI = &*DI;
917 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
920 return true; // MI is defining something KillMI uses
921 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
922 if (DDI == DistanceMap.end())
923 return true; // Below MI
924 unsigned DefDist = DDI->second;
925 assert(Dist > DefDist && "Visited def already?");
926 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
932 /// rescheduleKillAboveMI - If there is one more local instruction that reads
933 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
934 /// current two-address instruction in order to eliminate the need for the
936 bool TwoAddressInstructionPass::
937 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
938 MachineBasicBlock::iterator &nmi,
940 // Bail immediately if we don't have LV or LIS available. We use them to find
941 // kills efficiently.
945 MachineInstr *MI = &*mi;
946 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
947 if (DI == DistanceMap.end())
948 // Must be created from unfolded load. Don't waste time trying this.
951 MachineInstr *KillMI = 0;
953 LiveInterval &LI = LIS->getInterval(Reg);
954 assert(LI.end() != LI.begin() &&
955 "Reg should not have empty live interval.");
957 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
958 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
959 if (I != LI.end() && I->start < MBBEndIdx)
963 KillMI = LIS->getInstructionFromIndex(I->end);
965 KillMI = LV->getVarInfo(Reg).findKill(MBB);
967 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
968 // Don't mess with copies, they may be coalesced later.
972 if (isTwoAddrUse(*KillMI, Reg, DstReg))
975 bool SeenStore = true;
976 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
979 SmallSet<unsigned, 2> Uses;
980 SmallSet<unsigned, 2> Kills;
981 SmallSet<unsigned, 2> Defs;
982 SmallSet<unsigned, 2> LiveDefs;
983 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
984 const MachineOperand &MO = KillMI->getOperand(i);
987 unsigned MOReg = MO.getReg();
991 if (isDefTooClose(MOReg, DI->second, MI))
993 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
994 if (MOReg == Reg && !isKill)
997 if (isKill && MOReg != Reg)
999 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1002 LiveDefs.insert(MOReg);
1006 // Check if the reschedule will not break depedencies.
1007 unsigned NumVisited = 0;
1008 MachineBasicBlock::iterator KillPos = KillMI;
1009 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1010 MachineInstr *OtherMI = I;
1011 // DBG_VALUE cannot be counted against the limit.
1012 if (OtherMI->isDebugValue())
1014 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1017 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
1018 OtherMI->isBranch() || OtherMI->isTerminator())
1019 // Don't move pass calls, etc.
1021 SmallVector<unsigned, 2> OtherDefs;
1022 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
1023 const MachineOperand &MO = OtherMI->getOperand(i);
1026 unsigned MOReg = MO.getReg();
1030 if (Defs.count(MOReg))
1031 // Moving KillMI can clobber the physical register if the def has
1034 if (Kills.count(MOReg))
1035 // Don't want to extend other live ranges and update kills.
1037 if (OtherMI != MI && MOReg == Reg &&
1038 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
1039 // We can't schedule across a use of the register in question.
1042 OtherDefs.push_back(MOReg);
1046 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1047 unsigned MOReg = OtherDefs[i];
1048 if (Uses.count(MOReg))
1050 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1051 LiveDefs.count(MOReg))
1053 // Physical register def is seen.
1058 // Move the old kill above MI, don't forget to move debug info as well.
1059 MachineBasicBlock::iterator InsertPos = mi;
1060 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
1062 MachineBasicBlock::iterator From = KillMI;
1063 MachineBasicBlock::iterator To = llvm::next(From);
1064 while (llvm::prior(From)->isDebugValue())
1066 MBB->splice(InsertPos, MBB, From, To);
1068 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
1069 DistanceMap.erase(DI);
1071 // Update live variables
1073 LIS->handleMove(KillMI);
1075 LV->removeVirtualRegisterKilled(Reg, KillMI);
1076 LV->addVirtualRegisterKilled(Reg, MI);
1079 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1083 /// tryInstructionTransform - For the case where an instruction has a single
1084 /// pair of tied register operands, attempt some transformations that may
1085 /// either eliminate the tied operands or improve the opportunities for
1086 /// coalescing away the register copy. Returns true if no copy needs to be
1087 /// inserted to untie mi's operands (either because they were untied, or
1088 /// because mi was rescheduled, and will be visited again later). If the
1089 /// shouldOnlyCommute flag is true, only instruction commutation is attempted.
1090 bool TwoAddressInstructionPass::
1091 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1092 MachineBasicBlock::iterator &nmi,
1093 unsigned SrcIdx, unsigned DstIdx,
1094 unsigned Dist, bool shouldOnlyCommute) {
1095 if (OptLevel == CodeGenOpt::None)
1098 MachineInstr &MI = *mi;
1099 unsigned regA = MI.getOperand(DstIdx).getReg();
1100 unsigned regB = MI.getOperand(SrcIdx).getReg();
1102 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1103 "cannot make instruction into two-address form");
1104 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1106 if (TargetRegisterInfo::isVirtualRegister(regA))
1109 // Check if it is profitable to commute the operands.
1110 unsigned SrcOp1, SrcOp2;
1112 unsigned regCIdx = ~0U;
1113 bool TryCommute = false;
1114 bool AggressiveCommute = false;
1115 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1116 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1117 if (SrcIdx == SrcOp1)
1119 else if (SrcIdx == SrcOp2)
1122 if (regCIdx != ~0U) {
1123 regC = MI.getOperand(regCIdx).getReg();
1124 if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false))
1125 // If C dies but B does not, swap the B and C operands.
1126 // This makes the live ranges of A and C joinable.
1128 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1130 AggressiveCommute = true;
1135 // If it's profitable to commute, try to do so.
1136 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1138 if (AggressiveCommute)
1143 if (shouldOnlyCommute)
1146 // If there is one more use of regB later in the same MBB, consider
1147 // re-schedule this MI below it.
1148 if (rescheduleMIBelowKill(mi, nmi, regB)) {
1153 if (MI.isConvertibleTo3Addr()) {
1154 // This instruction is potentially convertible to a true
1155 // three-address instruction. Check if it is profitable.
1156 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1157 // Try to convert it.
1158 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1159 ++NumConvertedTo3Addr;
1160 return true; // Done with this instruction.
1165 // If there is one more use of regB later in the same MBB, consider
1166 // re-schedule it before this MI if it's legal.
1167 if (rescheduleKillAboveMI(mi, nmi, regB)) {
1172 // If this is an instruction with a load folded into it, try unfolding
1173 // the load, e.g. avoid this:
1175 // addq (%rax), %rcx
1176 // in favor of this:
1177 // movq (%rax), %rcx
1179 // because it's preferable to schedule a load than a register copy.
1180 if (MI.mayLoad() && !regBKilled) {
1181 // Determine if a load can be unfolded.
1182 unsigned LoadRegIndex;
1184 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1185 /*UnfoldLoad=*/true,
1186 /*UnfoldStore=*/false,
1189 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1190 if (UnfoldMCID.getNumDefs() == 1) {
1192 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1193 const TargetRegisterClass *RC =
1194 TRI->getAllocatableClass(
1195 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1196 unsigned Reg = MRI->createVirtualRegister(RC);
1197 SmallVector<MachineInstr *, 2> NewMIs;
1198 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1199 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1201 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1204 assert(NewMIs.size() == 2 &&
1205 "Unfolded a load into multiple instructions!");
1206 // The load was previously folded, so this is the only use.
1207 NewMIs[1]->addRegisterKilled(Reg, TRI);
1209 // Tentatively insert the instructions into the block so that they
1210 // look "normal" to the transformation logic.
1211 MBB->insert(mi, NewMIs[0]);
1212 MBB->insert(mi, NewMIs[1]);
1214 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1215 << "2addr: NEW INST: " << *NewMIs[1]);
1217 // Transform the instruction, now that it no longer has a load.
1218 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1219 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1220 MachineBasicBlock::iterator NewMI = NewMIs[1];
1221 bool TransformSuccess =
1222 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1223 if (TransformSuccess ||
1224 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1225 // Success, or at least we made an improvement. Keep the unfolded
1226 // instructions and discard the original.
1228 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1229 MachineOperand &MO = MI.getOperand(i);
1231 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1234 if (NewMIs[0]->killsRegister(MO.getReg()))
1235 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1237 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1238 "Kill missing after load unfold!");
1239 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1242 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1243 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1244 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1246 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1247 "Dead flag missing after load unfold!");
1248 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1253 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1256 SmallVector<unsigned, 4> OrigRegs;
1258 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
1259 MOE = MI.operands_end(); MOI != MOE; ++MOI) {
1261 OrigRegs.push_back(MOI->getReg());
1265 MI.eraseFromParent();
1267 // Update LiveIntervals.
1269 MachineBasicBlock::iterator Begin(NewMIs[0]);
1270 MachineBasicBlock::iterator End(NewMIs[1]);
1271 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1275 if (TransformSuccess)
1278 // Transforming didn't eliminate the tie and didn't lead to an
1279 // improvement. Clean up the unfolded instructions and keep the
1281 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1282 NewMIs[0]->eraseFromParent();
1283 NewMIs[1]->eraseFromParent();
1292 // Collect tied operands of MI that need to be handled.
1293 // Rewrite trivial cases immediately.
1294 // Return true if any tied operands where found, including the trivial ones.
1295 bool TwoAddressInstructionPass::
1296 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1297 const MCInstrDesc &MCID = MI->getDesc();
1298 bool AnyOps = false;
1299 unsigned NumOps = MI->getNumOperands();
1301 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1302 unsigned DstIdx = 0;
1303 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1306 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1307 MachineOperand &DstMO = MI->getOperand(DstIdx);
1308 unsigned SrcReg = SrcMO.getReg();
1309 unsigned DstReg = DstMO.getReg();
1310 // Tied constraint already satisfied?
1311 if (SrcReg == DstReg)
1314 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1316 // Deal with <undef> uses immediately - simply rewrite the src operand.
1317 if (SrcMO.isUndef()) {
1318 // Constrain the DstReg register class if required.
1319 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1320 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1322 MRI->constrainRegClass(DstReg, RC);
1323 SrcMO.setReg(DstReg);
1324 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1327 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1332 // Process a list of tied MI operands that all use the same source register.
1333 // The tied pairs are of the form (SrcIdx, DstIdx).
1335 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1336 TiedPairList &TiedPairs,
1338 bool IsEarlyClobber = false;
1339 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1340 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1341 IsEarlyClobber |= DstMO.isEarlyClobber();
1344 bool RemovedKillFlag = false;
1345 bool AllUsesCopied = true;
1346 unsigned LastCopiedReg = 0;
1347 SlotIndex LastCopyIdx;
1349 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1350 unsigned SrcIdx = TiedPairs[tpi].first;
1351 unsigned DstIdx = TiedPairs[tpi].second;
1353 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1354 unsigned RegA = DstMO.getReg();
1356 // Grab RegB from the instruction because it may have changed if the
1357 // instruction was commuted.
1358 RegB = MI->getOperand(SrcIdx).getReg();
1361 // The register is tied to multiple destinations (or else we would
1362 // not have continued this far), but this use of the register
1363 // already matches the tied destination. Leave it.
1364 AllUsesCopied = false;
1367 LastCopiedReg = RegA;
1369 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1370 "cannot make instruction into two-address form");
1373 // First, verify that we don't have a use of "a" in the instruction
1374 // (a = b + a for example) because our transformation will not
1375 // work. This should never occur because we are in SSA form.
1376 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1377 assert(i == DstIdx ||
1378 !MI->getOperand(i).isReg() ||
1379 MI->getOperand(i).getReg() != RegA);
1383 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1384 TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
1386 // Update DistanceMap.
1387 MachineBasicBlock::iterator PrevMI = MI;
1389 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1390 DistanceMap[MI] = ++Dist;
1393 LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
1395 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1396 LiveInterval &LI = LIS->getInterval(RegA);
1397 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1399 LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
1400 LI.addRange(LiveRange(LastCopyIdx, endIdx, VNI));
1404 DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
1406 MachineOperand &MO = MI->getOperand(SrcIdx);
1407 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1408 "inconsistent operand info for 2-reg pass");
1410 MO.setIsKill(false);
1411 RemovedKillFlag = true;
1414 // Make sure regA is a legal regclass for the SrcIdx operand.
1415 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1416 TargetRegisterInfo::isVirtualRegister(RegB))
1417 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
1421 // Propagate SrcRegMap.
1422 SrcRegMap[RegA] = RegB;
1426 if (AllUsesCopied) {
1427 if (!IsEarlyClobber) {
1428 // Replace other (un-tied) uses of regB with LastCopiedReg.
1429 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1430 MachineOperand &MO = MI->getOperand(i);
1431 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1433 MO.setIsKill(false);
1434 RemovedKillFlag = true;
1436 MO.setReg(LastCopiedReg);
1441 // Update live variables for regB.
1442 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1443 MachineBasicBlock::iterator PrevMI = MI;
1445 LV->addVirtualRegisterKilled(RegB, PrevMI);
1448 // Update LiveIntervals.
1450 LiveInterval &LI = LIS->getInterval(RegB);
1451 SlotIndex MIIdx = LIS->getInstructionIndex(MI);
1452 LiveInterval::const_iterator I = LI.find(MIIdx);
1453 assert(I != LI.end() && "RegB must be live-in to use.");
1455 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1456 if (I->end == UseIdx)
1457 LI.removeRange(LastCopyIdx, UseIdx);
1460 } else if (RemovedKillFlag) {
1461 // Some tied uses of regB matched their destination registers, so
1462 // regB is still used in this instruction, but a kill flag was
1463 // removed from a different tied use of regB, so now we need to add
1464 // a kill flag to one of the remaining uses of regB.
1465 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1466 MachineOperand &MO = MI->getOperand(i);
1467 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1475 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1477 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1479 const TargetMachine &TM = MF->getTarget();
1480 MRI = &MF->getRegInfo();
1481 TII = TM.getInstrInfo();
1482 TRI = TM.getRegisterInfo();
1483 InstrItins = TM.getInstrItineraryData();
1484 LV = getAnalysisIfAvailable<LiveVariables>();
1485 LIS = getAnalysisIfAvailable<LiveIntervals>();
1486 AA = &getAnalysis<AliasAnalysis>();
1487 OptLevel = TM.getOptLevel();
1489 bool MadeChange = false;
1491 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1492 DEBUG(dbgs() << "********** Function: "
1493 << MF->getName() << '\n');
1495 // This pass takes the function out of SSA form.
1498 TiedOperandMap TiedOperands;
1499 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1500 MBBI != MBBE; ++MBBI) {
1503 DistanceMap.clear();
1507 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1509 MachineBasicBlock::iterator nmi = llvm::next(mi);
1510 if (mi->isDebugValue()) {
1515 // Expand REG_SEQUENCE instructions. This will position mi at the first
1516 // expanded instruction.
1517 if (mi->isRegSequence())
1518 eliminateRegSequence(mi);
1520 DistanceMap.insert(std::make_pair(mi, ++Dist));
1524 // First scan through all the tied register uses in this instruction
1525 // and record a list of pairs of tied operands for each register.
1526 if (!collectTiedOperands(mi, TiedOperands)) {
1531 ++NumTwoAddressInstrs;
1533 DEBUG(dbgs() << '\t' << *mi);
1535 // If the instruction has a single pair of tied operands, try some
1536 // transformations that may either eliminate the tied operands or
1537 // improve the opportunities for coalescing away the register copy.
1538 if (TiedOperands.size() == 1) {
1539 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs
1540 = TiedOperands.begin()->second;
1541 if (TiedPairs.size() == 1) {
1542 unsigned SrcIdx = TiedPairs[0].first;
1543 unsigned DstIdx = TiedPairs[0].second;
1544 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1545 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1546 if (SrcReg != DstReg &&
1547 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1548 // The tied operands have been eliminated or shifted further down the
1549 // block to ease elimination. Continue processing with 'nmi'.
1550 TiedOperands.clear();
1557 // Now iterate over the information collected above.
1558 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1559 OE = TiedOperands.end(); OI != OE; ++OI) {
1560 processTiedPairs(mi, OI->second, Dist);
1561 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1564 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1565 if (mi->isInsertSubreg()) {
1566 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1567 // To %reg:subidx = COPY %subreg
1568 unsigned SubIdx = mi->getOperand(3).getImm();
1569 mi->RemoveOperand(3);
1570 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1571 mi->getOperand(0).setSubReg(SubIdx);
1572 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1573 mi->RemoveOperand(1);
1574 mi->setDesc(TII->get(TargetOpcode::COPY));
1575 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1578 // Clear TiedOperands here instead of at the top of the loop
1579 // since most instructions do not have tied operands.
1580 TiedOperands.clear();
1586 MF->verify(this, "After two-address instruction pass");
1591 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1593 /// The instruction is turned into a sequence of sub-register copies:
1595 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1599 /// %dst:ssub0<def,undef> = COPY %v1
1600 /// %dst:ssub1<def> = COPY %v2
1602 void TwoAddressInstructionPass::
1603 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1604 MachineInstr *MI = MBBI;
1605 unsigned DstReg = MI->getOperand(0).getReg();
1606 if (MI->getOperand(0).getSubReg() ||
1607 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1608 !(MI->getNumOperands() & 1)) {
1609 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1610 llvm_unreachable(0);
1613 SmallVector<unsigned, 4> OrigRegs;
1615 OrigRegs.push_back(MI->getOperand(0).getReg());
1616 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
1617 OrigRegs.push_back(MI->getOperand(i).getReg());
1620 bool DefEmitted = false;
1621 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1622 MachineOperand &UseMO = MI->getOperand(i);
1623 unsigned SrcReg = UseMO.getReg();
1624 unsigned SubIdx = MI->getOperand(i+1).getImm();
1625 // Nothing needs to be inserted for <undef> operands.
1626 if (UseMO.isUndef())
1629 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1630 // might insert a COPY that uses SrcReg after is was killed.
1631 bool isKill = UseMO.isKill();
1633 for (unsigned j = i + 2; j < e; j += 2)
1634 if (MI->getOperand(j).getReg() == SrcReg) {
1635 MI->getOperand(j).setIsKill();
1636 UseMO.setIsKill(false);
1641 // Insert the sub-register copy.
1642 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1643 TII->get(TargetOpcode::COPY))
1644 .addReg(DstReg, RegState::Define, SubIdx)
1647 // The first def needs an <undef> flag because there is no live register
1650 CopyMI->getOperand(0).setIsUndef(true);
1651 // Return an iterator pointing to the first inserted instr.
1656 // Update LiveVariables' kill info.
1657 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1658 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1660 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1663 MachineBasicBlock::iterator EndMBBI =
1664 llvm::next(MachineBasicBlock::iterator(MI));
1667 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1668 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1669 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1670 MI->RemoveOperand(j);
1672 DEBUG(dbgs() << "Eliminated: " << *MI);
1673 MI->eraseFromParent();
1676 // Udpate LiveIntervals.
1678 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);