1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/Analysis/AliasAnalysis.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/ADT/BitVector.h"
46 #include "llvm/ADT/DenseMap.h"
47 #include "llvm/ADT/SmallSet.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/ADT/STLExtras.h"
52 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
53 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
54 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
55 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
56 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
57 STATISTIC(NumReMats, "Number of instructions re-materialized");
58 STATISTIC(NumDeletes, "Number of dead instructions deleted");
61 class TwoAddressInstructionPass : public MachineFunctionPass {
62 const TargetInstrInfo *TII;
63 const TargetRegisterInfo *TRI;
64 MachineRegisterInfo *MRI;
68 // DistanceMap - Keep track the distance of a MI from the start of the
69 // current basic block.
70 DenseMap<MachineInstr*, unsigned> DistanceMap;
72 // SrcRegMap - A map from virtual registers to physical registers which
73 // are likely targets to be coalesced to due to copies from physical
74 // registers to virtual registers. e.g. v1024 = move r0.
75 DenseMap<unsigned, unsigned> SrcRegMap;
77 // DstRegMap - A map from virtual registers to physical registers which
78 // are likely targets to be coalesced to due to copies to physical
79 // registers from virtual registers. e.g. r1 = move v1024.
80 DenseMap<unsigned, unsigned> DstRegMap;
82 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
83 /// during the initial walk of the machine function.
84 SmallVector<MachineInstr*, 16> RegSequences;
86 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
88 MachineBasicBlock::iterator OldPos);
90 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
91 MachineInstr *MI, MachineInstr *DefMI,
92 MachineBasicBlock *MBB, unsigned Loc);
94 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
97 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
100 bool isProfitableToCommute(unsigned regB, unsigned regC,
101 MachineInstr *MI, MachineBasicBlock *MBB,
104 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
105 MachineFunction::iterator &mbbi,
106 unsigned RegB, unsigned RegC, unsigned Dist);
108 bool isProfitableToConv3Addr(unsigned RegA);
110 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
111 MachineBasicBlock::iterator &nmi,
112 MachineFunction::iterator &mbbi,
113 unsigned RegB, unsigned Dist);
115 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
116 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
117 SmallVector<NewKill, 4> &NewKills,
118 MachineBasicBlock *MBB, unsigned Dist);
119 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
120 MachineBasicBlock::iterator &nmi,
121 MachineFunction::iterator &mbbi, unsigned Dist);
123 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
124 MachineBasicBlock::iterator &nmi,
125 MachineFunction::iterator &mbbi,
126 unsigned SrcIdx, unsigned DstIdx,
129 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
130 SmallPtrSet<MachineInstr*, 8> &Processed);
132 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
134 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
135 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
136 /// sub-register references of the register defined by REG_SEQUENCE.
137 bool EliminateRegSequences();
140 static char ID; // Pass identification, replacement for typeid
141 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
142 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
145 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
146 AU.setPreservesCFG();
147 AU.addRequired<AliasAnalysis>();
148 AU.addPreserved<LiveVariables>();
149 AU.addPreservedID(MachineLoopInfoID);
150 AU.addPreservedID(MachineDominatorsID);
151 AU.addPreservedID(PHIEliminationID);
152 MachineFunctionPass::getAnalysisUsage(AU);
155 /// runOnMachineFunction - Pass entry point.
156 bool runOnMachineFunction(MachineFunction&);
160 char TwoAddressInstructionPass::ID = 0;
161 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
162 "Two-Address instruction pass", false, false)
163 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
164 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
165 "Two-Address instruction pass", false, false)
167 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
169 /// Sink3AddrInstruction - A two-address instruction has been converted to a
170 /// three-address instruction to avoid clobbering a register. Try to sink it
171 /// past the instruction that would kill the above mentioned register to reduce
172 /// register pressure.
173 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
174 MachineInstr *MI, unsigned SavedReg,
175 MachineBasicBlock::iterator OldPos) {
176 // Check if it's safe to move this instruction.
177 bool SeenStore = true; // Be conservative.
178 if (!MI->isSafeToMove(TII, AA, SeenStore))
182 SmallSet<unsigned, 4> UseRegs;
184 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
185 const MachineOperand &MO = MI->getOperand(i);
188 unsigned MOReg = MO.getReg();
191 if (MO.isUse() && MOReg != SavedReg)
192 UseRegs.insert(MO.getReg());
196 // Don't try to move it if it implicitly defines a register.
199 // For now, don't move any instructions that define multiple registers.
201 DefReg = MO.getReg();
204 // Find the instruction that kills SavedReg.
205 MachineInstr *KillMI = NULL;
206 for (MachineRegisterInfo::use_nodbg_iterator
207 UI = MRI->use_nodbg_begin(SavedReg),
208 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
209 MachineOperand &UseMO = UI.getOperand();
212 KillMI = UseMO.getParent();
216 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
219 // If any of the definitions are used by another instruction between the
220 // position and the kill use, then it's not safe to sink it.
222 // FIXME: This can be sped up if there is an easy way to query whether an
223 // instruction is before or after another instruction. Then we can use
224 // MachineRegisterInfo def / use instead.
225 MachineOperand *KillMO = NULL;
226 MachineBasicBlock::iterator KillPos = KillMI;
229 unsigned NumVisited = 0;
230 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
231 MachineInstr *OtherMI = I;
232 // DBG_VALUE cannot be counted against the limit.
233 if (OtherMI->isDebugValue())
235 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
238 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = OtherMI->getOperand(i);
242 unsigned MOReg = MO.getReg();
249 if (OtherMI == KillMI && MOReg == SavedReg)
250 // Save the operand that kills the register. We want to unset the kill
251 // marker if we can sink MI past it.
253 else if (UseRegs.count(MOReg))
254 // One of the uses is killed before the destination.
260 // Update kill and LV information.
261 KillMO->setIsKill(false);
262 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
263 KillMO->setIsKill(true);
266 LV->replaceKillInstruction(SavedReg, KillMI, MI);
268 // Move instruction to its destination.
270 MBB->insert(KillPos, MI);
276 /// isTwoAddrUse - Return true if the specified MI is using the specified
277 /// register as a two-address operand.
278 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
279 const TargetInstrDesc &TID = UseMI->getDesc();
280 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
281 MachineOperand &MO = UseMI->getOperand(i);
282 if (MO.isReg() && MO.getReg() == Reg &&
283 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
284 // Earlier use is a two-address one.
290 /// isProfitableToReMat - Return true if the heuristics determines it is likely
291 /// to be profitable to re-materialize the definition of Reg rather than copy
294 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
295 const TargetRegisterClass *RC,
296 MachineInstr *MI, MachineInstr *DefMI,
297 MachineBasicBlock *MBB, unsigned Loc) {
298 bool OtherUse = false;
299 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
300 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
301 MachineOperand &UseMO = UI.getOperand();
302 MachineInstr *UseMI = UseMO.getParent();
303 MachineBasicBlock *UseMBB = UseMI->getParent();
305 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
306 if (DI != DistanceMap.end() && DI->second == Loc)
307 continue; // Current use.
309 // There is at least one other use in the MBB that will clobber the
311 if (isTwoAddrUse(UseMI, Reg))
316 // If other uses in MBB are not two-address uses, then don't remat.
320 // No other uses in the same block, remat if it's defined in the same
321 // block so it does not unnecessarily extend the live range.
322 return MBB == DefMI->getParent();
325 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
326 /// last instruction in the MBB that defines the specified register and the
327 /// two-address instruction which is being processed. It also returns the last
328 /// def location by reference
329 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
330 MachineBasicBlock *MBB, unsigned Dist,
333 unsigned LastUse = Dist;
334 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
335 E = MRI->reg_end(); I != E; ++I) {
336 MachineOperand &MO = I.getOperand();
337 MachineInstr *MI = MO.getParent();
338 if (MI->getParent() != MBB || MI->isDebugValue())
340 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
341 if (DI == DistanceMap.end())
343 if (MO.isUse() && DI->second < LastUse)
344 LastUse = DI->second;
345 if (MO.isDef() && DI->second > LastDef)
346 LastDef = DI->second;
349 return !(LastUse > LastDef && LastUse < Dist);
352 MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
353 MachineBasicBlock *MBB,
355 unsigned LastUseDist = 0;
356 MachineInstr *LastUse = 0;
357 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
358 E = MRI->reg_end(); I != E; ++I) {
359 MachineOperand &MO = I.getOperand();
360 MachineInstr *MI = MO.getParent();
361 if (MI->getParent() != MBB || MI->isDebugValue())
363 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
364 if (DI == DistanceMap.end())
366 if (DI->second >= Dist)
369 if (MO.isUse() && DI->second > LastUseDist) {
371 LastUseDist = DI->second;
377 /// isCopyToReg - Return true if the specified MI is a copy instruction or
378 /// a extract_subreg instruction. It also returns the source and destination
379 /// registers and whether they are physical registers by reference.
380 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
381 unsigned &SrcReg, unsigned &DstReg,
382 bool &IsSrcPhys, bool &IsDstPhys) {
386 DstReg = MI.getOperand(0).getReg();
387 SrcReg = MI.getOperand(1).getReg();
388 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
389 DstReg = MI.getOperand(0).getReg();
390 SrcReg = MI.getOperand(2).getReg();
394 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
395 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
399 /// isKilled - Test if the given register value, which is used by the given
400 /// instruction, is killed by the given instruction. This looks through
401 /// coalescable copies to see if the original value is potentially not killed.
403 /// For example, in this code:
405 /// %reg1034 = copy %reg1024
406 /// %reg1035 = copy %reg1025<kill>
407 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
409 /// %reg1034 is not considered to be killed, since it is copied from a
410 /// register which is not killed. Treating it as not killed lets the
411 /// normal heuristics commute the (two-address) add, which lets
412 /// coalescing eliminate the extra copy.
414 static bool isKilled(MachineInstr &MI, unsigned Reg,
415 const MachineRegisterInfo *MRI,
416 const TargetInstrInfo *TII) {
417 MachineInstr *DefMI = &MI;
419 if (!DefMI->killsRegister(Reg))
421 if (TargetRegisterInfo::isPhysicalRegister(Reg))
423 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
424 // If there are multiple defs, we can't do a simple analysis, so just
425 // go with what the kill flag says.
426 if (llvm::next(Begin) != MRI->def_end())
429 bool IsSrcPhys, IsDstPhys;
430 unsigned SrcReg, DstReg;
431 // If the def is something other than a copy, then it isn't going to
432 // be coalesced, so follow the kill flag.
433 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
439 /// isTwoAddrUse - Return true if the specified MI uses the specified register
440 /// as a two-address use. If so, return the destination register by reference.
441 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
442 const TargetInstrDesc &TID = MI.getDesc();
443 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands();
444 for (unsigned i = 0; i != NumOps; ++i) {
445 const MachineOperand &MO = MI.getOperand(i);
446 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
449 if (MI.isRegTiedToDefOperand(i, &ti)) {
450 DstReg = MI.getOperand(ti).getReg();
457 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
458 /// use, return the use instruction if it's a copy or a two-address use.
460 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
461 MachineRegisterInfo *MRI,
462 const TargetInstrInfo *TII,
464 unsigned &DstReg, bool &IsDstPhys) {
465 if (!MRI->hasOneNonDBGUse(Reg))
466 // None or more than one use.
468 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
469 if (UseMI.getParent() != MBB)
473 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
478 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
479 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
485 /// getMappedReg - Return the physical register the specified virtual register
486 /// might be mapped to.
488 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
489 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
490 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
491 if (SI == RegMap.end())
495 if (TargetRegisterInfo::isPhysicalRegister(Reg))
500 /// regsAreCompatible - Return true if the two registers are equal or aliased.
503 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
508 return TRI->regsOverlap(RegA, RegB);
512 /// isProfitableToReMat - Return true if it's potentially profitable to commute
513 /// the two-address instruction that's being processed.
515 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
516 MachineInstr *MI, MachineBasicBlock *MBB,
518 // Determine if it's profitable to commute this two address instruction. In
519 // general, we want no uses between this instruction and the definition of
520 // the two-address register.
522 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
523 // %reg1029<def> = MOV8rr %reg1028
524 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
525 // insert => %reg1030<def> = MOV8rr %reg1028
526 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
527 // In this case, it might not be possible to coalesce the second MOV8rr
528 // instruction if the first one is coalesced. So it would be profitable to
530 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
531 // %reg1029<def> = MOV8rr %reg1028
532 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
533 // insert => %reg1030<def> = MOV8rr %reg1029
534 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
536 if (!MI->killsRegister(regC))
539 // Ok, we have something like:
540 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
541 // let's see if it's worth commuting it.
543 // Look for situations like this:
544 // %reg1024<def> = MOV r1
545 // %reg1025<def> = MOV r0
546 // %reg1026<def> = ADD %reg1024, %reg1025
548 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
549 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
550 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
551 unsigned ToRegB = getMappedReg(regB, DstRegMap);
552 unsigned ToRegC = getMappedReg(regC, DstRegMap);
553 if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
554 ((!FromRegC && !ToRegC) ||
555 regsAreCompatible(FromRegB, ToRegC, TRI) ||
556 regsAreCompatible(FromRegC, ToRegB, TRI)))
559 // If there is a use of regC between its last def (could be livein) and this
560 // instruction, then bail.
561 unsigned LastDefC = 0;
562 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
565 // If there is a use of regB between its last def (could be livein) and this
566 // instruction, then go ahead and make this transformation.
567 unsigned LastDefB = 0;
568 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
571 // Since there are no intervening uses for both registers, then commute
572 // if the def of regC is closer. Its live interval is shorter.
573 return LastDefB && LastDefC && LastDefC > LastDefB;
576 /// CommuteInstruction - Commute a two-address instruction and update the basic
577 /// block, distance map, and live variables if needed. Return true if it is
580 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
581 MachineFunction::iterator &mbbi,
582 unsigned RegB, unsigned RegC, unsigned Dist) {
583 MachineInstr *MI = mi;
584 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
585 MachineInstr *NewMI = TII->commuteInstruction(MI);
588 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
592 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
593 // If the instruction changed to commute it, update livevar.
596 // Update live variables
597 LV->replaceKillInstruction(RegC, MI, NewMI);
599 mbbi->insert(mi, NewMI); // Insert the new inst
600 mbbi->erase(mi); // Nuke the old inst.
602 DistanceMap.insert(std::make_pair(NewMI, Dist));
605 // Update source register map.
606 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
608 unsigned RegA = MI->getOperand(0).getReg();
609 SrcRegMap[RegA] = FromRegC;
615 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
616 /// given 2-address instruction to a 3-address one.
618 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
619 // Look for situations like this:
620 // %reg1024<def> = MOV r1
621 // %reg1025<def> = MOV r0
622 // %reg1026<def> = ADD %reg1024, %reg1025
624 // Turn ADD into a 3-address instruction to avoid a copy.
625 unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
626 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
627 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
630 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
631 /// three address one. Return true if this transformation was successful.
633 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
634 MachineBasicBlock::iterator &nmi,
635 MachineFunction::iterator &mbbi,
636 unsigned RegB, unsigned Dist) {
637 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
639 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
640 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
643 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
644 // FIXME: Temporary workaround. If the new instruction doesn't
645 // uses RegB, convertToThreeAddress must have created more
646 // then one instruction.
647 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
649 mbbi->erase(mi); // Nuke the old inst.
652 DistanceMap.insert(std::make_pair(NewMI, Dist));
654 nmi = llvm::next(mi);
662 /// ProcessCopy - If the specified instruction is not yet processed, process it
663 /// if it's a copy. For a copy instruction, we find the physical registers the
664 /// source and destination registers might be mapped to. These are kept in
665 /// point-to maps used to determine future optimizations. e.g.
668 /// v1026 = add v1024, v1025
670 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
671 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
672 /// potentially joined with r1 on the output side. It's worthwhile to commute
673 /// 'add' to eliminate a copy.
674 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
675 MachineBasicBlock *MBB,
676 SmallPtrSet<MachineInstr*, 8> &Processed) {
677 if (Processed.count(MI))
680 bool IsSrcPhys, IsDstPhys;
681 unsigned SrcReg, DstReg;
682 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
685 if (IsDstPhys && !IsSrcPhys)
686 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
687 else if (!IsDstPhys && IsSrcPhys) {
688 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
690 assert(SrcRegMap[DstReg] == SrcReg &&
691 "Can't map to two src physical registers!");
693 SmallVector<unsigned, 4> VirtRegPairs;
696 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
697 IsCopy, NewReg, IsDstPhys)) {
699 if (!Processed.insert(UseMI))
703 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
704 if (DI != DistanceMap.end())
705 // Earlier in the same MBB.Reached via a back edge.
709 VirtRegPairs.push_back(NewReg);
712 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
714 assert(SrcRegMap[NewReg] == DstReg &&
715 "Can't map to two src physical registers!");
716 VirtRegPairs.push_back(NewReg);
720 if (!VirtRegPairs.empty()) {
721 unsigned ToReg = VirtRegPairs.back();
722 VirtRegPairs.pop_back();
723 while (!VirtRegPairs.empty()) {
724 unsigned FromReg = VirtRegPairs.back();
725 VirtRegPairs.pop_back();
726 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
728 assert(DstRegMap[FromReg] == ToReg &&
729 "Can't map to two dst physical registers!");
735 Processed.insert(MI);
738 /// isSafeToDelete - If the specified instruction does not produce any side
739 /// effects and all of its defs are dead, then it's safe to delete.
740 static bool isSafeToDelete(MachineInstr *MI,
741 const TargetInstrInfo *TII,
742 SmallVector<unsigned, 4> &Kills) {
743 const TargetInstrDesc &TID = MI->getDesc();
744 if (TID.mayStore() || TID.isCall())
746 if (TID.isTerminator() || MI->hasUnmodeledSideEffects())
749 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
750 MachineOperand &MO = MI->getOperand(i);
753 if (MO.isDef() && !MO.isDead())
755 if (MO.isUse() && MO.isKill())
756 Kills.push_back(MO.getReg());
761 /// canUpdateDeletedKills - Check if all the registers listed in Kills are
762 /// killed by instructions in MBB preceding the current instruction at
763 /// position Dist. If so, return true and record information about the
764 /// preceding kills in NewKills.
765 bool TwoAddressInstructionPass::
766 canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
767 SmallVector<NewKill, 4> &NewKills,
768 MachineBasicBlock *MBB, unsigned Dist) {
769 while (!Kills.empty()) {
770 unsigned Kill = Kills.back();
772 if (TargetRegisterInfo::isPhysicalRegister(Kill))
775 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
779 bool isModRef = LastKill->definesRegister(Kill);
780 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
786 /// DeleteUnusedInstr - If an instruction with a tied register operand can
787 /// be safely deleted, just delete it.
789 TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
790 MachineBasicBlock::iterator &nmi,
791 MachineFunction::iterator &mbbi,
793 // Check if the instruction has no side effects and if all its defs are dead.
794 SmallVector<unsigned, 4> Kills;
795 if (!isSafeToDelete(mi, TII, Kills))
798 // If this instruction kills some virtual registers, we need to
799 // update the kill information. If it's not possible to do so,
801 SmallVector<NewKill, 4> NewKills;
802 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
806 while (!NewKills.empty()) {
807 MachineInstr *NewKill = NewKills.back().second;
808 unsigned Kill = NewKills.back().first.first;
809 bool isDead = NewKills.back().first.second;
811 if (LV->removeVirtualRegisterKilled(Kill, mi)) {
813 LV->addVirtualRegisterDead(Kill, NewKill);
815 LV->addVirtualRegisterKilled(Kill, NewKill);
820 mbbi->erase(mi); // Nuke the old inst.
825 /// TryInstructionTransform - For the case where an instruction has a single
826 /// pair of tied register operands, attempt some transformations that may
827 /// either eliminate the tied operands or improve the opportunities for
828 /// coalescing away the register copy. Returns true if the tied operands
829 /// are eliminated altogether.
830 bool TwoAddressInstructionPass::
831 TryInstructionTransform(MachineBasicBlock::iterator &mi,
832 MachineBasicBlock::iterator &nmi,
833 MachineFunction::iterator &mbbi,
834 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
835 const TargetInstrDesc &TID = mi->getDesc();
836 unsigned regA = mi->getOperand(DstIdx).getReg();
837 unsigned regB = mi->getOperand(SrcIdx).getReg();
839 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
840 "cannot make instruction into two-address form");
842 // If regA is dead and the instruction can be deleted, just delete
843 // it so it doesn't clobber regB.
844 bool regBKilled = isKilled(*mi, regB, MRI, TII);
845 if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
846 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
848 return true; // Done with this instruction.
851 // Check if it is profitable to commute the operands.
852 unsigned SrcOp1, SrcOp2;
854 unsigned regCIdx = ~0U;
855 bool TryCommute = false;
856 bool AggressiveCommute = false;
857 if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
858 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
859 if (SrcIdx == SrcOp1)
861 else if (SrcIdx == SrcOp2)
864 if (regCIdx != ~0U) {
865 regC = mi->getOperand(regCIdx).getReg();
866 if (!regBKilled && isKilled(*mi, regC, MRI, TII))
867 // If C dies but B does not, swap the B and C operands.
868 // This makes the live ranges of A and C joinable.
870 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
872 AggressiveCommute = true;
877 // If it's profitable to commute, try to do so.
878 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
880 if (AggressiveCommute)
885 if (TID.isConvertibleTo3Addr()) {
886 // This instruction is potentially convertible to a true
887 // three-address instruction. Check if it is profitable.
888 if (!regBKilled || isProfitableToConv3Addr(regA)) {
889 // Try to convert it.
890 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
891 ++NumConvertedTo3Addr;
892 return true; // Done with this instruction.
897 // If this is an instruction with a load folded into it, try unfolding
898 // the load, e.g. avoid this:
904 // because it's preferable to schedule a load than a register copy.
905 if (TID.mayLoad() && !regBKilled) {
906 // Determine if a load can be unfolded.
907 unsigned LoadRegIndex;
909 TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(),
911 /*UnfoldStore=*/false,
914 const TargetInstrDesc &UnfoldTID = TII->get(NewOpc);
915 if (UnfoldTID.getNumDefs() == 1) {
916 MachineFunction &MF = *mbbi->getParent();
919 DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
920 const TargetRegisterClass *RC =
921 UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
922 unsigned Reg = MRI->createVirtualRegister(RC);
923 SmallVector<MachineInstr *, 2> NewMIs;
924 if (!TII->unfoldMemoryOperand(MF, mi, Reg,
925 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
927 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
930 assert(NewMIs.size() == 2 &&
931 "Unfolded a load into multiple instructions!");
932 // The load was previously folded, so this is the only use.
933 NewMIs[1]->addRegisterKilled(Reg, TRI);
935 // Tentatively insert the instructions into the block so that they
936 // look "normal" to the transformation logic.
937 mbbi->insert(mi, NewMIs[0]);
938 mbbi->insert(mi, NewMIs[1]);
940 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
941 << "2addr: NEW INST: " << *NewMIs[1]);
943 // Transform the instruction, now that it no longer has a load.
944 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
945 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
946 MachineBasicBlock::iterator NewMI = NewMIs[1];
947 bool TransformSuccess =
948 TryInstructionTransform(NewMI, mi, mbbi,
949 NewSrcIdx, NewDstIdx, Dist);
950 if (TransformSuccess ||
951 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
952 // Success, or at least we made an improvement. Keep the unfolded
953 // instructions and discard the original.
955 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
956 MachineOperand &MO = mi->getOperand(i);
958 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
961 if (NewMIs[0]->killsRegister(MO.getReg()))
962 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]);
964 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
965 "Kill missing after load unfold!");
966 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]);
969 } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) {
970 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
971 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
973 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
974 "Dead flag missing after load unfold!");
975 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
980 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
982 mi->eraseFromParent();
984 if (TransformSuccess)
987 // Transforming didn't eliminate the tie and didn't lead to an
988 // improvement. Clean up the unfolded instructions and keep the
990 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
991 NewMIs[0]->eraseFromParent();
992 NewMIs[1]->eraseFromParent();
1001 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1003 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
1004 DEBUG(dbgs() << "Machine Function\n");
1005 const TargetMachine &TM = MF.getTarget();
1006 MRI = &MF.getRegInfo();
1007 TII = TM.getInstrInfo();
1008 TRI = TM.getRegisterInfo();
1009 LV = getAnalysisIfAvailable<LiveVariables>();
1010 AA = &getAnalysis<AliasAnalysis>();
1012 bool MadeChange = false;
1014 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1015 DEBUG(dbgs() << "********** Function: "
1016 << MF.getFunction()->getName() << '\n');
1018 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
1019 BitVector ReMatRegs(MRI->getNumVirtRegs());
1021 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
1023 TiedOperandMap TiedOperands(4);
1025 SmallPtrSet<MachineInstr*, 8> Processed;
1026 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
1027 mbbi != mbbe; ++mbbi) {
1029 DistanceMap.clear();
1033 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
1035 MachineBasicBlock::iterator nmi = llvm::next(mi);
1036 if (mi->isDebugValue()) {
1041 // Remember REG_SEQUENCE instructions, we'll deal with them later.
1042 if (mi->isRegSequence())
1043 RegSequences.push_back(&*mi);
1045 const TargetInstrDesc &TID = mi->getDesc();
1046 bool FirstTied = true;
1048 DistanceMap.insert(std::make_pair(mi, ++Dist));
1050 ProcessCopy(&*mi, &*mbbi, Processed);
1052 // First scan through all the tied register uses in this instruction
1053 // and record a list of pairs of tied operands for each register.
1054 unsigned NumOps = mi->isInlineAsm()
1055 ? mi->getNumOperands() : TID.getNumOperands();
1056 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1057 unsigned DstIdx = 0;
1058 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1063 ++NumTwoAddressInstrs;
1064 DEBUG(dbgs() << '\t' << *mi);
1067 assert(mi->getOperand(SrcIdx).isReg() &&
1068 mi->getOperand(SrcIdx).getReg() &&
1069 mi->getOperand(SrcIdx).isUse() &&
1070 "two address instruction invalid");
1072 unsigned regB = mi->getOperand(SrcIdx).getReg();
1073 TiedOperandMap::iterator OI = TiedOperands.find(regB);
1074 if (OI == TiedOperands.end()) {
1075 SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
1076 OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
1078 OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
1081 // Now iterate over the information collected above.
1082 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1083 OE = TiedOperands.end(); OI != OE; ++OI) {
1084 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
1086 // If the instruction has a single pair of tied operands, try some
1087 // transformations that may either eliminate the tied operands or
1088 // improve the opportunities for coalescing away the register copy.
1089 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
1090 unsigned SrcIdx = TiedPairs[0].first;
1091 unsigned DstIdx = TiedPairs[0].second;
1093 // If the registers are already equal, nothing needs to be done.
1094 if (mi->getOperand(SrcIdx).getReg() ==
1095 mi->getOperand(DstIdx).getReg())
1096 break; // Done with this instruction.
1098 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
1099 break; // The tied operands have been eliminated.
1102 bool RemovedKillFlag = false;
1103 bool AllUsesCopied = true;
1104 unsigned LastCopiedReg = 0;
1105 unsigned regB = OI->first;
1106 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1107 unsigned SrcIdx = TiedPairs[tpi].first;
1108 unsigned DstIdx = TiedPairs[tpi].second;
1109 unsigned regA = mi->getOperand(DstIdx).getReg();
1110 // Grab regB from the instruction because it may have changed if the
1111 // instruction was commuted.
1112 regB = mi->getOperand(SrcIdx).getReg();
1115 // The register is tied to multiple destinations (or else we would
1116 // not have continued this far), but this use of the register
1117 // already matches the tied destination. Leave it.
1118 AllUsesCopied = false;
1121 LastCopiedReg = regA;
1123 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1124 "cannot make instruction into two-address form");
1127 // First, verify that we don't have a use of "a" in the instruction
1128 // (a = b + a for example) because our transformation will not
1129 // work. This should never occur because we are in SSA form.
1130 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1131 assert(i == DstIdx ||
1132 !mi->getOperand(i).isReg() ||
1133 mi->getOperand(i).getReg() != regA);
1136 // Emit a copy or rematerialize the definition.
1137 const TargetRegisterClass *rc = MRI->getRegClass(regB);
1138 MachineInstr *DefMI = MRI->getVRegDef(regB);
1139 // If it's safe and profitable, remat the definition instead of
1142 DefMI->getDesc().isAsCheapAsAMove() &&
1143 DefMI->isSafeToReMat(TII, AA, regB) &&
1144 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1145 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
1146 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1147 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
1148 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
1151 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
1155 MachineBasicBlock::iterator prevMI = prior(mi);
1156 // Update DistanceMap.
1157 DistanceMap.insert(std::make_pair(prevMI, Dist));
1158 DistanceMap[mi] = ++Dist;
1160 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
1162 MachineOperand &MO = mi->getOperand(SrcIdx);
1163 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1164 "inconsistent operand info for 2-reg pass");
1166 MO.setIsKill(false);
1167 RemovedKillFlag = true;
1172 if (AllUsesCopied) {
1173 // Replace other (un-tied) uses of regB with LastCopiedReg.
1174 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1175 MachineOperand &MO = mi->getOperand(i);
1176 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1178 MO.setIsKill(false);
1179 RemovedKillFlag = true;
1181 MO.setReg(LastCopiedReg);
1185 // Update live variables for regB.
1186 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1187 LV->addVirtualRegisterKilled(regB, prior(mi));
1189 } else if (RemovedKillFlag) {
1190 // Some tied uses of regB matched their destination registers, so
1191 // regB is still used in this instruction, but a kill flag was
1192 // removed from a different tied use of regB, so now we need to add
1193 // a kill flag to one of the remaining uses of regB.
1194 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1195 MachineOperand &MO = mi->getOperand(i);
1196 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1203 // Schedule the source copy / remat inserted to form two-address
1204 // instruction. FIXME: Does it matter the distance map may not be
1205 // accurate after it's scheduled?
1206 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
1210 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1213 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1214 if (mi->isInsertSubreg()) {
1215 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1216 // To %reg:subidx = COPY %subreg
1217 unsigned SubIdx = mi->getOperand(3).getImm();
1218 mi->RemoveOperand(3);
1219 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1220 mi->getOperand(0).setSubReg(SubIdx);
1221 mi->RemoveOperand(1);
1222 mi->setDesc(TII->get(TargetOpcode::COPY));
1223 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1226 // Clear TiedOperands here instead of at the top of the loop
1227 // since most instructions do not have tied operands.
1228 TiedOperands.clear();
1233 // Some remat'ed instructions are dead.
1234 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
1235 unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
1236 if (MRI->use_nodbg_empty(VReg)) {
1237 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1238 DefMI->eraseFromParent();
1242 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1243 // SSA form. It's now safe to de-SSA.
1244 MadeChange |= EliminateRegSequences();
1249 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1250 unsigned DstReg, unsigned SubIdx,
1251 MachineRegisterInfo *MRI,
1252 const TargetRegisterInfo &TRI) {
1253 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1254 RE = MRI->reg_end(); RI != RE; ) {
1255 MachineOperand &MO = RI.getOperand();
1257 MO.substVirtReg(DstReg, SubIdx, TRI);
1261 /// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
1262 /// EXTRACT_SUBREG from the same register and to the same virtual register
1263 /// with different sub-register indices, attempt to combine the
1264 /// EXTRACT_SUBREGs and pre-coalesce them. e.g.
1265 /// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
1266 /// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
1267 /// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
1268 /// Since D subregs 5, 6 can combine to a Q register, we can coalesce
1269 /// reg1026 to reg1029.
1271 TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
1273 SmallSet<unsigned, 4> Seen;
1274 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
1275 unsigned SrcReg = Srcs[i];
1276 if (!Seen.insert(SrcReg))
1279 // Check that the instructions are all in the same basic block.
1280 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg);
1281 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg);
1282 if (SrcDefMI->getParent() != DstDefMI->getParent())
1285 // If there are no other uses than copies which feed into
1286 // the reg_sequence, then we might be able to coalesce them.
1287 bool CanCoalesce = true;
1288 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
1289 for (MachineRegisterInfo::use_nodbg_iterator
1290 UI = MRI->use_nodbg_begin(SrcReg),
1291 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1292 MachineInstr *UseMI = &*UI;
1293 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
1294 CanCoalesce = false;
1297 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
1298 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
1301 if (!CanCoalesce || SrcSubIndices.size() < 2)
1304 // Check that the source subregisters can be combined.
1305 std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
1306 unsigned NewSrcSubIdx = 0;
1307 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
1311 // Check that the destination subregisters can also be combined.
1312 std::sort(DstSubIndices.begin(), DstSubIndices.end());
1313 unsigned NewDstSubIdx = 0;
1314 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
1318 // If neither source nor destination can be combined to the full register,
1319 // just give up. This could be improved if it ever matters.
1320 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
1323 // Now that we know that all the uses are extract_subregs and that those
1324 // subregs can somehow be combined, scan all the extract_subregs again to
1325 // make sure the subregs are in the right order and can be composed.
1326 MachineInstr *SomeMI = 0;
1328 for (MachineRegisterInfo::use_nodbg_iterator
1329 UI = MRI->use_nodbg_begin(SrcReg),
1330 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1331 MachineInstr *UseMI = &*UI;
1332 assert(UseMI->isCopy());
1333 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
1334 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
1335 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
1336 if ((NewDstSubIdx == 0 &&
1337 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
1338 (NewSrcSubIdx == 0 &&
1339 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
1340 CanCoalesce = false;
1343 // Keep track of one of the uses.
1349 // Insert a copy to replace the original.
1350 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
1351 SomeMI->getDebugLoc(),
1352 TII->get(TargetOpcode::COPY))
1353 .addReg(DstReg, RegState::Define, NewDstSubIdx)
1354 .addReg(SrcReg, 0, NewSrcSubIdx);
1356 // Remove all the old extract instructions.
1357 for (MachineRegisterInfo::use_nodbg_iterator
1358 UI = MRI->use_nodbg_begin(SrcReg),
1359 UE = MRI->use_nodbg_end(); UI != UE; ) {
1360 MachineInstr *UseMI = &*UI;
1362 if (UseMI == CopyMI)
1364 assert(UseMI->isCopy());
1365 // Move any kills to the new copy or extract instruction.
1366 if (UseMI->getOperand(1).isKill()) {
1367 CopyMI->getOperand(1).setIsKill();
1369 // Update live variables
1370 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
1372 UseMI->eraseFromParent();
1377 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
1378 MachineRegisterInfo *MRI) {
1379 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
1380 UE = MRI->use_end(); UI != UE; ++UI) {
1381 MachineInstr *UseMI = &*UI;
1382 if (UseMI != RegSeq && UseMI->isRegSequence())
1388 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1389 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1390 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1392 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1393 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1395 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1396 bool TwoAddressInstructionPass::EliminateRegSequences() {
1397 if (RegSequences.empty())
1400 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1401 MachineInstr *MI = RegSequences[i];
1402 unsigned DstReg = MI->getOperand(0).getReg();
1403 if (MI->getOperand(0).getSubReg() ||
1404 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1405 !(MI->getNumOperands() & 1)) {
1406 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1407 llvm_unreachable(0);
1410 bool IsImpDef = true;
1411 SmallVector<unsigned, 4> RealSrcs;
1412 SmallSet<unsigned, 4> Seen;
1413 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1414 unsigned SrcReg = MI->getOperand(i).getReg();
1415 unsigned SubIdx = MI->getOperand(i+1).getImm();
1416 if (MI->getOperand(i).getSubReg() ||
1417 TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1418 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1419 llvm_unreachable(0);
1422 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
1423 if (DefMI->isImplicitDef()) {
1424 DefMI->eraseFromParent();
1429 // Remember COPY sources. These might be candidate for coalescing.
1430 if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
1431 RealSrcs.push_back(DefMI->getOperand(1).getReg());
1433 bool isKill = MI->getOperand(i).isKill();
1434 if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() ||
1435 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
1436 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
1437 MRI->getRegClass(SrcReg), SubIdx)) {
1438 // REG_SEQUENCE cannot have duplicated operands, add a copy.
1439 // Also add an copy if the source is live-in the block. We don't want
1440 // to end up with a partial-redef of a livein, e.g.
1442 // reg1051:10<def> =
1448 // LiveIntervalAnalysis won't like it.
1450 // If the REG_SEQUENCE doesn't kill its source, keeping live variables
1451 // correctly up to date becomes very difficult. Insert a copy.
1453 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1454 // might insert a COPY that uses SrcReg after is was killed.
1456 for (unsigned j = i + 2; j < e; j += 2)
1457 if (MI->getOperand(j).getReg() == SrcReg) {
1458 MI->getOperand(j).setIsKill();
1463 MachineBasicBlock::iterator InsertLoc = MI;
1464 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
1465 MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
1466 .addReg(DstReg, RegState::Define, SubIdx)
1467 .addReg(SrcReg, getKillRegState(isKill));
1468 MI->getOperand(i).setReg(0);
1470 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1471 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1475 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1476 unsigned SrcReg = MI->getOperand(i).getReg();
1477 if (!SrcReg) continue;
1478 unsigned SubIdx = MI->getOperand(i+1).getImm();
1479 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1483 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1484 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1485 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1486 MI->RemoveOperand(j);
1488 DEBUG(dbgs() << "Eliminated: " << *MI);
1489 MI->eraseFromParent();
1492 // Try coalescing some EXTRACT_SUBREG instructions. This can create
1493 // INSERT_SUBREG instructions that must have <undef> flags added by
1494 // LiveIntervalAnalysis, so only run it when LiveVariables is available.
1496 CoalesceExtSubRegs(RealSrcs, DstReg);
1499 RegSequences.clear();