1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "spiller"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/STLExtras.h"
35 Statistic<> NumSpills("spiller", "Number of register spills");
36 Statistic<> NumStores("spiller", "Number of stores added");
37 Statistic<> NumLoads ("spiller", "Number of loads added");
38 Statistic<> NumReused("spiller", "Number of values reused");
39 Statistic<> NumDSE ("spiller", "Number of dead stores elided");
41 enum SpillerName { simple, local };
45 cl::desc("Spiller to use: (default: local)"),
47 cl::values(clEnumVal(simple, " simple spiller"),
48 clEnumVal(local, " local spiller"),
53 //===----------------------------------------------------------------------===//
54 // VirtRegMap implementation
55 //===----------------------------------------------------------------------===//
57 void VirtRegMap::grow() {
58 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
59 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
62 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
63 assert(MRegisterInfo::isVirtualRegister(virtReg));
64 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
65 "attempt to assign stack slot to already spilled register");
66 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
67 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
69 Virt2StackSlotMap[virtReg] = frameIndex;
74 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
75 assert(MRegisterInfo::isVirtualRegister(virtReg));
76 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
77 "attempt to assign stack slot to already spilled register");
78 Virt2StackSlotMap[virtReg] = frameIndex;
81 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
82 unsigned OpNo, MachineInstr *NewMI) {
83 // Move previous memory references folded to new instruction.
84 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
85 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
86 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
87 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
88 MI2VirtMap.erase(I++);
92 if (!OldMI->getOperand(OpNo).isDef()) {
93 assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?");
96 MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod;
99 // add new memory reference
100 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
103 void VirtRegMap::print(std::ostream &OS) const {
104 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
106 OS << "********** REGISTER MAP **********\n";
107 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
108 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
109 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
110 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
114 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
115 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
116 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
117 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
121 void VirtRegMap::dump() const { print(std::cerr); }
124 //===----------------------------------------------------------------------===//
125 // Simple Spiller Implementation
126 //===----------------------------------------------------------------------===//
128 Spiller::~Spiller() {}
131 struct SimpleSpiller : public Spiller {
132 bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM);
136 bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
137 const VirtRegMap &VRM) {
138 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
139 DEBUG(std::cerr << "********** Function: "
140 << MF.getFunction()->getName() << '\n');
141 const TargetMachine &TM = MF.getTarget();
142 const MRegisterInfo &MRI = *TM.getRegisterInfo();
143 bool *PhysRegsUsed = MF.getUsedPhysregs();
145 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
146 // each vreg once (in the case where a spilled vreg is used by multiple
147 // operands). This is always smaller than the number of operands to the
148 // current machine instr, so it should be small.
149 std::vector<unsigned> LoadedRegs;
151 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
153 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
154 MachineBasicBlock &MBB = *MBBI;
155 for (MachineBasicBlock::iterator MII = MBB.begin(),
156 E = MBB.end(); MII != E; ++MII) {
157 MachineInstr &MI = *MII;
158 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
159 MachineOperand &MO = MI.getOperand(i);
160 if (MO.isRegister() && MO.getReg())
161 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
162 unsigned VirtReg = MO.getReg();
163 unsigned PhysReg = VRM.getPhys(VirtReg);
164 if (VRM.hasStackSlot(VirtReg)) {
165 int StackSlot = VRM.getStackSlot(VirtReg);
166 const TargetRegisterClass* RC =
167 MF.getSSARegMap()->getRegClass(VirtReg);
170 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
171 == LoadedRegs.end()) {
172 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
173 LoadedRegs.push_back(VirtReg);
175 DEBUG(std::cerr << '\t' << *prior(MII));
179 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
183 PhysRegsUsed[PhysReg] = true;
184 MI.SetMachineOperandReg(i, PhysReg);
186 PhysRegsUsed[MO.getReg()] = true;
190 DEBUG(std::cerr << '\t' << MI);
197 //===----------------------------------------------------------------------===//
198 // Local Spiller Implementation
199 //===----------------------------------------------------------------------===//
202 /// LocalSpiller - This spiller does a simple pass over the machine basic
203 /// block to attempt to keep spills in registers as much as possible for
204 /// blocks that have low register pressure (the vreg may be spilled due to
205 /// register pressure in other blocks).
206 class LocalSpiller : public Spiller {
207 const MRegisterInfo *MRI;
208 const TargetInstrInfo *TII;
210 bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) {
211 MRI = MF.getTarget().getRegisterInfo();
212 TII = MF.getTarget().getInstrInfo();
213 DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
214 << MF.getFunction()->getName() << "':\n");
216 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
218 RewriteMBB(*MBB, VRM);
222 void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM);
223 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
224 std::map<unsigned, int> &PhysRegs);
225 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
226 std::map<unsigned, int> &PhysRegs);
230 void LocalSpiller::ClobberPhysRegOnly(unsigned PhysReg,
231 std::map<int, unsigned> &SpillSlots,
232 std::map<unsigned, int> &PhysRegs) {
233 std::map<unsigned, int>::iterator I = PhysRegs.find(PhysReg);
234 if (I != PhysRegs.end()) {
235 int Slot = I->second;
237 assert(SpillSlots[Slot] == PhysReg && "Bidirectional map mismatch!");
238 SpillSlots.erase(Slot);
239 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
240 << " clobbered, invalidating SS#" << Slot << "\n");
245 void LocalSpiller::ClobberPhysReg(unsigned PhysReg,
246 std::map<int, unsigned> &SpillSlots,
247 std::map<unsigned, int> &PhysRegs) {
248 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
249 ClobberPhysRegOnly(*AS, SpillSlots, PhysRegs);
250 ClobberPhysRegOnly(PhysReg, SpillSlots, PhysRegs);
254 // ReusedOp - For each reused operand, we keep track of a bit of information, in
255 // case we need to rollback upon processing a new operand. See comments below.
258 // The MachineInstr operand that reused an available value.
261 // StackSlot - The spill slot of the value being reused.
264 // PhysRegReused - The physical register the value was available in.
265 unsigned PhysRegReused;
267 // AssignedPhysReg - The physreg that was assigned for use by the reload.
268 unsigned AssignedPhysReg;
270 // VirtReg - The virtual register itself.
273 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
275 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
281 /// rewriteMBB - Keep track of which spills are available even after the
282 /// register allocator is done with them. If possible, avoid reloading vregs.
283 void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
285 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
286 // register values that are still available, due to being loaded to stored to,
287 // but not invalidated yet.
288 std::map<int, unsigned> SpillSlotsAvailable;
290 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
291 // which physregs are in use holding a stack slot value.
292 std::map<unsigned, int> PhysRegsAvailable;
294 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
296 std::vector<ReusedOp> ReusedOperands;
298 // DefAndUseVReg - When we see a def&use operand that is spilled, keep track
299 // of it. ".first" is the machine operand index (should always be 0 for now),
300 // and ".second" is the virtual register that is spilled.
301 std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg;
303 // MaybeDeadStores - When we need to write a value back into a stack slot,
304 // keep track of the inserted store. If the stack slot value is never read
305 // (because the value was used from some available register, for example), and
306 // subsequently stored to, the original store is dead. This map keeps track
307 // of inserted stores that are not used. If we see a subsequent store to the
308 // same stack slot, the original store is deleted.
309 std::map<int, MachineInstr*> MaybeDeadStores;
311 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
313 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
315 MachineInstr &MI = *MII;
316 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
318 ReusedOperands.clear();
319 DefAndUseVReg.clear();
321 // Process all of the spilled uses and all non spilled reg references.
322 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
323 MachineOperand &MO = MI.getOperand(i);
324 if (!MO.isRegister() || MO.getReg() == 0)
325 continue; // Ignore non-register operands.
327 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
328 // Ignore physregs for spilling, but remember that it is used by this
330 PhysRegsUsed[MO.getReg()] = true;
334 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
335 "Not a virtual or a physical register?");
337 unsigned VirtReg = MO.getReg();
338 if (!VRM.hasStackSlot(VirtReg)) {
339 // This virtual register was assigned a physreg!
340 unsigned Phys = VRM.getPhys(VirtReg);
341 PhysRegsUsed[Phys] = true;
342 MI.SetMachineOperandReg(i, Phys);
346 // This virtual register is now known to be a spilled value.
348 continue; // Handle defs in the loop below (handle use&def here though)
350 // If this is both a def and a use, we need to emit a store to the
351 // stack slot after the instruction. Keep track of D&U operands
352 // because we are about to change it to a physreg here.
354 // Remember that this was a def-and-use operand, and that the
355 // stack slot is live after this instruction executes.
356 DefAndUseVReg.push_back(std::make_pair(i, VirtReg));
359 int StackSlot = VRM.getStackSlot(VirtReg);
362 // Check to see if this stack slot is available.
363 std::map<int, unsigned>::iterator SSI =
364 SpillSlotsAvailable.find(StackSlot);
365 if (SSI != SpillSlotsAvailable.end()) {
366 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
367 << MRI->getName(SSI->second) << " for vreg"
368 << VirtReg <<" instead of reloading into physreg "
369 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
370 // If this stack slot value is already available, reuse it!
371 PhysReg = SSI->second;
372 MI.SetMachineOperandReg(i, PhysReg);
374 // The only technical detail we have is that we don't know that
375 // PhysReg won't be clobbered by a reloaded stack slot that occurs
376 // later in the instruction. In particular, consider 'op V1, V2'.
377 // If V1 is available in physreg R0, we would choose to reuse it
378 // here, instead of reloading it into the register the allocator
379 // indicated (say R1). However, V2 might have to be reloaded
380 // later, and it might indicate that it needs to live in R0. When
381 // this occurs, we need to have information available that
382 // indicates it is safe to use R1 for the reload instead of R0.
384 // To further complicate matters, we might conflict with an alias,
385 // or R0 and R1 might not be compatible with each other. In this
386 // case, we actually insert a reload for V1 in R1, ensuring that
387 // we can get at R0 or its alias.
388 ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
389 VRM.getPhys(VirtReg), VirtReg));
394 // Otherwise, reload it and remember that we have it.
395 PhysReg = VRM.getPhys(VirtReg);
396 const TargetRegisterClass* RC =
397 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
400 // Note that, if we reused a register for a previous operand, the
401 // register we want to reload into might not actually be
402 // available. If this occurs, use the register indicated by the
404 if (!ReusedOperands.empty()) // This is most often empty.
405 for (unsigned ro = 0, e = ReusedOperands.size(); ro != e; ++ro)
406 if (ReusedOperands[ro].PhysRegReused == PhysReg) {
407 // Yup, use the reload register that we didn't use before.
408 PhysReg = ReusedOperands[ro].AssignedPhysReg;
409 goto RecheckRegister;
411 ReusedOp &Op = ReusedOperands[ro];
412 unsigned PRRU = Op.PhysRegReused;
413 if (MRI->areAliases(PRRU, PhysReg)) {
414 // Okay, we found out that an alias of a reused register
415 // was used. This isn't good because it means we have
416 // to undo a previous reuse.
417 const TargetRegisterClass *AliasRC =
418 MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
419 MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
420 Op.StackSlot, AliasRC);
421 ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
424 // Any stores to this stack slot are not dead anymore.
425 MaybeDeadStores.erase(Op.StackSlot);
427 MI.SetMachineOperandReg(Op.Operand, Op.AssignedPhysReg);
428 PhysRegsAvailable[Op.AssignedPhysReg] = Op.StackSlot;
429 SpillSlotsAvailable[Op.StackSlot] = Op.AssignedPhysReg;
430 PhysRegsAvailable.erase(Op.PhysRegReused);
431 DEBUG(std::cerr << "Remembering SS#" << Op.StackSlot
433 << MRI->getName(Op.AssignedPhysReg) << "\n");
435 DEBUG(std::cerr << '\t' << *prior(MII));
437 DEBUG(std::cerr << "Reuse undone!\n");
438 ReusedOperands.erase(ReusedOperands.begin()+ro);
444 PhysRegsUsed[PhysReg] = true;
445 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
446 // This invalidates PhysReg.
447 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
449 // Any stores to this stack slot are not dead anymore.
450 MaybeDeadStores.erase(StackSlot);
452 MI.SetMachineOperandReg(i, PhysReg);
453 PhysRegsAvailable[PhysReg] = StackSlot;
454 SpillSlotsAvailable[StackSlot] = PhysReg;
455 DEBUG(std::cerr << "Remembering SS#" << StackSlot <<" in physreg "
456 << MRI->getName(PhysReg) << "\n");
458 DEBUG(std::cerr << '\t' << *prior(MII));
461 // Loop over all of the implicit defs, clearing them from our available
463 for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
465 PhysRegsUsed[*ImpDef] = true;
466 ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable);
469 DEBUG(std::cerr << '\t' << MI);
471 // If we have folded references to memory operands, make sure we clear all
472 // physical registers that may contain the value of the spilled virtual
474 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
475 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
476 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
477 << I->second.second);
478 unsigned VirtReg = I->second.first;
479 VirtRegMap::ModRef MR = I->second.second;
480 if (!VRM.hasStackSlot(VirtReg)) {
481 DEBUG(std::cerr << ": No stack slot!\n");
484 int SS = VRM.getStackSlot(VirtReg);
485 DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
487 // If this folded instruction is just a use, check to see if it's a
488 // straight load from the virt reg slot.
489 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
491 if (unsigned DestReg = MRI->isLoadFromStackSlot(&MI, FrameIdx)) {
492 // If this spill slot is available, insert a copy for it!
493 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS);
494 if (FrameIdx == SS && It != SpillSlotsAvailable.end()) {
495 DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
496 MachineFunction &MF = *MBB.getParent();
497 if (DestReg != It->second) {
498 MRI->copyRegToReg(MBB, &MI, DestReg, It->second,
499 MF.getSSARegMap()->getRegClass(VirtReg));
500 // Revisit the copy so we make sure to notice the effects of the
501 // operation on the destreg (either needing to RA it if it's
502 // virtual or needing to clobber any values if it's physical).
504 --NextMII; // backtrack to the copy.
507 goto ProcessNextInst;
512 // If this reference is not a use, any previous store is now dead.
513 // Otherwise, the store to this stack slot is not dead anymore.
514 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
515 if (MDSI != MaybeDeadStores.end()) {
516 if (MR & VirtRegMap::isRef) // Previous store is not dead.
517 MaybeDeadStores.erase(MDSI);
519 // If we get here, the store is dead, nuke it now.
520 assert(MR == VirtRegMap::isMod && "Can't be modref!");
521 MBB.erase(MDSI->second);
522 MaybeDeadStores.erase(MDSI);
527 // If the spill slot value is available, and this is a new definition of
528 // the value, the value is not available anymore.
529 if (MR & VirtRegMap::isMod) {
530 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS);
531 if (It != SpillSlotsAvailable.end()) {
532 PhysRegsAvailable.erase(It->second);
533 SpillSlotsAvailable.erase(It);
538 // Process all of the spilled defs.
539 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
540 MachineOperand &MO = MI.getOperand(i);
541 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
542 unsigned VirtReg = MO.getReg();
544 bool TakenCareOf = false;
545 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
546 // Check to see if this is a def-and-use vreg operand that we do need
547 // to insert a store for.
548 bool OpTakenCareOf = false;
549 if (MO.isUse() && !DefAndUseVReg.empty()) {
550 for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau)
551 if (DefAndUseVReg[dau].first == i) {
552 VirtReg = DefAndUseVReg[dau].second;
553 OpTakenCareOf = true;
558 if (!OpTakenCareOf) {
559 ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable);
565 // The only vregs left are stack slot definitions.
566 int StackSlot = VRM.getStackSlot(VirtReg);
567 const TargetRegisterClass *RC =
568 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
571 // If this is a def&use operand, and we used a different physreg for
572 // it than the one assigned, make sure to execute the store from the
573 // correct physical register.
574 if (MO.getReg() == VirtReg)
575 PhysReg = VRM.getPhys(VirtReg);
577 PhysReg = MO.getReg();
579 PhysRegsUsed[PhysReg] = true;
580 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
581 DEBUG(std::cerr << "Store:\t" << *next(MII));
582 MI.SetMachineOperandReg(i, PhysReg);
584 // If there is a dead store to this stack slot, nuke it now.
585 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
587 DEBUG(std::cerr << " Killed store:\t" << *LastStore);
589 MBB.erase(LastStore);
591 LastStore = next(MII);
593 // If the stack slot value was previously available in some other
594 // register, change it now. Otherwise, make the register available,
596 std::map<int, unsigned>::iterator SSA =
597 SpillSlotsAvailable.find(StackSlot);
598 if (SSA != SpillSlotsAvailable.end()) {
599 // Remove the record for physreg.
600 PhysRegsAvailable.erase(SSA->second);
601 SpillSlotsAvailable.erase(SSA);
603 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
605 PhysRegsAvailable[PhysReg] = StackSlot;
606 SpillSlotsAvailable[StackSlot] = PhysReg;
607 DEBUG(std::cerr << "Updating SS#" << StackSlot <<" in physreg "
608 << MRI->getName(PhysReg) << " for virtreg #"
623 llvm::Spiller* llvm::createSpiller() {
624 switch (SpillerOpt) {
625 default: assert(0 && "Unreachable!");
627 return new LocalSpiller();
629 return new SimpleSpiller();