1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "spiller"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/ADT/SmallSet.h"
37 STATISTIC(NumSpills, "Number of register spills");
38 STATISTIC(NumPSpills,"Number of physical register spills");
39 STATISTIC(NumReMats, "Number of re-materialization");
40 STATISTIC(NumDRM , "Number of re-materializable defs elided");
41 STATISTIC(NumStores, "Number of stores added");
42 STATISTIC(NumLoads , "Number of loads added");
43 STATISTIC(NumReused, "Number of values reused");
44 STATISTIC(NumDSE , "Number of dead stores elided");
45 STATISTIC(NumDCE , "Number of copies elided");
46 STATISTIC(NumDSS , "Number of dead spill slots removed");
49 enum SpillerName { simple, local };
51 static cl::opt<SpillerName>
53 cl::desc("Spiller to use: (default: local)"),
55 cl::values(clEnumVal(simple, " simple spiller"),
56 clEnumVal(local, " local spiller"),
61 //===----------------------------------------------------------------------===//
62 // VirtRegMap implementation
63 //===----------------------------------------------------------------------===//
65 VirtRegMap::VirtRegMap(MachineFunction &mf)
66 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
67 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
68 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
69 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1),
70 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) {
71 SpillSlotToUsesMap.resize(8);
75 void VirtRegMap::grow() {
76 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
77 Virt2PhysMap.grow(LastVirtReg);
78 Virt2StackSlotMap.grow(LastVirtReg);
79 Virt2ReMatIdMap.grow(LastVirtReg);
80 Virt2SplitMap.grow(LastVirtReg);
81 Virt2SplitKillMap.grow(LastVirtReg);
82 ReMatMap.grow(LastVirtReg);
85 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
86 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
87 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
88 "attempt to assign stack slot to already spilled register");
89 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
90 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
92 if (LowSpillSlot == NO_STACK_SLOT)
94 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
96 unsigned Idx = SS-LowSpillSlot;
97 while (Idx >= SpillSlotToUsesMap.size())
98 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
99 Virt2StackSlotMap[virtReg] = SS;
104 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
105 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
106 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
107 "attempt to assign stack slot to already spilled register");
109 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) &&
110 "illegal fixed frame index");
111 Virt2StackSlotMap[virtReg] = SS;
114 int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
115 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
116 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
117 "attempt to assign re-mat id to already spilled register");
118 Virt2ReMatIdMap[virtReg] = ReMatId;
122 void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
123 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
124 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
125 "attempt to assign re-mat id to already spilled register");
126 Virt2ReMatIdMap[virtReg] = id;
129 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
130 std::map<const TargetRegisterClass*, int>::iterator I =
131 EmergencySpillSlots.find(RC);
132 if (I != EmergencySpillSlots.end())
134 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
136 if (LowSpillSlot == NO_STACK_SLOT)
138 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
144 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
145 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) {
146 assert(FI >= 0 && "Spill slot index should not be negative!");
147 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
151 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
152 MachineInstr *NewMI, ModRef MRInfo) {
153 // Move previous memory references folded to new instruction.
154 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
155 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
156 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
157 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
158 MI2VirtMap.erase(I++);
161 // add new memory reference
162 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
165 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
166 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
167 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
170 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
171 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
172 MachineOperand &MO = MI->getOperand(i);
173 if (!MO.isFrameIndex())
175 int FI = MO.getIndex();
176 if (MF.getFrameInfo()->isFixedObjectIndex(FI))
178 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
180 MI2VirtMap.erase(MI);
181 SpillPt2VirtMap.erase(MI);
182 RestorePt2VirtMap.erase(MI);
183 EmergencySpillMap.erase(MI);
186 void VirtRegMap::print(std::ostream &OS) const {
187 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
189 OS << "********** REGISTER MAP **********\n";
190 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
191 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
192 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
193 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
197 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
198 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
199 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
200 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
204 void VirtRegMap::dump() const {
209 //===----------------------------------------------------------------------===//
210 // Simple Spiller Implementation
211 //===----------------------------------------------------------------------===//
213 Spiller::~Spiller() {}
216 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
217 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
221 bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
222 DOUT << "********** REWRITE MACHINE CODE **********\n";
223 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
224 const TargetMachine &TM = MF.getTarget();
225 const TargetInstrInfo &TII = *TM.getInstrInfo();
228 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
229 // each vreg once (in the case where a spilled vreg is used by multiple
230 // operands). This is always smaller than the number of operands to the
231 // current machine instr, so it should be small.
232 std::vector<unsigned> LoadedRegs;
234 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
236 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
237 MachineBasicBlock &MBB = *MBBI;
238 for (MachineBasicBlock::iterator MII = MBB.begin(),
239 E = MBB.end(); MII != E; ++MII) {
240 MachineInstr &MI = *MII;
241 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
242 MachineOperand &MO = MI.getOperand(i);
243 if (MO.isRegister() && MO.getReg()) {
244 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
245 unsigned VirtReg = MO.getReg();
246 unsigned PhysReg = VRM.getPhys(VirtReg);
247 if (!VRM.isAssignedReg(VirtReg)) {
248 int StackSlot = VRM.getStackSlot(VirtReg);
249 const TargetRegisterClass* RC =
250 MF.getRegInfo().getRegClass(VirtReg);
253 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
254 == LoadedRegs.end()) {
255 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
256 MachineInstr *LoadMI = prior(MII);
257 VRM.addSpillSlotUse(StackSlot, LoadMI);
258 LoadedRegs.push_back(VirtReg);
260 DOUT << '\t' << *LoadMI;
264 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
266 MachineInstr *StoreMI = next(MII);
267 VRM.addSpillSlotUse(StackSlot, StoreMI);
271 MF.getRegInfo().setPhysRegUsed(PhysReg);
272 MI.getOperand(i).setReg(PhysReg);
274 MF.getRegInfo().setPhysRegUsed(MO.getReg());
286 //===----------------------------------------------------------------------===//
287 // Local Spiller Implementation
288 //===----------------------------------------------------------------------===//
291 class AvailableSpills;
293 /// LocalSpiller - This spiller does a simple pass over the machine basic
294 /// block to attempt to keep spills in registers as much as possible for
295 /// blocks that have low register pressure (the vreg may be spilled due to
296 /// register pressure in other blocks).
297 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
298 MachineRegisterInfo *RegInfo;
299 const TargetRegisterInfo *TRI;
300 const TargetInstrInfo *TII;
302 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
303 RegInfo = &MF.getRegInfo();
304 TRI = MF.getTarget().getRegisterInfo();
305 TII = MF.getTarget().getInstrInfo();
306 DOUT << "\n**** Local spiller rewriting function '"
307 << MF.getFunction()->getName() << "':\n";
308 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
312 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
314 RewriteMBB(*MBB, VRM);
316 // Mark unused spill slots.
317 MachineFrameInfo *MFI = MF.getFrameInfo();
318 int SS = VRM.getLowSpillSlot();
319 if (SS != VirtRegMap::NO_STACK_SLOT)
320 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
321 if (!VRM.isSpillSlotUsed(SS)) {
322 MFI->RemoveStackObject(SS);
326 DOUT << "**** Post Machine Instrs ****\n";
332 bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator &MII,
334 std::vector<MachineInstr*> &MaybeDeadStores,
335 AvailableSpills &Spills, BitVector &RegKills,
336 std::vector<MachineOperand*> &KillOps,
338 void SpillRegToStackSlot(MachineBasicBlock &MBB,
339 MachineBasicBlock::iterator &MII,
340 int Idx, unsigned PhysReg, int StackSlot,
341 const TargetRegisterClass *RC,
342 bool isAvailable, MachineInstr *&LastStore,
343 AvailableSpills &Spills,
344 SmallSet<MachineInstr*, 4> &ReMatDefs,
346 std::vector<MachineOperand*> &KillOps,
348 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
352 /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
353 /// top down, keep track of which spills slots or remat are available in each
356 /// Note that not all physregs are created equal here. In particular, some
357 /// physregs are reloads that we are allowed to clobber or ignore at any time.
358 /// Other physregs are values that the register allocated program is using that
359 /// we cannot CHANGE, but we can read if we like. We keep track of this on a
360 /// per-stack-slot / remat id basis as the low bit in the value of the
361 /// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
362 /// this bit and addAvailable sets it if.
364 class VISIBILITY_HIDDEN AvailableSpills {
365 const TargetRegisterInfo *TRI;
366 const TargetInstrInfo *TII;
368 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
369 // or remat'ed virtual register values that are still available, due to being
370 // loaded or stored to, but not invalidated yet.
371 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
373 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
374 // indicating which stack slot values are currently held by a physreg. This
375 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
376 // physreg is modified.
377 std::multimap<unsigned, int> PhysRegsAvailable;
379 void disallowClobberPhysRegOnly(unsigned PhysReg);
381 void ClobberPhysRegOnly(unsigned PhysReg);
383 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
384 : TRI(tri), TII(tii) {
387 const TargetRegisterInfo *getRegInfo() const { return TRI; }
389 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
390 /// available in a physical register, return that PhysReg, otherwise
392 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
393 std::map<int, unsigned>::const_iterator I =
394 SpillSlotsOrReMatsAvailable.find(Slot);
395 if (I != SpillSlotsOrReMatsAvailable.end()) {
396 return I->second >> 1; // Remove the CanClobber bit.
401 /// addAvailable - Mark that the specified stack slot / remat is available in
402 /// the specified physreg. If CanClobber is true, the physreg can be modified
403 /// at any time without changing the semantics of the program.
404 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
405 bool CanClobber = true) {
406 // If this stack slot is thought to be available in some other physreg,
407 // remove its record.
408 ModifyStackSlotOrReMat(SlotOrReMat);
410 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
411 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
413 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
414 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
416 DOUT << "Remembering SS#" << SlotOrReMat;
417 DOUT << " in physreg " << TRI->getName(Reg) << "\n";
420 /// canClobberPhysReg - Return true if the spiller is allowed to change the
421 /// value of the specified stackslot register if it desires. The specified
422 /// stack slot must be available in a physreg for this query to make sense.
423 bool canClobberPhysReg(int SlotOrReMat) const {
424 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
425 "Value not available!");
426 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
429 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
430 /// stackslot register. The register is still available but is no longer
431 /// allowed to be modifed.
432 void disallowClobberPhysReg(unsigned PhysReg);
434 /// ClobberPhysReg - This is called when the specified physreg changes
435 /// value. We use this to invalidate any info about stuff that lives in
436 /// it and any of its aliases.
437 void ClobberPhysReg(unsigned PhysReg);
439 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
440 /// slot changes. This removes information about which register the previous
441 /// value for this slot lives in (as the previous value is dead now).
442 void ModifyStackSlotOrReMat(int SlotOrReMat);
446 /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
447 /// stackslot register. The register is still available but is no longer
448 /// allowed to be modifed.
449 void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
450 std::multimap<unsigned, int>::iterator I =
451 PhysRegsAvailable.lower_bound(PhysReg);
452 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
453 int SlotOrReMat = I->second;
455 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
456 "Bidirectional map mismatch!");
457 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
458 DOUT << "PhysReg " << TRI->getName(PhysReg)
459 << " copied, it is available for use but can no longer be modified\n";
463 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
464 /// stackslot register and its aliases. The register and its aliases may
465 /// still available but is no longer allowed to be modifed.
466 void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
467 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
468 disallowClobberPhysRegOnly(*AS);
469 disallowClobberPhysRegOnly(PhysReg);
472 /// ClobberPhysRegOnly - This is called when the specified physreg changes
473 /// value. We use this to invalidate any info about stuff we thing lives in it.
474 void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
475 std::multimap<unsigned, int>::iterator I =
476 PhysRegsAvailable.lower_bound(PhysReg);
477 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
478 int SlotOrReMat = I->second;
479 PhysRegsAvailable.erase(I++);
480 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
481 "Bidirectional map mismatch!");
482 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
483 DOUT << "PhysReg " << TRI->getName(PhysReg)
484 << " clobbered, invalidating ";
485 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
486 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
488 DOUT << "SS#" << SlotOrReMat << "\n";
492 /// ClobberPhysReg - This is called when the specified physreg changes
493 /// value. We use this to invalidate any info about stuff we thing lives in
494 /// it and any of its aliases.
495 void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
496 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
497 ClobberPhysRegOnly(*AS);
498 ClobberPhysRegOnly(PhysReg);
501 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
502 /// slot changes. This removes information about which register the previous
503 /// value for this slot lives in (as the previous value is dead now).
504 void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
505 std::map<int, unsigned>::iterator It =
506 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
507 if (It == SpillSlotsOrReMatsAvailable.end()) return;
508 unsigned Reg = It->second >> 1;
509 SpillSlotsOrReMatsAvailable.erase(It);
511 // This register may hold the value of multiple stack slots, only remove this
512 // stack slot from the set of values the register contains.
513 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
515 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
516 "Map inverse broken!");
517 if (I->second == SlotOrReMat) break;
519 PhysRegsAvailable.erase(I);
524 /// InvalidateKills - MI is going to be deleted. If any of its operands are
525 /// marked kill, then invalidate the information.
526 static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
527 std::vector<MachineOperand*> &KillOps,
528 SmallVector<unsigned, 2> *KillRegs = NULL) {
529 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
530 MachineOperand &MO = MI.getOperand(i);
531 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
533 unsigned Reg = MO.getReg();
535 KillRegs->push_back(Reg);
536 if (KillOps[Reg] == &MO) {
543 /// InvalidateKill - A MI that defines the specified register is being deleted,
544 /// invalidate the register kill information.
545 static void InvalidateKill(unsigned Reg, BitVector &RegKills,
546 std::vector<MachineOperand*> &KillOps) {
548 KillOps[Reg]->setIsKill(false);
554 /// InvalidateRegDef - If the def operand of the specified def MI is now dead
555 /// (since it's spill instruction is removed), mark it isDead. Also checks if
556 /// the def MI has other definition operands that are not dead. Returns it by
558 static bool InvalidateRegDef(MachineBasicBlock::iterator I,
559 MachineInstr &NewDef, unsigned Reg,
561 // Due to remat, it's possible this reg isn't being reused. That is,
562 // the def of this reg (by prev MI) is now dead.
563 MachineInstr *DefMI = I;
564 MachineOperand *DefOp = NULL;
565 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
566 MachineOperand &MO = DefMI->getOperand(i);
567 if (MO.isRegister() && MO.isDef()) {
568 if (MO.getReg() == Reg)
570 else if (!MO.isDead())
577 bool FoundUse = false, Done = false;
578 MachineBasicBlock::iterator E = NewDef;
580 for (; !Done && I != E; ++I) {
581 MachineInstr *NMI = I;
582 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
583 MachineOperand &MO = NMI->getOperand(j);
584 if (!MO.isRegister() || MO.getReg() != Reg)
588 Done = true; // Stop after scanning all the operands of this MI.
599 /// UpdateKills - Track and update kill info. If a MI reads a register that is
600 /// marked kill, then it must be due to register reuse. Transfer the kill info
602 static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
603 std::vector<MachineOperand*> &KillOps) {
604 const TargetInstrDesc &TID = MI.getDesc();
605 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
606 MachineOperand &MO = MI.getOperand(i);
607 if (!MO.isRegister() || !MO.isUse())
609 unsigned Reg = MO.getReg();
614 // That can't be right. Register is killed but not re-defined and it's
615 // being reused. Let's fix that.
616 KillOps[Reg]->setIsKill(false);
619 if (i < TID.getNumOperands() &&
620 TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
621 // Unless it's a two-address operand, this is the new kill.
630 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
631 const MachineOperand &MO = MI.getOperand(i);
632 if (!MO.isRegister() || !MO.isDef())
634 unsigned Reg = MO.getReg();
640 /// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
642 static void ReMaterialize(MachineBasicBlock &MBB,
643 MachineBasicBlock::iterator &MII,
644 unsigned DestReg, unsigned Reg,
645 const TargetRegisterInfo *TRI,
647 TRI->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
648 MachineInstr *NewMI = prior(MII);
649 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
650 MachineOperand &MO = NewMI->getOperand(i);
651 if (!MO.isRegister() || MO.getReg() == 0)
653 unsigned VirtReg = MO.getReg();
654 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
657 unsigned SubIdx = MO.getSubReg();
658 unsigned Phys = VRM.getPhys(VirtReg);
660 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
667 // ReusedOp - For each reused operand, we keep track of a bit of information, in
668 // case we need to rollback upon processing a new operand. See comments below.
671 // The MachineInstr operand that reused an available value.
674 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
675 unsigned StackSlotOrReMat;
677 // PhysRegReused - The physical register the value was available in.
678 unsigned PhysRegReused;
680 // AssignedPhysReg - The physreg that was assigned for use by the reload.
681 unsigned AssignedPhysReg;
683 // VirtReg - The virtual register itself.
686 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
688 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
689 AssignedPhysReg(apr), VirtReg(vreg) {}
692 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
693 /// is reused instead of reloaded.
694 class VISIBILITY_HIDDEN ReuseInfo {
696 std::vector<ReusedOp> Reuses;
697 BitVector PhysRegsClobbered;
699 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
700 PhysRegsClobbered.resize(tri->getNumRegs());
703 bool hasReuses() const {
704 return !Reuses.empty();
707 /// addReuse - If we choose to reuse a virtual register that is already
708 /// available instead of reloading it, remember that we did so.
709 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
710 unsigned PhysRegReused, unsigned AssignedPhysReg,
712 // If the reload is to the assigned register anyway, no undo will be
714 if (PhysRegReused == AssignedPhysReg) return;
716 // Otherwise, remember this.
717 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
718 AssignedPhysReg, VirtReg));
721 void markClobbered(unsigned PhysReg) {
722 PhysRegsClobbered.set(PhysReg);
725 bool isClobbered(unsigned PhysReg) const {
726 return PhysRegsClobbered.test(PhysReg);
729 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
730 /// is some other operand that is using the specified register, either pick
731 /// a new register to use, or evict the previous reload and use this reg.
732 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
733 AvailableSpills &Spills,
734 std::vector<MachineInstr*> &MaybeDeadStores,
735 SmallSet<unsigned, 8> &Rejected,
737 std::vector<MachineOperand*> &KillOps,
739 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
742 if (Reuses.empty()) return PhysReg; // This is most often empty.
744 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
745 ReusedOp &Op = Reuses[ro];
746 // If we find some other reuse that was supposed to use this register
747 // exactly for its reload, we can change this reload to use ITS reload
748 // register. That is, unless its reload register has already been
749 // considered and subsequently rejected because it has also been reused
750 // by another operand.
751 if (Op.PhysRegReused == PhysReg &&
752 Rejected.count(Op.AssignedPhysReg) == 0) {
753 // Yup, use the reload register that we didn't use before.
754 unsigned NewReg = Op.AssignedPhysReg;
755 Rejected.insert(PhysReg);
756 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
757 RegKills, KillOps, VRM);
759 // Otherwise, we might also have a problem if a previously reused
760 // value aliases the new register. If so, codegen the previous reload
762 unsigned PRRU = Op.PhysRegReused;
763 const TargetRegisterInfo *TRI = Spills.getRegInfo();
764 if (TRI->areAliases(PRRU, PhysReg)) {
765 // Okay, we found out that an alias of a reused register
766 // was used. This isn't good because it means we have
767 // to undo a previous reuse.
768 MachineBasicBlock *MBB = MI->getParent();
769 const TargetRegisterClass *AliasRC =
770 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
772 // Copy Op out of the vector and remove it, we're going to insert an
773 // explicit load for it.
775 Reuses.erase(Reuses.begin()+ro);
777 // Ok, we're going to try to reload the assigned physreg into the
778 // slot that we were supposed to in the first place. However, that
779 // register could hold a reuse. Check to see if it conflicts or
780 // would prefer us to use a different register.
781 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
782 MI, Spills, MaybeDeadStores,
783 Rejected, RegKills, KillOps, VRM);
785 MachineBasicBlock::iterator MII = MI;
786 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
787 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TRI, VRM);
789 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
790 NewOp.StackSlotOrReMat, AliasRC);
791 MachineInstr *LoadMI = prior(MII);
792 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
793 // Any stores to this stack slot are not dead anymore.
794 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
797 Spills.ClobberPhysReg(NewPhysReg);
798 Spills.ClobberPhysReg(NewOp.PhysRegReused);
800 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
802 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
804 UpdateKills(*MII, RegKills, KillOps);
805 DOUT << '\t' << *MII;
807 DOUT << "Reuse undone!\n";
810 // Finally, PhysReg is now available, go ahead and use it.
818 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
819 /// 'Rejected' set to remember which registers have been considered and
820 /// rejected for the reload. This avoids infinite looping in case like
823 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
824 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
826 /// sees r1 is taken by t2, tries t2's reload register r0
827 /// sees r0 is taken by t3, tries t3's reload register r1
828 /// sees r1 is taken by t2, tries t2's reload register r0 ...
829 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
830 AvailableSpills &Spills,
831 std::vector<MachineInstr*> &MaybeDeadStores,
833 std::vector<MachineOperand*> &KillOps,
835 SmallSet<unsigned, 8> Rejected;
836 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
837 RegKills, KillOps, VRM);
842 /// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
843 /// instruction. e.g.
845 /// movl %eax, -32(%ebp)
846 /// movl -36(%ebp), %eax
847 /// orl %eax, -32(%ebp)
850 /// orl -36(%ebp), %eax
851 /// mov %eax, -32(%ebp)
852 /// This enables unfolding optimization for a subsequent instruction which will
853 /// also eliminate the newly introduced store instruction.
854 bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
855 MachineBasicBlock::iterator &MII,
856 std::vector<MachineInstr*> &MaybeDeadStores,
857 AvailableSpills &Spills,
859 std::vector<MachineOperand*> &KillOps,
861 MachineFunction &MF = *MBB.getParent();
862 MachineInstr &MI = *MII;
863 unsigned UnfoldedOpc = 0;
864 unsigned UnfoldPR = 0;
865 unsigned UnfoldVR = 0;
866 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
867 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
868 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
869 // Only transform a MI that folds a single register.
872 UnfoldVR = I->second.first;
873 VirtRegMap::ModRef MR = I->second.second;
874 if (VRM.isAssignedReg(UnfoldVR))
876 // If this reference is not a use, any previous store is now dead.
877 // Otherwise, the store to this stack slot is not dead anymore.
878 FoldedSS = VRM.getStackSlot(UnfoldVR);
879 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
880 if (DeadStore && (MR & VirtRegMap::isModRef)) {
881 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
882 if (!PhysReg || !DeadStore->readsRegister(PhysReg))
885 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
893 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
894 MachineOperand &MO = MI.getOperand(i);
895 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
897 unsigned VirtReg = MO.getReg();
898 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
900 if (VRM.isAssignedReg(VirtReg)) {
901 unsigned PhysReg = VRM.getPhys(VirtReg);
902 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
904 } else if (VRM.isReMaterialized(VirtReg))
906 int SS = VRM.getStackSlot(VirtReg);
907 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
909 if (TRI->regsOverlap(PhysReg, UnfoldPR))
913 PhysReg = VRM.getPhys(VirtReg);
914 if (!TRI->regsOverlap(PhysReg, UnfoldPR))
917 // Ok, we'll need to reload the value into a register which makes
918 // it impossible to perform the store unfolding optimization later.
919 // Let's see if it is possible to fold the load if the store is
920 // unfolded. This allows us to perform the store unfolding
922 SmallVector<MachineInstr*, 4> NewMIs;
923 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
924 assert(NewMIs.size() == 1);
925 MachineInstr *NewMI = NewMIs.back();
927 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
929 SmallVector<unsigned, 2> Ops;
931 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
933 VRM.addSpillSlotUse(SS, FoldedMI);
934 if (!VRM.hasPhys(UnfoldVR))
935 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
936 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
937 MII = MBB.insert(MII, FoldedMI);
938 VRM.RemoveMachineInstrFromMaps(&MI);
948 /// findSuperReg - Find the SubReg's super-register of given register class
949 /// where its SubIdx sub-register is SubReg.
950 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
951 unsigned SubIdx, const TargetRegisterInfo *TRI) {
952 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
955 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
961 /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
962 /// the last store to the same slot is now dead. If so, remove the last store.
963 void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
964 MachineBasicBlock::iterator &MII,
965 int Idx, unsigned PhysReg, int StackSlot,
966 const TargetRegisterClass *RC,
967 bool isAvailable, MachineInstr *&LastStore,
968 AvailableSpills &Spills,
969 SmallSet<MachineInstr*, 4> &ReMatDefs,
971 std::vector<MachineOperand*> &KillOps,
973 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
974 MachineInstr *StoreMI = next(MII);
975 VRM.addSpillSlotUse(StackSlot, StoreMI);
976 DOUT << "Store:\t" << *StoreMI;
978 // If there is a dead store to this stack slot, nuke it now.
980 DOUT << "Removed dead store:\t" << *LastStore;
982 SmallVector<unsigned, 2> KillRegs;
983 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
984 MachineBasicBlock::iterator PrevMII = LastStore;
985 bool CheckDef = PrevMII != MBB.begin();
988 VRM.RemoveMachineInstrFromMaps(LastStore);
989 MBB.erase(LastStore);
991 // Look at defs of killed registers on the store. Mark the defs
992 // as dead since the store has been deleted and they aren't
994 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
995 bool HasOtherDef = false;
996 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
997 MachineInstr *DeadDef = PrevMII;
998 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
999 // FIXME: This assumes a remat def does not have side
1001 VRM.RemoveMachineInstrFromMaps(DeadDef);
1010 LastStore = next(MII);
1012 // If the stack slot value was previously available in some other
1013 // register, change it now. Otherwise, make the register available,
1015 Spills.ModifyStackSlotOrReMat(StackSlot);
1016 Spills.ClobberPhysReg(PhysReg);
1017 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable);
1021 /// rewriteMBB - Keep track of which spills are available even after the
1022 /// register allocator is done with them. If possible, avid reloading vregs.
1023 void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
1024 DOUT << MBB.getBasicBlock()->getName() << ":\n";
1026 MachineFunction &MF = *MBB.getParent();
1028 // Spills - Keep track of which spilled values are available in physregs so
1029 // that we can choose to reuse the physregs instead of emitting reloads.
1030 AvailableSpills Spills(TRI, TII);
1032 // MaybeDeadStores - When we need to write a value back into a stack slot,
1033 // keep track of the inserted store. If the stack slot value is never read
1034 // (because the value was used from some available register, for example), and
1035 // subsequently stored to, the original store is dead. This map keeps track
1036 // of inserted stores that are not used. If we see a subsequent store to the
1037 // same stack slot, the original store is deleted.
1038 std::vector<MachineInstr*> MaybeDeadStores;
1039 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
1041 // ReMatDefs - These are rematerializable def MIs which are not deleted.
1042 SmallSet<MachineInstr*, 4> ReMatDefs;
1044 // Keep track of kill information.
1045 BitVector RegKills(TRI->getNumRegs());
1046 std::vector<MachineOperand*> KillOps;
1047 KillOps.resize(TRI->getNumRegs(), NULL);
1049 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
1051 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
1053 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1054 bool Erased = false;
1055 bool BackTracked = false;
1056 if (PrepForUnfoldOpti(MBB, MII,
1057 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
1058 NextMII = next(MII);
1060 MachineInstr &MI = *MII;
1061 const TargetInstrDesc &TID = MI.getDesc();
1063 if (VRM.hasEmergencySpills(&MI)) {
1064 // Spill physical register(s) in the rare case the allocator has run out
1065 // of registers to allocate.
1066 SmallSet<int, 4> UsedSS;
1067 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
1068 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
1069 unsigned PhysReg = EmSpills[i];
1070 const TargetRegisterClass *RC =
1071 TRI->getPhysicalRegisterRegClass(PhysReg);
1072 assert(RC && "Unable to determine register class!");
1073 int SS = VRM.getEmergencySpillSlot(RC);
1074 if (UsedSS.count(SS))
1075 assert(0 && "Need to spill more than one physical registers!");
1077 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
1078 MachineInstr *StoreMI = prior(MII);
1079 VRM.addSpillSlotUse(SS, StoreMI);
1080 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC);
1081 MachineInstr *LoadMI = next(MII);
1082 VRM.addSpillSlotUse(SS, LoadMI);
1087 // Insert restores here if asked to.
1088 if (VRM.isRestorePt(&MI)) {
1089 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
1090 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
1091 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
1092 if (!VRM.getPreSplitReg(VirtReg))
1093 continue; // Split interval spilled again.
1094 unsigned Phys = VRM.getPhys(VirtReg);
1095 RegInfo->setPhysRegUsed(Phys);
1096 if (VRM.isReMaterialized(VirtReg)) {
1097 ReMaterialize(MBB, MII, Phys, VirtReg, TRI, VRM);
1099 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1100 int SS = VRM.getStackSlot(VirtReg);
1101 TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC);
1102 MachineInstr *LoadMI = prior(MII);
1103 VRM.addSpillSlotUse(SS, LoadMI);
1106 // This invalidates Phys.
1107 Spills.ClobberPhysReg(Phys);
1108 UpdateKills(*prior(MII), RegKills, KillOps);
1109 DOUT << '\t' << *prior(MII);
1113 // Insert spills here if asked to.
1114 if (VRM.isSpillPt(&MI)) {
1115 std::vector<std::pair<unsigned,bool> > &SpillRegs =
1116 VRM.getSpillPtSpills(&MI);
1117 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
1118 unsigned VirtReg = SpillRegs[i].first;
1119 bool isKill = SpillRegs[i].second;
1120 if (!VRM.getPreSplitReg(VirtReg))
1121 continue; // Split interval spilled again.
1122 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1123 unsigned Phys = VRM.getPhys(VirtReg);
1124 int StackSlot = VRM.getStackSlot(VirtReg);
1125 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
1126 MachineInstr *StoreMI = next(MII);
1127 VRM.addSpillSlotUse(StackSlot, StoreMI);
1128 DOUT << "Store:\t" << StoreMI;
1129 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1131 NextMII = next(MII);
1134 /// ReusedOperands - Keep track of operand reuse in case we need to undo
1136 ReuseInfo ReusedOperands(MI, TRI);
1137 SmallVector<unsigned, 4> VirtUseOps;
1138 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1139 MachineOperand &MO = MI.getOperand(i);
1140 if (!MO.isRegister() || MO.getReg() == 0)
1141 continue; // Ignore non-register operands.
1143 unsigned VirtReg = MO.getReg();
1144 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
1145 // Ignore physregs for spilling, but remember that it is used by this
1147 RegInfo->setPhysRegUsed(VirtReg);
1151 // We want to process implicit virtual register uses first.
1152 if (MO.isImplicit())
1153 VirtUseOps.insert(VirtUseOps.begin(), i);
1155 VirtUseOps.push_back(i);
1158 // Process all of the spilled uses and all non spilled reg references.
1159 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
1160 unsigned i = VirtUseOps[j];
1161 MachineOperand &MO = MI.getOperand(i);
1162 unsigned VirtReg = MO.getReg();
1163 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
1164 "Not a virtual register?");
1166 unsigned SubIdx = MO.getSubReg();
1167 if (VRM.isAssignedReg(VirtReg)) {
1168 // This virtual register was assigned a physreg!
1169 unsigned Phys = VRM.getPhys(VirtReg);
1170 RegInfo->setPhysRegUsed(Phys);
1172 ReusedOperands.markClobbered(Phys);
1173 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
1174 MI.getOperand(i).setReg(RReg);
1178 // This virtual register is now known to be a spilled value.
1180 continue; // Handle defs in the loop below (handle use&def here though)
1182 bool DoReMat = VRM.isReMaterialized(VirtReg);
1183 int SSorRMId = DoReMat
1184 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1185 int ReuseSlot = SSorRMId;
1187 // Check to see if this stack slot is available.
1188 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1190 // If this is a sub-register use, make sure the reuse register is in the
1191 // right register class. For example, for x86 not all of the 32-bit
1192 // registers have accessible sub-registers.
1193 // Similarly so for EXTRACT_SUBREG. Consider this:
1195 // MOV32_mr fi#1, EDI
1197 // = EXTRACT_SUBREG fi#1
1198 // fi#1 is available in EDI, but it cannot be reused because it's not in
1199 // the right register file.
1201 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
1202 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1203 if (!RC->contains(PhysReg))
1208 // This spilled operand might be part of a two-address operand. If this
1209 // is the case, then changing it will necessarily require changing the
1210 // def part of the instruction as well. However, in some cases, we
1211 // aren't allowed to modify the reused register. If none of these cases
1213 bool CanReuse = true;
1214 int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
1216 MI.getOperand(ti).isRegister() &&
1217 MI.getOperand(ti).getReg() == VirtReg) {
1218 // Okay, we have a two address operand. We can reuse this physreg as
1219 // long as we are allowed to clobber the value and there isn't an
1220 // earlier def that has already clobbered the physreg.
1221 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
1222 !ReusedOperands.isClobbered(PhysReg);
1226 // If this stack slot value is already available, reuse it!
1227 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1228 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
1230 DOUT << "Reusing SS#" << ReuseSlot;
1231 DOUT << " from physreg "
1232 << TRI->getName(PhysReg) << " for vreg"
1233 << VirtReg <<" instead of reloading into physreg "
1234 << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
1235 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1236 MI.getOperand(i).setReg(RReg);
1238 // The only technical detail we have is that we don't know that
1239 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1240 // later in the instruction. In particular, consider 'op V1, V2'.
1241 // If V1 is available in physreg R0, we would choose to reuse it
1242 // here, instead of reloading it into the register the allocator
1243 // indicated (say R1). However, V2 might have to be reloaded
1244 // later, and it might indicate that it needs to live in R0. When
1245 // this occurs, we need to have information available that
1246 // indicates it is safe to use R1 for the reload instead of R0.
1248 // To further complicate matters, we might conflict with an alias,
1249 // or R0 and R1 might not be compatible with each other. In this
1250 // case, we actually insert a reload for V1 in R1, ensuring that
1251 // we can get at R0 or its alias.
1252 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
1253 VRM.getPhys(VirtReg), VirtReg);
1255 // Only mark it clobbered if this is a use&def operand.
1256 ReusedOperands.markClobbered(PhysReg);
1259 if (MI.getOperand(i).isKill() &&
1260 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1261 // This was the last use and the spilled value is still available
1262 // for reuse. That means the spill was unnecessary!
1263 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
1265 DOUT << "Removed dead store:\t" << *DeadStore;
1266 InvalidateKills(*DeadStore, RegKills, KillOps);
1267 VRM.RemoveMachineInstrFromMaps(DeadStore);
1268 MBB.erase(DeadStore);
1269 MaybeDeadStores[ReuseSlot] = NULL;
1276 // Otherwise we have a situation where we have a two-address instruction
1277 // whose mod/ref operand needs to be reloaded. This reload is already
1278 // available in some register "PhysReg", but if we used PhysReg as the
1279 // operand to our 2-addr instruction, the instruction would modify
1280 // PhysReg. This isn't cool if something later uses PhysReg and expects
1281 // to get its initial value.
1283 // To avoid this problem, and to avoid doing a load right after a store,
1284 // we emit a copy from PhysReg into the designated register for this
1286 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1287 assert(DesignatedReg && "Must map virtreg to physreg!");
1289 // Note that, if we reused a register for a previous operand, the
1290 // register we want to reload into might not actually be
1291 // available. If this occurs, use the register indicated by the
1293 if (ReusedOperands.hasReuses())
1294 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
1295 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1297 // If the mapped designated register is actually the physreg we have
1298 // incoming, we don't need to inserted a dead copy.
1299 if (DesignatedReg == PhysReg) {
1300 // If this stack slot value is already available, reuse it!
1301 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1302 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
1304 DOUT << "Reusing SS#" << ReuseSlot;
1305 DOUT << " from physreg " << TRI->getName(PhysReg)
1306 << " for vreg" << VirtReg
1307 << " instead of reloading into same physreg.\n";
1308 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1309 MI.getOperand(i).setReg(RReg);
1310 ReusedOperands.markClobbered(RReg);
1315 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1316 RegInfo->setPhysRegUsed(DesignatedReg);
1317 ReusedOperands.markClobbered(DesignatedReg);
1318 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
1320 MachineInstr *CopyMI = prior(MII);
1321 UpdateKills(*CopyMI, RegKills, KillOps);
1323 // This invalidates DesignatedReg.
1324 Spills.ClobberPhysReg(DesignatedReg);
1326 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
1328 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
1329 MI.getOperand(i).setReg(RReg);
1330 DOUT << '\t' << *prior(MII);
1335 // Otherwise, reload it and remember that we have it.
1336 PhysReg = VRM.getPhys(VirtReg);
1337 assert(PhysReg && "Must map virtreg to physreg!");
1339 // Note that, if we reused a register for a previous operand, the
1340 // register we want to reload into might not actually be
1341 // available. If this occurs, use the register indicated by the
1343 if (ReusedOperands.hasReuses())
1344 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1345 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1347 RegInfo->setPhysRegUsed(PhysReg);
1348 ReusedOperands.markClobbered(PhysReg);
1350 ReMaterialize(MBB, MII, PhysReg, VirtReg, TRI, VRM);
1352 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1353 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
1354 MachineInstr *LoadMI = prior(MII);
1355 VRM.addSpillSlotUse(SSorRMId, LoadMI);
1358 // This invalidates PhysReg.
1359 Spills.ClobberPhysReg(PhysReg);
1361 // Any stores to this stack slot are not dead anymore.
1363 MaybeDeadStores[SSorRMId] = NULL;
1364 Spills.addAvailable(SSorRMId, &MI, PhysReg);
1365 // Assumes this is the last use. IsKill will be unset if reg is reused
1366 // unless it's a two-address operand.
1367 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
1368 MI.getOperand(i).setIsKill();
1369 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1370 MI.getOperand(i).setReg(RReg);
1371 UpdateKills(*prior(MII), RegKills, KillOps);
1372 DOUT << '\t' << *prior(MII);
1378 // If we have folded references to memory operands, make sure we clear all
1379 // physical registers that may contain the value of the spilled virtual
1381 SmallSet<int, 2> FoldedSS;
1382 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
1383 unsigned VirtReg = I->second.first;
1384 VirtRegMap::ModRef MR = I->second.second;
1385 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR;
1387 int SS = VRM.getStackSlot(VirtReg);
1388 if (SS == VirtRegMap::NO_STACK_SLOT)
1390 FoldedSS.insert(SS);
1391 DOUT << " - StackSlot: " << SS << "\n";
1393 // If this folded instruction is just a use, check to see if it's a
1394 // straight load from the virt reg slot.
1395 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1397 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1398 if (DestReg && FrameIdx == SS) {
1399 // If this spill slot is available, turn it into a copy (or nothing)
1400 // instead of leaving it as a load!
1401 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1402 DOUT << "Promoted Load To Copy: " << MI;
1403 if (DestReg != InReg) {
1404 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1405 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
1406 // Revisit the copy so we make sure to notice the effects of the
1407 // operation on the destreg (either needing to RA it if it's
1408 // virtual or needing to clobber any values if it's physical).
1410 --NextMII; // backtrack to the copy.
1413 DOUT << "Removing now-noop copy: " << MI;
1414 // Unset last kill since it's being reused.
1415 InvalidateKill(InReg, RegKills, KillOps);
1418 VRM.RemoveMachineInstrFromMaps(&MI);
1421 goto ProcessNextInst;
1424 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1425 SmallVector<MachineInstr*, 4> NewMIs;
1427 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
1428 MBB.insert(MII, NewMIs[0]);
1429 VRM.RemoveMachineInstrFromMaps(&MI);
1432 --NextMII; // backtrack to the unfolded instruction.
1434 goto ProcessNextInst;
1439 // If this reference is not a use, any previous store is now dead.
1440 // Otherwise, the store to this stack slot is not dead anymore.
1441 MachineInstr* DeadStore = MaybeDeadStores[SS];
1443 bool isDead = !(MR & VirtRegMap::isRef);
1444 MachineInstr *NewStore = NULL;
1445 if (MR & VirtRegMap::isModRef) {
1446 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1447 SmallVector<MachineInstr*, 4> NewMIs;
1448 // We can reuse this physreg as long as we are allowed to clobber
1449 // the value and there isn't an earlier def that has already clobbered
1452 !TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
1453 DeadStore->killsRegister(PhysReg) &&
1454 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
1455 MBB.insert(MII, NewMIs[0]);
1456 NewStore = NewMIs[1];
1457 MBB.insert(MII, NewStore);
1458 VRM.addSpillSlotUse(SS, NewStore);
1459 VRM.RemoveMachineInstrFromMaps(&MI);
1463 --NextMII; // backtrack to the unfolded instruction.
1469 if (isDead) { // Previous store is dead.
1470 // If we get here, the store is dead, nuke it now.
1471 DOUT << "Removed dead store:\t" << *DeadStore;
1472 InvalidateKills(*DeadStore, RegKills, KillOps);
1473 VRM.RemoveMachineInstrFromMaps(DeadStore);
1474 MBB.erase(DeadStore);
1479 MaybeDeadStores[SS] = NULL;
1481 // Treat this store as a spill merged into a copy. That makes the
1482 // stack slot value available.
1483 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
1484 goto ProcessNextInst;
1488 // If the spill slot value is available, and this is a new definition of
1489 // the value, the value is not available anymore.
1490 if (MR & VirtRegMap::isMod) {
1491 // Notice that the value in this stack slot has been modified.
1492 Spills.ModifyStackSlotOrReMat(SS);
1494 // If this is *just* a mod of the value, check to see if this is just a
1495 // store to the spill slot (i.e. the spill got merged into the copy). If
1496 // so, realize that the vreg is available now, and add the store to the
1497 // MaybeDeadStore info.
1499 if (!(MR & VirtRegMap::isRef)) {
1500 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1501 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1502 "Src hasn't been allocated yet?");
1503 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
1504 // this as a potentially dead store in case there is a subsequent
1505 // store into the stack slot without a read from it.
1506 MaybeDeadStores[StackSlot] = &MI;
1508 // If the stack slot value was previously available in some other
1509 // register, change it now. Otherwise, make the register available,
1511 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
1517 // Process all of the spilled defs.
1518 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1519 MachineOperand &MO = MI.getOperand(i);
1520 if (!(MO.isRegister() && MO.getReg() && MO.isDef()))
1523 unsigned VirtReg = MO.getReg();
1524 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1525 // Check to see if this is a noop copy. If so, eliminate the
1526 // instruction before considering the dest reg to be changed.
1528 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1530 DOUT << "Removing now-noop copy: " << MI;
1531 VRM.RemoveMachineInstrFromMaps(&MI);
1534 Spills.disallowClobberPhysReg(VirtReg);
1535 goto ProcessNextInst;
1538 // If it's not a no-op copy, it clobbers the value in the destreg.
1539 Spills.ClobberPhysReg(VirtReg);
1540 ReusedOperands.markClobbered(VirtReg);
1542 // Check to see if this instruction is a load from a stack slot into
1543 // a register. If so, this provides the stack slot value in the reg.
1545 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1546 assert(DestReg == VirtReg && "Unknown load situation!");
1548 // If it is a folded reference, then it's not safe to clobber.
1549 bool Folded = FoldedSS.count(FrameIdx);
1550 // Otherwise, if it wasn't available, remember that it is now!
1551 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
1552 goto ProcessNextInst;
1558 unsigned SubIdx = MO.getSubReg();
1559 bool DoReMat = VRM.isReMaterialized(VirtReg);
1561 ReMatDefs.insert(&MI);
1563 // The only vregs left are stack slot definitions.
1564 int StackSlot = VRM.getStackSlot(VirtReg);
1565 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1567 // If this def is part of a two-address operand, make sure to execute
1568 // the store from the correct physical register.
1570 int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
1572 PhysReg = MI.getOperand(TiedOp).getReg();
1574 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
1575 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
1576 "Can't find corresponding super-register!");
1580 PhysReg = VRM.getPhys(VirtReg);
1581 if (ReusedOperands.isClobbered(PhysReg)) {
1582 // Another def has taken the assigned physreg. It must have been a
1583 // use&def which got it due to reuse. Undo the reuse!
1584 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1585 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1589 RegInfo->setPhysRegUsed(PhysReg);
1590 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1591 ReusedOperands.markClobbered(RReg);
1592 MI.getOperand(i).setReg(RReg);
1595 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1596 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
1597 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
1598 NextMII = next(MII);
1600 // Check to see if this is a noop copy. If so, eliminate the
1601 // instruction before considering the dest reg to be changed.
1604 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1606 DOUT << "Removing now-noop copy: " << MI;
1607 VRM.RemoveMachineInstrFromMaps(&MI);
1610 UpdateKills(*LastStore, RegKills, KillOps);
1611 goto ProcessNextInst;
1617 if (!Erased && !BackTracked) {
1618 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1619 UpdateKills(*II, RegKills, KillOps);
1625 llvm::Spiller* llvm::createSpiller() {
1626 switch (SpillerOpt) {
1627 default: assert(0 && "Unreachable!");
1629 return new LocalSpiller();
1631 return new SimpleSpiller();