1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/LiveStackAnalysis.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
42 #define DEBUG_TYPE "regalloc"
44 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
45 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
47 //===----------------------------------------------------------------------===//
48 // VirtRegMap implementation
49 //===----------------------------------------------------------------------===//
51 char VirtRegMap::ID = 0;
53 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
55 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
56 MRI = &mf.getRegInfo();
57 TII = mf.getTarget().getInstrInfo();
58 TRI = mf.getTarget().getRegisterInfo();
62 Virt2StackSlotMap.clear();
63 Virt2SplitMap.clear();
69 void VirtRegMap::grow() {
70 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
71 Virt2PhysMap.resize(NumRegs);
72 Virt2StackSlotMap.resize(NumRegs);
73 Virt2SplitMap.resize(NumRegs);
76 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
77 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
83 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
84 unsigned Hint = MRI->getSimpleHint(VirtReg);
87 if (TargetRegisterInfo::isVirtualRegister(Hint))
89 return getPhys(VirtReg) == Hint;
92 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
93 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
94 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
96 if (TargetRegisterInfo::isVirtualRegister(Hint.second))
97 return hasPhys(Hint.second);
101 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
102 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
103 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
104 "attempt to assign stack slot to already spilled register");
105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
106 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
109 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
110 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
112 "attempt to assign stack slot to already spilled register");
114 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
115 "illegal fixed frame index");
116 Virt2StackSlotMap[virtReg] = SS;
119 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
120 OS << "********** REGISTER MAP **********\n";
121 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
122 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
123 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
124 OS << '[' << PrintReg(Reg, TRI) << " -> "
125 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
126 << MRI->getRegClass(Reg)->getName() << "\n";
130 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
131 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
132 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
133 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
134 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
140 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
141 void VirtRegMap::dump() const {
146 //===----------------------------------------------------------------------===//
148 //===----------------------------------------------------------------------===//
150 // The VirtRegRewriter is the last of the register allocator passes.
151 // It rewrites virtual registers to physical registers as specified in the
152 // VirtRegMap analysis. It also updates live-in information on basic blocks
153 // according to LiveIntervals.
156 class VirtRegRewriter : public MachineFunctionPass {
158 const TargetMachine *TM;
159 const TargetRegisterInfo *TRI;
160 const TargetInstrInfo *TII;
161 MachineRegisterInfo *MRI;
162 SlotIndexes *Indexes;
165 SparseSet<unsigned> PhysRegs;
168 void addMBBLiveIns();
171 VirtRegRewriter() : MachineFunctionPass(ID) {}
173 void getAnalysisUsage(AnalysisUsage &AU) const override;
175 bool runOnMachineFunction(MachineFunction&) override;
177 } // end anonymous namespace
179 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
181 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
182 "Virtual Register Rewriter", false, false)
183 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
184 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
185 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
186 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
187 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
188 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
189 "Virtual Register Rewriter", false, false)
191 char VirtRegRewriter::ID = 0;
193 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
194 AU.setPreservesCFG();
195 AU.addRequired<LiveIntervals>();
196 AU.addRequired<SlotIndexes>();
197 AU.addPreserved<SlotIndexes>();
198 AU.addRequired<LiveDebugVariables>();
199 AU.addRequired<LiveStacks>();
200 AU.addPreserved<LiveStacks>();
201 AU.addRequired<VirtRegMap>();
202 MachineFunctionPass::getAnalysisUsage(AU);
205 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
207 TM = &MF->getTarget();
208 TRI = TM->getRegisterInfo();
209 TII = TM->getInstrInfo();
210 MRI = &MF->getRegInfo();
211 Indexes = &getAnalysis<SlotIndexes>();
212 LIS = &getAnalysis<LiveIntervals>();
213 VRM = &getAnalysis<VirtRegMap>();
214 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
215 << "********** Function: "
216 << MF->getName() << '\n');
219 // Add kill flags while we still have virtual registers.
220 LIS->addKillFlags(VRM);
222 // Live-in lists on basic blocks are required for physregs.
225 // Rewrite virtual registers.
228 // Write out new DBG_VALUE instructions.
229 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
231 // All machine operands and other references to virtual registers have been
232 // replaced. Remove the virtual registers and release all the transient data.
234 MRI->clearVirtRegs();
238 // Compute MBB live-in lists from virtual register live ranges and their
240 void VirtRegRewriter::addMBBLiveIns() {
241 SmallVector<MachineBasicBlock*, 16> LiveIn;
242 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
243 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
244 if (MRI->reg_nodbg_empty(VirtReg))
246 LiveInterval &LI = LIS->getInterval(VirtReg);
247 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
249 // This is a virtual register that is live across basic blocks. Its
250 // assigned PhysReg must be marked as live-in to those blocks.
251 unsigned PhysReg = VRM->getPhys(VirtReg);
252 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
254 // Scan the segments of LI.
255 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I != E;
257 if (!Indexes->findLiveInMBBs(I->start, I->end, LiveIn))
259 for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
260 if (!LiveIn[i]->isLiveIn(PhysReg))
261 LiveIn[i]->addLiveIn(PhysReg);
267 void VirtRegRewriter::rewrite() {
268 SmallVector<unsigned, 8> SuperDeads;
269 SmallVector<unsigned, 8> SuperDefs;
270 SmallVector<unsigned, 8> SuperKills;
271 SmallPtrSet<const MachineInstr *, 4> NoReturnInsts;
273 // Here we have a SparseSet to hold which PhysRegs are actually encountered
274 // in the MF we are about to iterate over so that later when we call
275 // setPhysRegUsed, we are only doing it for physRegs that were actually found
276 // in the program and not for all of the possible physRegs for the given
277 // target architecture. If the target has a lot of physRegs, then for a small
278 // program there will be a significant compile time reduction here.
280 PhysRegs.setUniverse(TRI->getNumRegs());
282 // The function with uwtable should guarantee that the stack unwinder
283 // can unwind the stack to the previous frame. Thus, we can't apply the
284 // noreturn optimization if the caller function has uwtable attribute.
285 bool HasUWTable = MF->getFunction()->hasFnAttribute(Attribute::UWTable);
287 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
288 MBBI != MBBE; ++MBBI) {
289 DEBUG(MBBI->print(dbgs(), Indexes));
290 bool IsExitBB = MBBI->succ_empty();
291 for (MachineBasicBlock::instr_iterator
292 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
293 MachineInstr *MI = MII;
296 // Check if this instruction is a call to a noreturn function. If this
297 // is a call to noreturn function and we don't need the stack unwinding
298 // functionality (i.e. this function does not have uwtable attribute and
299 // the callee function has the nounwind attribute), then we can ignore
300 // the definitions set by this instruction.
301 if (!HasUWTable && IsExitBB && MI->isCall()) {
302 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
303 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
304 MachineOperand &MO = *MOI;
307 const Function *Func = dyn_cast<Function>(MO.getGlobal());
308 if (!Func || !Func->hasFnAttribute(Attribute::NoReturn) ||
309 // We need to keep correct unwind information
310 // even if the function will not return, since the
311 // runtime may need it.
312 !Func->hasFnAttribute(Attribute::NoUnwind))
314 NoReturnInsts.insert(MI);
319 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
320 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
321 MachineOperand &MO = *MOI;
323 // Make sure MRI knows about registers clobbered by regmasks.
325 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
327 // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
328 // it to the physreg bitset. Later we use only the PhysRegs that were
329 // actually encountered in the MF to populate the MRI's used physregs.
330 if (MO.isReg() && MO.getReg())
332 TargetRegisterInfo::isVirtualRegister(MO.getReg()) ?
333 VRM->getPhys(MO.getReg()) :
336 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
338 unsigned VirtReg = MO.getReg();
339 unsigned PhysReg = VRM->getPhys(VirtReg);
340 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
341 "Instruction uses unmapped VirtReg");
342 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
344 // Preserve semantics of sub-register operands.
345 if (MO.getSubReg()) {
346 // A virtual register kill refers to the whole register, so we may
347 // have to add <imp-use,kill> operands for the super-register. A
348 // partial redef always kills and redefines the super-register.
349 if (MO.readsReg() && (MO.isDef() || MO.isKill()))
350 SuperKills.push_back(PhysReg);
353 // The <def,undef> flag only makes sense for sub-register defs, and
354 // we are substituting a full physreg. An <imp-use,kill> operand
355 // from the SuperKills list will represent the partial read of the
357 MO.setIsUndef(false);
359 // Also add implicit defs for the super-register.
361 SuperDeads.push_back(PhysReg);
363 SuperDefs.push_back(PhysReg);
366 // PhysReg operands cannot have subregister indexes.
367 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
368 assert(PhysReg && "Invalid SubReg for physical register");
371 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
372 // we need the inlining here.
376 // Add any missing super-register kills after rewriting the whole
378 while (!SuperKills.empty())
379 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
381 while (!SuperDeads.empty())
382 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
384 while (!SuperDefs.empty())
385 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
387 DEBUG(dbgs() << "> " << *MI);
389 // Finally, remove any identity copies.
390 if (MI->isIdentityCopy()) {
392 if (MI->getNumOperands() == 2) {
393 DEBUG(dbgs() << "Deleting identity copy.\n");
395 Indexes->removeMachineInstrFromMaps(MI);
396 // It's safe to erase MI because MII has already been incremented.
397 MI->eraseFromParent();
399 // Transform identity copy to a KILL to deal with subregisters.
400 MI->setDesc(TII->get(TargetOpcode::KILL));
401 DEBUG(dbgs() << "Identity copy: " << *MI);
407 // Tell MRI about physical registers in use.
408 if (NoReturnInsts.empty()) {
409 for (SparseSet<unsigned>::iterator
410 RegI = PhysRegs.begin(), E = PhysRegs.end(); RegI != E; ++RegI)
411 if (!MRI->reg_nodbg_empty(*RegI))
412 MRI->setPhysRegUsed(*RegI);
414 for (SparseSet<unsigned>::iterator
415 I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) {
417 if (MRI->reg_nodbg_empty(Reg))
419 // Check if this register has a use that will impact the rest of the
420 // code. Uses in debug and noreturn instructions do not impact the
422 for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
423 if (!NoReturnInsts.count(&It)) {
424 MRI->setPhysRegUsed(Reg);