1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "spiller"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/ADT/SmallSet.h"
39 STATISTIC(NumSpills , "Number of register spills");
40 STATISTIC(NumPSpills , "Number of physical register spills");
41 STATISTIC(NumReMats , "Number of re-materialization");
42 STATISTIC(NumDRM , "Number of re-materializable defs elided");
43 STATISTIC(NumStores , "Number of stores added");
44 STATISTIC(NumLoads , "Number of loads added");
45 STATISTIC(NumReused , "Number of values reused");
46 STATISTIC(NumDSE , "Number of dead stores elided");
47 STATISTIC(NumDCE , "Number of copies elided");
48 STATISTIC(NumDSS , "Number of dead spill slots removed");
49 STATISTIC(NumCommutes, "Number of instructions commuted");
52 enum SpillerName { simple, local };
55 static cl::opt<SpillerName>
57 cl::desc("Spiller to use: (default: local)"),
59 cl::values(clEnumVal(simple, " simple spiller"),
60 clEnumVal(local, " local spiller"),
64 //===----------------------------------------------------------------------===//
65 // VirtRegMap implementation
66 //===----------------------------------------------------------------------===//
68 VirtRegMap::VirtRegMap(MachineFunction &mf)
69 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
70 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
71 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
72 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1),
73 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) {
74 SpillSlotToUsesMap.resize(8);
75 ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1-
76 TargetRegisterInfo::FirstVirtualRegister);
80 void VirtRegMap::grow() {
81 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
82 Virt2PhysMap.grow(LastVirtReg);
83 Virt2StackSlotMap.grow(LastVirtReg);
84 Virt2ReMatIdMap.grow(LastVirtReg);
85 Virt2SplitMap.grow(LastVirtReg);
86 Virt2SplitKillMap.grow(LastVirtReg);
87 ReMatMap.grow(LastVirtReg);
88 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
91 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
92 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
93 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
94 "attempt to assign stack slot to already spilled register");
95 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
96 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
98 if (LowSpillSlot == NO_STACK_SLOT)
100 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
102 unsigned Idx = SS-LowSpillSlot;
103 while (Idx >= SpillSlotToUsesMap.size())
104 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
105 Virt2StackSlotMap[virtReg] = SS;
110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
111 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
113 "attempt to assign stack slot to already spilled register");
115 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) &&
116 "illegal fixed frame index");
117 Virt2StackSlotMap[virtReg] = SS;
120 int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
121 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
122 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
123 "attempt to assign re-mat id to already spilled register");
124 Virt2ReMatIdMap[virtReg] = ReMatId;
128 void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
129 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
130 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
131 "attempt to assign re-mat id to already spilled register");
132 Virt2ReMatIdMap[virtReg] = id;
135 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
136 std::map<const TargetRegisterClass*, int>::iterator I =
137 EmergencySpillSlots.find(RC);
138 if (I != EmergencySpillSlots.end())
140 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
142 if (LowSpillSlot == NO_STACK_SLOT)
144 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
150 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
151 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) {
152 // If FI < LowSpillSlot, this stack reference was produced by
153 // instruction selection and is not a spill
154 if (FI >= LowSpillSlot) {
155 assert(FI >= 0 && "Spill slot index should not be negative!");
156 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
157 && "Invalid spill slot");
158 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
163 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
164 MachineInstr *NewMI, ModRef MRInfo) {
165 // Move previous memory references folded to new instruction.
166 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
167 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
168 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
169 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
170 MI2VirtMap.erase(I++);
173 // add new memory reference
174 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
177 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
178 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
179 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
182 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
183 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
184 MachineOperand &MO = MI->getOperand(i);
185 if (!MO.isFrameIndex())
187 int FI = MO.getIndex();
188 if (MF.getFrameInfo()->isFixedObjectIndex(FI))
190 // This stack reference was produced by instruction selection and
192 if (FI < LowSpillSlot)
194 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
195 && "Invalid spill slot");
196 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
198 MI2VirtMap.erase(MI);
199 SpillPt2VirtMap.erase(MI);
200 RestorePt2VirtMap.erase(MI);
201 EmergencySpillMap.erase(MI);
204 void VirtRegMap::print(std::ostream &OS) const {
205 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
207 OS << "********** REGISTER MAP **********\n";
208 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
209 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
210 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
211 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
215 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
216 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
217 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
218 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
222 void VirtRegMap::dump() const {
227 //===----------------------------------------------------------------------===//
228 // Simple Spiller Implementation
229 //===----------------------------------------------------------------------===//
231 Spiller::~Spiller() {}
234 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
235 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
239 bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
240 DOUT << "********** REWRITE MACHINE CODE **********\n";
241 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
242 const TargetMachine &TM = MF.getTarget();
243 const TargetInstrInfo &TII = *TM.getInstrInfo();
246 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
247 // each vreg once (in the case where a spilled vreg is used by multiple
248 // operands). This is always smaller than the number of operands to the
249 // current machine instr, so it should be small.
250 std::vector<unsigned> LoadedRegs;
252 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
254 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
255 MachineBasicBlock &MBB = *MBBI;
256 for (MachineBasicBlock::iterator MII = MBB.begin(),
257 E = MBB.end(); MII != E; ++MII) {
258 MachineInstr &MI = *MII;
259 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
260 MachineOperand &MO = MI.getOperand(i);
261 if (MO.isRegister() && MO.getReg()) {
262 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
263 unsigned VirtReg = MO.getReg();
264 unsigned PhysReg = VRM.getPhys(VirtReg);
265 if (!VRM.isAssignedReg(VirtReg)) {
266 int StackSlot = VRM.getStackSlot(VirtReg);
267 const TargetRegisterClass* RC =
268 MF.getRegInfo().getRegClass(VirtReg);
271 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
272 == LoadedRegs.end()) {
273 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
274 MachineInstr *LoadMI = prior(MII);
275 VRM.addSpillSlotUse(StackSlot, LoadMI);
276 LoadedRegs.push_back(VirtReg);
278 DOUT << '\t' << *LoadMI;
282 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
284 MachineInstr *StoreMI = next(MII);
285 VRM.addSpillSlotUse(StackSlot, StoreMI);
289 MF.getRegInfo().setPhysRegUsed(PhysReg);
290 MI.getOperand(i).setReg(PhysReg);
292 MF.getRegInfo().setPhysRegUsed(MO.getReg());
304 //===----------------------------------------------------------------------===//
305 // Local Spiller Implementation
306 //===----------------------------------------------------------------------===//
309 class AvailableSpills;
311 /// LocalSpiller - This spiller does a simple pass over the machine basic
312 /// block to attempt to keep spills in registers as much as possible for
313 /// blocks that have low register pressure (the vreg may be spilled due to
314 /// register pressure in other blocks).
315 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
316 MachineRegisterInfo *RegInfo;
317 const TargetRegisterInfo *TRI;
318 const TargetInstrInfo *TII;
319 DenseMap<MachineInstr*, unsigned> DistanceMap;
321 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
322 RegInfo = &MF.getRegInfo();
323 TRI = MF.getTarget().getRegisterInfo();
324 TII = MF.getTarget().getInstrInfo();
325 DOUT << "\n**** Local spiller rewriting function '"
326 << MF.getFunction()->getName() << "':\n";
327 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
331 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
333 RewriteMBB(*MBB, VRM);
335 // Mark unused spill slots.
336 MachineFrameInfo *MFI = MF.getFrameInfo();
337 int SS = VRM.getLowSpillSlot();
338 if (SS != VirtRegMap::NO_STACK_SLOT)
339 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
340 if (!VRM.isSpillSlotUsed(SS)) {
341 MFI->RemoveStackObject(SS);
345 DOUT << "**** Post Machine Instrs ****\n";
351 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
352 unsigned Reg, BitVector &RegKills,
353 std::vector<MachineOperand*> &KillOps);
354 bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
355 MachineBasicBlock::iterator &MII,
356 std::vector<MachineInstr*> &MaybeDeadStores,
357 AvailableSpills &Spills, BitVector &RegKills,
358 std::vector<MachineOperand*> &KillOps,
360 bool CommuteToFoldReload(MachineBasicBlock &MBB,
361 MachineBasicBlock::iterator &MII,
362 unsigned VirtReg, unsigned SrcReg, int SS,
364 std::vector<MachineOperand*> &KillOps,
365 const TargetRegisterInfo *TRI,
367 void SpillRegToStackSlot(MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator &MII,
369 int Idx, unsigned PhysReg, int StackSlot,
370 const TargetRegisterClass *RC,
371 bool isAvailable, MachineInstr *&LastStore,
372 AvailableSpills &Spills,
373 SmallSet<MachineInstr*, 4> &ReMatDefs,
375 std::vector<MachineOperand*> &KillOps,
377 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
381 /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
382 /// top down, keep track of which spills slots or remat are available in each
385 /// Note that not all physregs are created equal here. In particular, some
386 /// physregs are reloads that we are allowed to clobber or ignore at any time.
387 /// Other physregs are values that the register allocated program is using that
388 /// we cannot CHANGE, but we can read if we like. We keep track of this on a
389 /// per-stack-slot / remat id basis as the low bit in the value of the
390 /// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
391 /// this bit and addAvailable sets it if.
393 class VISIBILITY_HIDDEN AvailableSpills {
394 const TargetRegisterInfo *TRI;
395 const TargetInstrInfo *TII;
397 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
398 // or remat'ed virtual register values that are still available, due to being
399 // loaded or stored to, but not invalidated yet.
400 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
402 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
403 // indicating which stack slot values are currently held by a physreg. This
404 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
405 // physreg is modified.
406 std::multimap<unsigned, int> PhysRegsAvailable;
408 void disallowClobberPhysRegOnly(unsigned PhysReg);
410 void ClobberPhysRegOnly(unsigned PhysReg);
412 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
413 : TRI(tri), TII(tii) {
416 const TargetRegisterInfo *getRegInfo() const { return TRI; }
418 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
419 /// available in a physical register, return that PhysReg, otherwise
421 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
422 std::map<int, unsigned>::const_iterator I =
423 SpillSlotsOrReMatsAvailable.find(Slot);
424 if (I != SpillSlotsOrReMatsAvailable.end()) {
425 return I->second >> 1; // Remove the CanClobber bit.
430 /// addAvailable - Mark that the specified stack slot / remat is available in
431 /// the specified physreg. If CanClobber is true, the physreg can be modified
432 /// at any time without changing the semantics of the program.
433 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
434 bool CanClobber = true) {
435 // If this stack slot is thought to be available in some other physreg,
436 // remove its record.
437 ModifyStackSlotOrReMat(SlotOrReMat);
439 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
440 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
442 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
443 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
445 DOUT << "Remembering SS#" << SlotOrReMat;
446 DOUT << " in physreg " << TRI->getName(Reg) << "\n";
449 /// canClobberPhysReg - Return true if the spiller is allowed to change the
450 /// value of the specified stackslot register if it desires. The specified
451 /// stack slot must be available in a physreg for this query to make sense.
452 bool canClobberPhysReg(int SlotOrReMat) const {
453 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
454 "Value not available!");
455 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
458 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
459 /// stackslot register. The register is still available but is no longer
460 /// allowed to be modifed.
461 void disallowClobberPhysReg(unsigned PhysReg);
463 /// ClobberPhysReg - This is called when the specified physreg changes
464 /// value. We use this to invalidate any info about stuff that lives in
465 /// it and any of its aliases.
466 void ClobberPhysReg(unsigned PhysReg);
468 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
469 /// slot changes. This removes information about which register the previous
470 /// value for this slot lives in (as the previous value is dead now).
471 void ModifyStackSlotOrReMat(int SlotOrReMat);
475 /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
476 /// stackslot register. The register is still available but is no longer
477 /// allowed to be modifed.
478 void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
479 std::multimap<unsigned, int>::iterator I =
480 PhysRegsAvailable.lower_bound(PhysReg);
481 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
482 int SlotOrReMat = I->second;
484 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
485 "Bidirectional map mismatch!");
486 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
487 DOUT << "PhysReg " << TRI->getName(PhysReg)
488 << " copied, it is available for use but can no longer be modified\n";
492 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
493 /// stackslot register and its aliases. The register and its aliases may
494 /// still available but is no longer allowed to be modifed.
495 void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
496 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
497 disallowClobberPhysRegOnly(*AS);
498 disallowClobberPhysRegOnly(PhysReg);
501 /// ClobberPhysRegOnly - This is called when the specified physreg changes
502 /// value. We use this to invalidate any info about stuff we thing lives in it.
503 void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
504 std::multimap<unsigned, int>::iterator I =
505 PhysRegsAvailable.lower_bound(PhysReg);
506 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
507 int SlotOrReMat = I->second;
508 PhysRegsAvailable.erase(I++);
509 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
510 "Bidirectional map mismatch!");
511 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
512 DOUT << "PhysReg " << TRI->getName(PhysReg)
513 << " clobbered, invalidating ";
514 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
515 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
517 DOUT << "SS#" << SlotOrReMat << "\n";
521 /// ClobberPhysReg - This is called when the specified physreg changes
522 /// value. We use this to invalidate any info about stuff we thing lives in
523 /// it and any of its aliases.
524 void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
525 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
526 ClobberPhysRegOnly(*AS);
527 ClobberPhysRegOnly(PhysReg);
530 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
531 /// slot changes. This removes information about which register the previous
532 /// value for this slot lives in (as the previous value is dead now).
533 void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
534 std::map<int, unsigned>::iterator It =
535 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
536 if (It == SpillSlotsOrReMatsAvailable.end()) return;
537 unsigned Reg = It->second >> 1;
538 SpillSlotsOrReMatsAvailable.erase(It);
540 // This register may hold the value of multiple stack slots, only remove this
541 // stack slot from the set of values the register contains.
542 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
544 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
545 "Map inverse broken!");
546 if (I->second == SlotOrReMat) break;
548 PhysRegsAvailable.erase(I);
553 /// InvalidateKills - MI is going to be deleted. If any of its operands are
554 /// marked kill, then invalidate the information.
555 static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
556 std::vector<MachineOperand*> &KillOps,
557 SmallVector<unsigned, 2> *KillRegs = NULL) {
558 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
559 MachineOperand &MO = MI.getOperand(i);
560 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
562 unsigned Reg = MO.getReg();
564 KillRegs->push_back(Reg);
565 if (KillOps[Reg] == &MO) {
572 /// InvalidateKill - A MI that defines the specified register is being deleted,
573 /// invalidate the register kill information.
574 static void InvalidateKill(unsigned Reg, BitVector &RegKills,
575 std::vector<MachineOperand*> &KillOps) {
577 KillOps[Reg]->setIsKill(false);
583 /// InvalidateRegDef - If the def operand of the specified def MI is now dead
584 /// (since it's spill instruction is removed), mark it isDead. Also checks if
585 /// the def MI has other definition operands that are not dead. Returns it by
587 static bool InvalidateRegDef(MachineBasicBlock::iterator I,
588 MachineInstr &NewDef, unsigned Reg,
590 // Due to remat, it's possible this reg isn't being reused. That is,
591 // the def of this reg (by prev MI) is now dead.
592 MachineInstr *DefMI = I;
593 MachineOperand *DefOp = NULL;
594 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
595 MachineOperand &MO = DefMI->getOperand(i);
596 if (MO.isRegister() && MO.isDef()) {
597 if (MO.getReg() == Reg)
599 else if (!MO.isDead())
606 bool FoundUse = false, Done = false;
607 MachineBasicBlock::iterator E = &NewDef;
609 for (; !Done && I != E; ++I) {
610 MachineInstr *NMI = I;
611 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
612 MachineOperand &MO = NMI->getOperand(j);
613 if (!MO.isRegister() || MO.getReg() != Reg)
617 Done = true; // Stop after scanning all the operands of this MI.
628 /// UpdateKills - Track and update kill info. If a MI reads a register that is
629 /// marked kill, then it must be due to register reuse. Transfer the kill info
631 static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
632 std::vector<MachineOperand*> &KillOps) {
633 const TargetInstrDesc &TID = MI.getDesc();
634 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
635 MachineOperand &MO = MI.getOperand(i);
636 if (!MO.isRegister() || !MO.isUse())
638 unsigned Reg = MO.getReg();
642 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) {
643 // That can't be right. Register is killed but not re-defined and it's
644 // being reused. Let's fix that.
645 KillOps[Reg]->setIsKill(false);
648 if (i < TID.getNumOperands() &&
649 TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
650 // Unless it's a two-address operand, this is the new kill.
659 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
660 const MachineOperand &MO = MI.getOperand(i);
661 if (!MO.isRegister() || !MO.isDef())
663 unsigned Reg = MO.getReg();
669 /// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
671 static void ReMaterialize(MachineBasicBlock &MBB,
672 MachineBasicBlock::iterator &MII,
673 unsigned DestReg, unsigned Reg,
674 const TargetInstrInfo *TII,
675 const TargetRegisterInfo *TRI,
677 TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
678 MachineInstr *NewMI = prior(MII);
679 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
680 MachineOperand &MO = NewMI->getOperand(i);
681 if (!MO.isRegister() || MO.getReg() == 0)
683 unsigned VirtReg = MO.getReg();
684 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
687 unsigned SubIdx = MO.getSubReg();
688 unsigned Phys = VRM.getPhys(VirtReg);
690 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
697 // ReusedOp - For each reused operand, we keep track of a bit of information, in
698 // case we need to rollback upon processing a new operand. See comments below.
701 // The MachineInstr operand that reused an available value.
704 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
705 unsigned StackSlotOrReMat;
707 // PhysRegReused - The physical register the value was available in.
708 unsigned PhysRegReused;
710 // AssignedPhysReg - The physreg that was assigned for use by the reload.
711 unsigned AssignedPhysReg;
713 // VirtReg - The virtual register itself.
716 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
718 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
719 AssignedPhysReg(apr), VirtReg(vreg) {}
722 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
723 /// is reused instead of reloaded.
724 class VISIBILITY_HIDDEN ReuseInfo {
726 std::vector<ReusedOp> Reuses;
727 BitVector PhysRegsClobbered;
729 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
730 PhysRegsClobbered.resize(tri->getNumRegs());
733 bool hasReuses() const {
734 return !Reuses.empty();
737 /// addReuse - If we choose to reuse a virtual register that is already
738 /// available instead of reloading it, remember that we did so.
739 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
740 unsigned PhysRegReused, unsigned AssignedPhysReg,
742 // If the reload is to the assigned register anyway, no undo will be
744 if (PhysRegReused == AssignedPhysReg) return;
746 // Otherwise, remember this.
747 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
748 AssignedPhysReg, VirtReg));
751 void markClobbered(unsigned PhysReg) {
752 PhysRegsClobbered.set(PhysReg);
755 bool isClobbered(unsigned PhysReg) const {
756 return PhysRegsClobbered.test(PhysReg);
759 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
760 /// is some other operand that is using the specified register, either pick
761 /// a new register to use, or evict the previous reload and use this reg.
762 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
763 AvailableSpills &Spills,
764 std::vector<MachineInstr*> &MaybeDeadStores,
765 SmallSet<unsigned, 8> &Rejected,
767 std::vector<MachineOperand*> &KillOps,
769 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
772 if (Reuses.empty()) return PhysReg; // This is most often empty.
774 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
775 ReusedOp &Op = Reuses[ro];
776 // If we find some other reuse that was supposed to use this register
777 // exactly for its reload, we can change this reload to use ITS reload
778 // register. That is, unless its reload register has already been
779 // considered and subsequently rejected because it has also been reused
780 // by another operand.
781 if (Op.PhysRegReused == PhysReg &&
782 Rejected.count(Op.AssignedPhysReg) == 0) {
783 // Yup, use the reload register that we didn't use before.
784 unsigned NewReg = Op.AssignedPhysReg;
785 Rejected.insert(PhysReg);
786 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
787 RegKills, KillOps, VRM);
789 // Otherwise, we might also have a problem if a previously reused
790 // value aliases the new register. If so, codegen the previous reload
792 unsigned PRRU = Op.PhysRegReused;
793 const TargetRegisterInfo *TRI = Spills.getRegInfo();
794 if (TRI->areAliases(PRRU, PhysReg)) {
795 // Okay, we found out that an alias of a reused register
796 // was used. This isn't good because it means we have
797 // to undo a previous reuse.
798 MachineBasicBlock *MBB = MI->getParent();
799 const TargetRegisterClass *AliasRC =
800 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
802 // Copy Op out of the vector and remove it, we're going to insert an
803 // explicit load for it.
805 Reuses.erase(Reuses.begin()+ro);
807 // Ok, we're going to try to reload the assigned physreg into the
808 // slot that we were supposed to in the first place. However, that
809 // register could hold a reuse. Check to see if it conflicts or
810 // would prefer us to use a different register.
811 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
812 MI, Spills, MaybeDeadStores,
813 Rejected, RegKills, KillOps, VRM);
815 MachineBasicBlock::iterator MII = MI;
816 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
817 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM);
819 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
820 NewOp.StackSlotOrReMat, AliasRC);
821 MachineInstr *LoadMI = prior(MII);
822 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
823 // Any stores to this stack slot are not dead anymore.
824 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
827 Spills.ClobberPhysReg(NewPhysReg);
828 Spills.ClobberPhysReg(NewOp.PhysRegReused);
830 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
832 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
834 UpdateKills(*MII, RegKills, KillOps);
835 DOUT << '\t' << *MII;
837 DOUT << "Reuse undone!\n";
840 // Finally, PhysReg is now available, go ahead and use it.
848 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
849 /// 'Rejected' set to remember which registers have been considered and
850 /// rejected for the reload. This avoids infinite looping in case like
853 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
854 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
856 /// sees r1 is taken by t2, tries t2's reload register r0
857 /// sees r0 is taken by t3, tries t3's reload register r1
858 /// sees r1 is taken by t2, tries t2's reload register r0 ...
859 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
860 AvailableSpills &Spills,
861 std::vector<MachineInstr*> &MaybeDeadStores,
863 std::vector<MachineOperand*> &KillOps,
865 SmallSet<unsigned, 8> Rejected;
866 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
867 RegKills, KillOps, VRM);
872 /// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
873 /// instruction. e.g.
875 /// movl %eax, -32(%ebp)
876 /// movl -36(%ebp), %eax
877 /// orl %eax, -32(%ebp)
880 /// orl -36(%ebp), %eax
881 /// mov %eax, -32(%ebp)
882 /// This enables unfolding optimization for a subsequent instruction which will
883 /// also eliminate the newly introduced store instruction.
884 bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
885 MachineBasicBlock::iterator &MII,
886 std::vector<MachineInstr*> &MaybeDeadStores,
887 AvailableSpills &Spills,
889 std::vector<MachineOperand*> &KillOps,
891 MachineFunction &MF = *MBB.getParent();
892 MachineInstr &MI = *MII;
893 unsigned UnfoldedOpc = 0;
894 unsigned UnfoldPR = 0;
895 unsigned UnfoldVR = 0;
896 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
897 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
898 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
899 // Only transform a MI that folds a single register.
902 UnfoldVR = I->second.first;
903 VirtRegMap::ModRef MR = I->second.second;
904 // MI2VirtMap be can updated which invalidate the iterator.
905 // Increment the iterator first.
907 if (VRM.isAssignedReg(UnfoldVR))
909 // If this reference is not a use, any previous store is now dead.
910 // Otherwise, the store to this stack slot is not dead anymore.
911 FoldedSS = VRM.getStackSlot(UnfoldVR);
912 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
913 if (DeadStore && (MR & VirtRegMap::isModRef)) {
914 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
915 if (!PhysReg || !DeadStore->readsRegister(PhysReg))
918 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
926 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
927 MachineOperand &MO = MI.getOperand(i);
928 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
930 unsigned VirtReg = MO.getReg();
931 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
933 if (VRM.isAssignedReg(VirtReg)) {
934 unsigned PhysReg = VRM.getPhys(VirtReg);
935 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
937 } else if (VRM.isReMaterialized(VirtReg))
939 int SS = VRM.getStackSlot(VirtReg);
940 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
942 if (TRI->regsOverlap(PhysReg, UnfoldPR))
946 PhysReg = VRM.getPhys(VirtReg);
947 if (!TRI->regsOverlap(PhysReg, UnfoldPR))
950 // Ok, we'll need to reload the value into a register which makes
951 // it impossible to perform the store unfolding optimization later.
952 // Let's see if it is possible to fold the load if the store is
953 // unfolded. This allows us to perform the store unfolding
955 SmallVector<MachineInstr*, 4> NewMIs;
956 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
957 assert(NewMIs.size() == 1);
958 MachineInstr *NewMI = NewMIs.back();
960 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
962 SmallVector<unsigned, 2> Ops;
964 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
966 VRM.addSpillSlotUse(SS, FoldedMI);
967 if (!VRM.hasPhys(UnfoldVR))
968 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
969 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
970 MII = MBB.insert(MII, FoldedMI);
971 InvalidateKills(MI, RegKills, KillOps);
972 VRM.RemoveMachineInstrFromMaps(&MI);
976 MF.DeleteMachineInstr(NewMI);
982 /// CommuteToFoldReload -
985 /// r1 = op r1, r2<kill>
988 /// If op is commutable and r2 is killed, then we can xform these to
991 bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB,
992 MachineBasicBlock::iterator &MII,
993 unsigned VirtReg, unsigned SrcReg, int SS,
995 std::vector<MachineOperand*> &KillOps,
996 const TargetRegisterInfo *TRI,
998 if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
1001 MachineFunction &MF = *MBB.getParent();
1002 MachineInstr &MI = *MII;
1003 MachineBasicBlock::iterator DefMII = prior(MII);
1004 MachineInstr *DefMI = DefMII;
1005 const TargetInstrDesc &TID = DefMI->getDesc();
1007 if (DefMII != MBB.begin() &&
1008 TID.isCommutable() &&
1009 TII->CommuteChangesDestination(DefMI, NewDstIdx)) {
1010 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
1011 unsigned NewReg = NewDstMO.getReg();
1012 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
1014 MachineInstr *ReloadMI = prior(DefMII);
1016 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
1017 if (DestReg != SrcReg || FrameIdx != SS)
1019 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
1022 int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO);
1025 assert(DefMI->getOperand(DefIdx).isRegister() &&
1026 DefMI->getOperand(DefIdx).getReg() == SrcReg);
1028 // Now commute def instruction.
1029 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true);
1032 SmallVector<unsigned, 2> Ops;
1033 Ops.push_back(NewDstIdx);
1034 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
1035 // Not needed since foldMemoryOperand returns new MI.
1036 MF.DeleteMachineInstr(CommutedMI);
1040 VRM.addSpillSlotUse(SS, FoldedMI);
1041 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1042 // Insert new def MI and spill MI.
1043 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
1044 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
1046 MachineInstr *StoreMI = MII;
1047 VRM.addSpillSlotUse(SS, StoreMI);
1048 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1049 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack.
1051 // Delete all 3 old instructions.
1052 InvalidateKills(*ReloadMI, RegKills, KillOps);
1053 VRM.RemoveMachineInstrFromMaps(ReloadMI);
1054 MBB.erase(ReloadMI);
1055 InvalidateKills(*DefMI, RegKills, KillOps);
1056 VRM.RemoveMachineInstrFromMaps(DefMI);
1058 InvalidateKills(MI, RegKills, KillOps);
1059 VRM.RemoveMachineInstrFromMaps(&MI);
1069 /// findSuperReg - Find the SubReg's super-register of given register class
1070 /// where its SubIdx sub-register is SubReg.
1071 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
1072 unsigned SubIdx, const TargetRegisterInfo *TRI) {
1073 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1076 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
1082 /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
1083 /// the last store to the same slot is now dead. If so, remove the last store.
1084 void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
1085 MachineBasicBlock::iterator &MII,
1086 int Idx, unsigned PhysReg, int StackSlot,
1087 const TargetRegisterClass *RC,
1088 bool isAvailable, MachineInstr *&LastStore,
1089 AvailableSpills &Spills,
1090 SmallSet<MachineInstr*, 4> &ReMatDefs,
1091 BitVector &RegKills,
1092 std::vector<MachineOperand*> &KillOps,
1094 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
1095 MachineInstr *StoreMI = next(MII);
1096 VRM.addSpillSlotUse(StackSlot, StoreMI);
1097 DOUT << "Store:\t" << *StoreMI;
1099 // If there is a dead store to this stack slot, nuke it now.
1101 DOUT << "Removed dead store:\t" << *LastStore;
1103 SmallVector<unsigned, 2> KillRegs;
1104 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
1105 MachineBasicBlock::iterator PrevMII = LastStore;
1106 bool CheckDef = PrevMII != MBB.begin();
1109 VRM.RemoveMachineInstrFromMaps(LastStore);
1110 MBB.erase(LastStore);
1112 // Look at defs of killed registers on the store. Mark the defs
1113 // as dead since the store has been deleted and they aren't
1115 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1116 bool HasOtherDef = false;
1117 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
1118 MachineInstr *DeadDef = PrevMII;
1119 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1120 // FIXME: This assumes a remat def does not have side
1122 VRM.RemoveMachineInstrFromMaps(DeadDef);
1131 LastStore = next(MII);
1133 // If the stack slot value was previously available in some other
1134 // register, change it now. Otherwise, make the register available,
1136 Spills.ModifyStackSlotOrReMat(StackSlot);
1137 Spills.ClobberPhysReg(PhysReg);
1138 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable);
1142 /// TransferDeadness - A identity copy definition is dead and it's being
1143 /// removed. Find the last def or use and mark it as dead / kill.
1144 void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
1145 unsigned Reg, BitVector &RegKills,
1146 std::vector<MachineOperand*> &KillOps) {
1147 int LastUDDist = -1;
1148 MachineInstr *LastUDMI = NULL;
1149 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
1150 RE = RegInfo->reg_end(); RI != RE; ++RI) {
1151 MachineInstr *UDMI = &*RI;
1152 if (UDMI->getParent() != MBB)
1154 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
1155 if (DI == DistanceMap.end() || DI->second > CurDist)
1157 if ((int)DI->second < LastUDDist)
1159 LastUDDist = DI->second;
1164 const TargetInstrDesc &TID = LastUDMI->getDesc();
1165 MachineOperand *LastUD = NULL;
1166 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
1167 MachineOperand &MO = LastUDMI->getOperand(i);
1168 if (!MO.isRegister() || MO.getReg() != Reg)
1170 if (!LastUD || (LastUD->isUse() && MO.isDef()))
1172 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1)
1175 if (LastUD->isDef())
1176 LastUD->setIsDead();
1178 LastUD->setIsKill();
1180 KillOps[Reg] = LastUD;
1185 /// rewriteMBB - Keep track of which spills are available even after the
1186 /// register allocator is done with them. If possible, avid reloading vregs.
1187 void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
1188 DOUT << MBB.getBasicBlock()->getName() << ":\n";
1190 MachineFunction &MF = *MBB.getParent();
1192 // Spills - Keep track of which spilled values are available in physregs so
1193 // that we can choose to reuse the physregs instead of emitting reloads.
1194 AvailableSpills Spills(TRI, TII);
1196 // MaybeDeadStores - When we need to write a value back into a stack slot,
1197 // keep track of the inserted store. If the stack slot value is never read
1198 // (because the value was used from some available register, for example), and
1199 // subsequently stored to, the original store is dead. This map keeps track
1200 // of inserted stores that are not used. If we see a subsequent store to the
1201 // same stack slot, the original store is deleted.
1202 std::vector<MachineInstr*> MaybeDeadStores;
1203 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
1205 // ReMatDefs - These are rematerializable def MIs which are not deleted.
1206 SmallSet<MachineInstr*, 4> ReMatDefs;
1208 // Keep track of kill information.
1209 BitVector RegKills(TRI->getNumRegs());
1210 std::vector<MachineOperand*> KillOps;
1211 KillOps.resize(TRI->getNumRegs(), NULL);
1214 DistanceMap.clear();
1215 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
1217 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
1219 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1220 bool Erased = false;
1221 bool BackTracked = false;
1222 if (PrepForUnfoldOpti(MBB, MII,
1223 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
1224 NextMII = next(MII);
1226 MachineInstr &MI = *MII;
1227 const TargetInstrDesc &TID = MI.getDesc();
1229 if (VRM.hasEmergencySpills(&MI)) {
1230 // Spill physical register(s) in the rare case the allocator has run out
1231 // of registers to allocate.
1232 SmallSet<int, 4> UsedSS;
1233 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
1234 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
1235 unsigned PhysReg = EmSpills[i];
1236 const TargetRegisterClass *RC =
1237 TRI->getPhysicalRegisterRegClass(PhysReg);
1238 assert(RC && "Unable to determine register class!");
1239 int SS = VRM.getEmergencySpillSlot(RC);
1240 if (UsedSS.count(SS))
1241 assert(0 && "Need to spill more than one physical registers!");
1243 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
1244 MachineInstr *StoreMI = prior(MII);
1245 VRM.addSpillSlotUse(SS, StoreMI);
1246 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC);
1247 MachineInstr *LoadMI = next(MII);
1248 VRM.addSpillSlotUse(SS, LoadMI);
1251 NextMII = next(MII);
1254 // Insert restores here if asked to.
1255 if (VRM.isRestorePt(&MI)) {
1256 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
1257 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
1258 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
1259 if (!VRM.getPreSplitReg(VirtReg))
1260 continue; // Split interval spilled again.
1261 unsigned Phys = VRM.getPhys(VirtReg);
1262 RegInfo->setPhysRegUsed(Phys);
1263 if (VRM.isReMaterialized(VirtReg)) {
1264 ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM);
1266 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1267 int SS = VRM.getStackSlot(VirtReg);
1268 TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC);
1269 MachineInstr *LoadMI = prior(MII);
1270 VRM.addSpillSlotUse(SS, LoadMI);
1273 // This invalidates Phys.
1274 Spills.ClobberPhysReg(Phys);
1275 UpdateKills(*prior(MII), RegKills, KillOps);
1276 DOUT << '\t' << *prior(MII);
1280 // Insert spills here if asked to.
1281 if (VRM.isSpillPt(&MI)) {
1282 std::vector<std::pair<unsigned,bool> > &SpillRegs =
1283 VRM.getSpillPtSpills(&MI);
1284 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
1285 unsigned VirtReg = SpillRegs[i].first;
1286 bool isKill = SpillRegs[i].second;
1287 if (!VRM.getPreSplitReg(VirtReg))
1288 continue; // Split interval spilled again.
1289 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1290 unsigned Phys = VRM.getPhys(VirtReg);
1291 int StackSlot = VRM.getStackSlot(VirtReg);
1292 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
1293 MachineInstr *StoreMI = next(MII);
1294 VRM.addSpillSlotUse(StackSlot, StoreMI);
1295 DOUT << "Store:\t" << *StoreMI;
1296 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1298 NextMII = next(MII);
1301 /// ReusedOperands - Keep track of operand reuse in case we need to undo
1303 ReuseInfo ReusedOperands(MI, TRI);
1304 SmallVector<unsigned, 4> VirtUseOps;
1305 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1306 MachineOperand &MO = MI.getOperand(i);
1307 if (!MO.isRegister() || MO.getReg() == 0)
1308 continue; // Ignore non-register operands.
1310 unsigned VirtReg = MO.getReg();
1311 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
1312 // Ignore physregs for spilling, but remember that it is used by this
1314 RegInfo->setPhysRegUsed(VirtReg);
1318 // We want to process implicit virtual register uses first.
1319 if (MO.isImplicit())
1320 // If the virtual register is implicitly defined, emit a implicit_def
1321 // before so scavenger knows it's "defined".
1322 VirtUseOps.insert(VirtUseOps.begin(), i);
1324 VirtUseOps.push_back(i);
1327 // Process all of the spilled uses and all non spilled reg references.
1328 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
1329 unsigned i = VirtUseOps[j];
1330 MachineOperand &MO = MI.getOperand(i);
1331 unsigned VirtReg = MO.getReg();
1332 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
1333 "Not a virtual register?");
1335 unsigned SubIdx = MO.getSubReg();
1336 if (VRM.isAssignedReg(VirtReg)) {
1337 // This virtual register was assigned a physreg!
1338 unsigned Phys = VRM.getPhys(VirtReg);
1339 RegInfo->setPhysRegUsed(Phys);
1341 ReusedOperands.markClobbered(Phys);
1342 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
1343 MI.getOperand(i).setReg(RReg);
1344 if (VRM.isImplicitlyDefined(VirtReg))
1345 BuildMI(MBB, &MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
1349 // This virtual register is now known to be a spilled value.
1351 continue; // Handle defs in the loop below (handle use&def here though)
1353 bool DoReMat = VRM.isReMaterialized(VirtReg);
1354 int SSorRMId = DoReMat
1355 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1356 int ReuseSlot = SSorRMId;
1358 // Check to see if this stack slot is available.
1359 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1361 // If this is a sub-register use, make sure the reuse register is in the
1362 // right register class. For example, for x86 not all of the 32-bit
1363 // registers have accessible sub-registers.
1364 // Similarly so for EXTRACT_SUBREG. Consider this:
1366 // MOV32_mr fi#1, EDI
1368 // = EXTRACT_SUBREG fi#1
1369 // fi#1 is available in EDI, but it cannot be reused because it's not in
1370 // the right register file.
1372 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
1373 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1374 if (!RC->contains(PhysReg))
1379 // This spilled operand might be part of a two-address operand. If this
1380 // is the case, then changing it will necessarily require changing the
1381 // def part of the instruction as well. However, in some cases, we
1382 // aren't allowed to modify the reused register. If none of these cases
1384 bool CanReuse = true;
1385 int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
1387 MI.getOperand(ti).isRegister() &&
1388 MI.getOperand(ti).getReg() == VirtReg) {
1389 // Okay, we have a two address operand. We can reuse this physreg as
1390 // long as we are allowed to clobber the value and there isn't an
1391 // earlier def that has already clobbered the physreg.
1392 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
1393 !ReusedOperands.isClobbered(PhysReg);
1397 // If this stack slot value is already available, reuse it!
1398 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1399 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
1401 DOUT << "Reusing SS#" << ReuseSlot;
1402 DOUT << " from physreg "
1403 << TRI->getName(PhysReg) << " for vreg"
1404 << VirtReg <<" instead of reloading into physreg "
1405 << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
1406 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1407 MI.getOperand(i).setReg(RReg);
1409 // The only technical detail we have is that we don't know that
1410 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1411 // later in the instruction. In particular, consider 'op V1, V2'.
1412 // If V1 is available in physreg R0, we would choose to reuse it
1413 // here, instead of reloading it into the register the allocator
1414 // indicated (say R1). However, V2 might have to be reloaded
1415 // later, and it might indicate that it needs to live in R0. When
1416 // this occurs, we need to have information available that
1417 // indicates it is safe to use R1 for the reload instead of R0.
1419 // To further complicate matters, we might conflict with an alias,
1420 // or R0 and R1 might not be compatible with each other. In this
1421 // case, we actually insert a reload for V1 in R1, ensuring that
1422 // we can get at R0 or its alias.
1423 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
1424 VRM.getPhys(VirtReg), VirtReg);
1426 // Only mark it clobbered if this is a use&def operand.
1427 ReusedOperands.markClobbered(PhysReg);
1430 if (MI.getOperand(i).isKill() &&
1431 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1432 // This was the last use and the spilled value is still available
1433 // for reuse. That means the spill was unnecessary!
1434 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
1436 DOUT << "Removed dead store:\t" << *DeadStore;
1437 InvalidateKills(*DeadStore, RegKills, KillOps);
1438 VRM.RemoveMachineInstrFromMaps(DeadStore);
1439 MBB.erase(DeadStore);
1440 MaybeDeadStores[ReuseSlot] = NULL;
1447 // Otherwise we have a situation where we have a two-address instruction
1448 // whose mod/ref operand needs to be reloaded. This reload is already
1449 // available in some register "PhysReg", but if we used PhysReg as the
1450 // operand to our 2-addr instruction, the instruction would modify
1451 // PhysReg. This isn't cool if something later uses PhysReg and expects
1452 // to get its initial value.
1454 // To avoid this problem, and to avoid doing a load right after a store,
1455 // we emit a copy from PhysReg into the designated register for this
1457 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1458 assert(DesignatedReg && "Must map virtreg to physreg!");
1460 // Note that, if we reused a register for a previous operand, the
1461 // register we want to reload into might not actually be
1462 // available. If this occurs, use the register indicated by the
1464 if (ReusedOperands.hasReuses())
1465 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
1466 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1468 // If the mapped designated register is actually the physreg we have
1469 // incoming, we don't need to inserted a dead copy.
1470 if (DesignatedReg == PhysReg) {
1471 // If this stack slot value is already available, reuse it!
1472 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1473 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
1475 DOUT << "Reusing SS#" << ReuseSlot;
1476 DOUT << " from physreg " << TRI->getName(PhysReg)
1477 << " for vreg" << VirtReg
1478 << " instead of reloading into same physreg.\n";
1479 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1480 MI.getOperand(i).setReg(RReg);
1481 ReusedOperands.markClobbered(RReg);
1486 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1487 RegInfo->setPhysRegUsed(DesignatedReg);
1488 ReusedOperands.markClobbered(DesignatedReg);
1489 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
1491 MachineInstr *CopyMI = prior(MII);
1492 UpdateKills(*CopyMI, RegKills, KillOps);
1494 // This invalidates DesignatedReg.
1495 Spills.ClobberPhysReg(DesignatedReg);
1497 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
1499 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
1500 MI.getOperand(i).setReg(RReg);
1501 DOUT << '\t' << *prior(MII);
1506 // Otherwise, reload it and remember that we have it.
1507 PhysReg = VRM.getPhys(VirtReg);
1508 assert(PhysReg && "Must map virtreg to physreg!");
1510 // Note that, if we reused a register for a previous operand, the
1511 // register we want to reload into might not actually be
1512 // available. If this occurs, use the register indicated by the
1514 if (ReusedOperands.hasReuses())
1515 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1516 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1518 RegInfo->setPhysRegUsed(PhysReg);
1519 ReusedOperands.markClobbered(PhysReg);
1521 ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM);
1523 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1524 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
1525 MachineInstr *LoadMI = prior(MII);
1526 VRM.addSpillSlotUse(SSorRMId, LoadMI);
1529 // This invalidates PhysReg.
1530 Spills.ClobberPhysReg(PhysReg);
1532 // Any stores to this stack slot are not dead anymore.
1534 MaybeDeadStores[SSorRMId] = NULL;
1535 Spills.addAvailable(SSorRMId, &MI, PhysReg);
1536 // Assumes this is the last use. IsKill will be unset if reg is reused
1537 // unless it's a two-address operand.
1538 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
1539 MI.getOperand(i).setIsKill();
1540 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1541 MI.getOperand(i).setReg(RReg);
1542 UpdateKills(*prior(MII), RegKills, KillOps);
1543 DOUT << '\t' << *prior(MII);
1549 // If we have folded references to memory operands, make sure we clear all
1550 // physical registers that may contain the value of the spilled virtual
1552 SmallSet<int, 2> FoldedSS;
1553 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
1554 unsigned VirtReg = I->second.first;
1555 VirtRegMap::ModRef MR = I->second.second;
1556 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR;
1558 // MI2VirtMap be can updated which invalidate the iterator.
1559 // Increment the iterator first.
1561 int SS = VRM.getStackSlot(VirtReg);
1562 if (SS == VirtRegMap::NO_STACK_SLOT)
1564 FoldedSS.insert(SS);
1565 DOUT << " - StackSlot: " << SS << "\n";
1567 // If this folded instruction is just a use, check to see if it's a
1568 // straight load from the virt reg slot.
1569 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1571 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1572 if (DestReg && FrameIdx == SS) {
1573 // If this spill slot is available, turn it into a copy (or nothing)
1574 // instead of leaving it as a load!
1575 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1576 DOUT << "Promoted Load To Copy: " << MI;
1577 if (DestReg != InReg) {
1578 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1579 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
1580 // Revisit the copy so we make sure to notice the effects of the
1581 // operation on the destreg (either needing to RA it if it's
1582 // virtual or needing to clobber any values if it's physical).
1584 --NextMII; // backtrack to the copy.
1587 DOUT << "Removing now-noop copy: " << MI;
1588 // Unset last kill since it's being reused.
1589 InvalidateKill(InReg, RegKills, KillOps);
1592 InvalidateKills(MI, RegKills, KillOps);
1593 VRM.RemoveMachineInstrFromMaps(&MI);
1596 goto ProcessNextInst;
1599 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1600 SmallVector<MachineInstr*, 4> NewMIs;
1602 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
1603 MBB.insert(MII, NewMIs[0]);
1604 InvalidateKills(MI, RegKills, KillOps);
1605 VRM.RemoveMachineInstrFromMaps(&MI);
1608 --NextMII; // backtrack to the unfolded instruction.
1610 goto ProcessNextInst;
1615 // If this reference is not a use, any previous store is now dead.
1616 // Otherwise, the store to this stack slot is not dead anymore.
1617 MachineInstr* DeadStore = MaybeDeadStores[SS];
1619 bool isDead = !(MR & VirtRegMap::isRef);
1620 MachineInstr *NewStore = NULL;
1621 if (MR & VirtRegMap::isModRef) {
1622 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1623 SmallVector<MachineInstr*, 4> NewMIs;
1624 // We can reuse this physreg as long as we are allowed to clobber
1625 // the value and there isn't an earlier def that has already clobbered
1628 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
1629 MachineOperand *KillOpnd =
1630 DeadStore->findRegisterUseOperand(PhysReg, true);
1631 // Note, if the store is storing a sub-register, it's possible the
1632 // super-register is needed below.
1633 if (KillOpnd && !KillOpnd->getSubReg() &&
1634 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
1635 MBB.insert(MII, NewMIs[0]);
1636 NewStore = NewMIs[1];
1637 MBB.insert(MII, NewStore);
1638 VRM.addSpillSlotUse(SS, NewStore);
1639 InvalidateKills(MI, RegKills, KillOps);
1640 VRM.RemoveMachineInstrFromMaps(&MI);
1644 --NextMII; // backtrack to the unfolded instruction.
1651 if (isDead) { // Previous store is dead.
1652 // If we get here, the store is dead, nuke it now.
1653 DOUT << "Removed dead store:\t" << *DeadStore;
1654 InvalidateKills(*DeadStore, RegKills, KillOps);
1655 VRM.RemoveMachineInstrFromMaps(DeadStore);
1656 MBB.erase(DeadStore);
1661 MaybeDeadStores[SS] = NULL;
1663 // Treat this store as a spill merged into a copy. That makes the
1664 // stack slot value available.
1665 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
1666 goto ProcessNextInst;
1670 // If the spill slot value is available, and this is a new definition of
1671 // the value, the value is not available anymore.
1672 if (MR & VirtRegMap::isMod) {
1673 // Notice that the value in this stack slot has been modified.
1674 Spills.ModifyStackSlotOrReMat(SS);
1676 // If this is *just* a mod of the value, check to see if this is just a
1677 // store to the spill slot (i.e. the spill got merged into the copy). If
1678 // so, realize that the vreg is available now, and add the store to the
1679 // MaybeDeadStore info.
1681 if (!(MR & VirtRegMap::isRef)) {
1682 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1683 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1684 "Src hasn't been allocated yet?");
1686 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot,
1687 RegKills, KillOps, TRI, VRM)) {
1688 NextMII = next(MII);
1690 goto ProcessNextInst;
1693 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
1694 // this as a potentially dead store in case there is a subsequent
1695 // store into the stack slot without a read from it.
1696 MaybeDeadStores[StackSlot] = &MI;
1698 // If the stack slot value was previously available in some other
1699 // register, change it now. Otherwise, make the register
1700 // available in PhysReg.
1701 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*!clobber*/);
1707 // Process all of the spilled defs.
1708 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1709 MachineOperand &MO = MI.getOperand(i);
1710 if (!(MO.isRegister() && MO.getReg() && MO.isDef()))
1713 unsigned VirtReg = MO.getReg();
1714 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1715 // Check to see if this is a noop copy. If so, eliminate the
1716 // instruction before considering the dest reg to be changed.
1718 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1720 DOUT << "Removing now-noop copy: " << MI;
1721 SmallVector<unsigned, 2> KillRegs;
1722 InvalidateKills(MI, RegKills, KillOps, &KillRegs);
1723 if (MO.isDead() && !KillRegs.empty()) {
1724 assert(KillRegs[0] == Dst);
1725 // Last def is now dead.
1726 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps);
1728 VRM.RemoveMachineInstrFromMaps(&MI);
1731 Spills.disallowClobberPhysReg(VirtReg);
1732 goto ProcessNextInst;
1735 // If it's not a no-op copy, it clobbers the value in the destreg.
1736 Spills.ClobberPhysReg(VirtReg);
1737 ReusedOperands.markClobbered(VirtReg);
1739 // Check to see if this instruction is a load from a stack slot into
1740 // a register. If so, this provides the stack slot value in the reg.
1742 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1743 assert(DestReg == VirtReg && "Unknown load situation!");
1745 // If it is a folded reference, then it's not safe to clobber.
1746 bool Folded = FoldedSS.count(FrameIdx);
1747 // Otherwise, if it wasn't available, remember that it is now!
1748 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
1749 goto ProcessNextInst;
1755 unsigned SubIdx = MO.getSubReg();
1756 bool DoReMat = VRM.isReMaterialized(VirtReg);
1758 ReMatDefs.insert(&MI);
1760 // The only vregs left are stack slot definitions.
1761 int StackSlot = VRM.getStackSlot(VirtReg);
1762 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1764 // If this def is part of a two-address operand, make sure to execute
1765 // the store from the correct physical register.
1767 int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
1769 PhysReg = MI.getOperand(TiedOp).getReg();
1771 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
1772 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
1773 "Can't find corresponding super-register!");
1777 PhysReg = VRM.getPhys(VirtReg);
1778 if (ReusedOperands.isClobbered(PhysReg)) {
1779 // Another def has taken the assigned physreg. It must have been a
1780 // use&def which got it due to reuse. Undo the reuse!
1781 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1782 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1786 assert(PhysReg && "VR not assigned a physical register?");
1787 RegInfo->setPhysRegUsed(PhysReg);
1788 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1789 ReusedOperands.markClobbered(RReg);
1790 MI.getOperand(i).setReg(RReg);
1793 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1794 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
1795 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
1796 NextMII = next(MII);
1798 // Check to see if this is a noop copy. If so, eliminate the
1799 // instruction before considering the dest reg to be changed.
1802 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1804 DOUT << "Removing now-noop copy: " << MI;
1805 InvalidateKills(MI, RegKills, KillOps);
1806 VRM.RemoveMachineInstrFromMaps(&MI);
1809 UpdateKills(*LastStore, RegKills, KillOps);
1810 goto ProcessNextInst;
1816 DistanceMap.insert(std::make_pair(&MI, Dist++));
1817 if (!Erased && !BackTracked) {
1818 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
1819 UpdateKills(*II, RegKills, KillOps);
1825 llvm::Spiller* llvm::createSpiller() {
1826 switch (SpillerOpt) {
1827 default: assert(0 && "Unreachable!");
1829 return new LocalSpiller();
1831 return new SimpleSpiller();