1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "spiller"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/STLExtras.h"
36 Statistic<> NumSpills("spiller", "Number of register spills");
37 Statistic<> NumStores("spiller", "Number of stores added");
38 Statistic<> NumLoads ("spiller", "Number of loads added");
39 Statistic<> NumReused("spiller", "Number of values reused");
40 Statistic<> NumDSE ("spiller", "Number of dead stores elided");
42 enum SpillerName { simple, local };
46 cl::desc("Spiller to use: (default: local)"),
48 cl::values(clEnumVal(simple, " simple spiller"),
49 clEnumVal(local, " local spiller"),
54 //===----------------------------------------------------------------------===//
55 // VirtRegMap implementation
56 //===----------------------------------------------------------------------===//
58 void VirtRegMap::grow() {
59 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
60 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
63 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
64 assert(MRegisterInfo::isVirtualRegister(virtReg));
65 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
66 "attempt to assign stack slot to already spilled register");
67 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
68 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
70 Virt2StackSlotMap[virtReg] = frameIndex;
75 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
76 assert(MRegisterInfo::isVirtualRegister(virtReg));
77 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
78 "attempt to assign stack slot to already spilled register");
79 Virt2StackSlotMap[virtReg] = frameIndex;
82 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
83 unsigned OpNo, MachineInstr *NewMI) {
84 // Move previous memory references folded to new instruction.
85 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
86 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
87 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
88 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
89 MI2VirtMap.erase(I++);
93 if (!OldMI->getOperand(OpNo).isDef()) {
94 assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?");
97 MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod;
100 // add new memory reference
101 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
104 void VirtRegMap::print(std::ostream &OS) const {
105 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
107 OS << "********** REGISTER MAP **********\n";
108 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
109 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
110 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
111 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
115 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
116 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
117 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
118 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
122 void VirtRegMap::dump() const { print(std::cerr); }
125 //===----------------------------------------------------------------------===//
126 // Simple Spiller Implementation
127 //===----------------------------------------------------------------------===//
129 Spiller::~Spiller() {}
132 struct SimpleSpiller : public Spiller {
133 bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM);
137 bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
138 const VirtRegMap &VRM) {
139 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
140 DEBUG(std::cerr << "********** Function: "
141 << MF.getFunction()->getName() << '\n');
142 const TargetMachine &TM = MF.getTarget();
143 const MRegisterInfo &MRI = *TM.getRegisterInfo();
144 bool *PhysRegsUsed = MF.getUsedPhysregs();
146 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
147 // each vreg once (in the case where a spilled vreg is used by multiple
148 // operands). This is always smaller than the number of operands to the
149 // current machine instr, so it should be small.
150 std::vector<unsigned> LoadedRegs;
152 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
154 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
155 MachineBasicBlock &MBB = *MBBI;
156 for (MachineBasicBlock::iterator MII = MBB.begin(),
157 E = MBB.end(); MII != E; ++MII) {
158 MachineInstr &MI = *MII;
159 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
160 MachineOperand &MO = MI.getOperand(i);
161 if (MO.isRegister() && MO.getReg())
162 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
163 unsigned VirtReg = MO.getReg();
164 unsigned PhysReg = VRM.getPhys(VirtReg);
165 if (VRM.hasStackSlot(VirtReg)) {
166 int StackSlot = VRM.getStackSlot(VirtReg);
167 const TargetRegisterClass* RC =
168 MF.getSSARegMap()->getRegClass(VirtReg);
171 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
172 == LoadedRegs.end()) {
173 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
174 LoadedRegs.push_back(VirtReg);
176 DEBUG(std::cerr << '\t' << *prior(MII));
180 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
184 PhysRegsUsed[PhysReg] = true;
185 MI.SetMachineOperandReg(i, PhysReg);
187 PhysRegsUsed[MO.getReg()] = true;
191 DEBUG(std::cerr << '\t' << MI);
198 //===----------------------------------------------------------------------===//
199 // Local Spiller Implementation
200 //===----------------------------------------------------------------------===//
203 /// LocalSpiller - This spiller does a simple pass over the machine basic
204 /// block to attempt to keep spills in registers as much as possible for
205 /// blocks that have low register pressure (the vreg may be spilled due to
206 /// register pressure in other blocks).
207 class LocalSpiller : public Spiller {
208 const MRegisterInfo *MRI;
209 const TargetInstrInfo *TII;
211 bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) {
212 MRI = MF.getTarget().getRegisterInfo();
213 TII = MF.getTarget().getInstrInfo();
214 DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
215 << MF.getFunction()->getName() << "':\n");
217 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
219 RewriteMBB(*MBB, VRM);
223 void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM);
224 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
225 std::map<unsigned, int> &PhysRegs);
226 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
227 std::map<unsigned, int> &PhysRegs);
231 void LocalSpiller::ClobberPhysRegOnly(unsigned PhysReg,
232 std::map<int, unsigned> &SpillSlots,
233 std::map<unsigned, int> &PhysRegs) {
234 std::map<unsigned, int>::iterator I = PhysRegs.find(PhysReg);
235 if (I != PhysRegs.end()) {
236 int Slot = I->second;
238 assert(SpillSlots[Slot] == PhysReg && "Bidirectional map mismatch!");
239 SpillSlots.erase(Slot);
240 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
241 << " clobbered, invalidating SS#" << Slot << "\n");
246 void LocalSpiller::ClobberPhysReg(unsigned PhysReg,
247 std::map<int, unsigned> &SpillSlots,
248 std::map<unsigned, int> &PhysRegs) {
249 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
250 ClobberPhysRegOnly(*AS, SpillSlots, PhysRegs);
251 ClobberPhysRegOnly(PhysReg, SpillSlots, PhysRegs);
255 // ReusedOp - For each reused operand, we keep track of a bit of information, in
256 // case we need to rollback upon processing a new operand. See comments below.
259 // The MachineInstr operand that reused an available value.
262 // StackSlot - The spill slot of the value being reused.
265 // PhysRegReused - The physical register the value was available in.
266 unsigned PhysRegReused;
268 // AssignedPhysReg - The physreg that was assigned for use by the reload.
269 unsigned AssignedPhysReg;
271 // VirtReg - The virtual register itself.
274 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
276 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
282 /// rewriteMBB - Keep track of which spills are available even after the
283 /// register allocator is done with them. If possible, avoid reloading vregs.
284 void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
286 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
287 // register values that are still available, due to being loaded to stored to,
288 // but not invalidated yet.
289 std::map<int, unsigned> SpillSlotsAvailable;
291 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
292 // which physregs are in use holding a stack slot value.
293 std::map<unsigned, int> PhysRegsAvailable;
295 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
297 std::vector<ReusedOp> ReusedOperands;
299 // DefAndUseVReg - When we see a def&use operand that is spilled, keep track
300 // of it. ".first" is the machine operand index (should always be 0 for now),
301 // and ".second" is the virtual register that is spilled.
302 std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg;
304 // MaybeDeadStores - When we need to write a value back into a stack slot,
305 // keep track of the inserted store. If the stack slot value is never read
306 // (because the value was used from some available register, for example), and
307 // subsequently stored to, the original store is dead. This map keeps track
308 // of inserted stores that are not used. If we see a subsequent store to the
309 // same stack slot, the original store is deleted.
310 std::map<int, MachineInstr*> MaybeDeadStores;
312 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
314 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
316 MachineInstr &MI = *MII;
317 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
319 ReusedOperands.clear();
320 DefAndUseVReg.clear();
322 // Process all of the spilled uses and all non spilled reg references.
323 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
324 MachineOperand &MO = MI.getOperand(i);
325 if (!MO.isRegister() || MO.getReg() == 0)
326 continue; // Ignore non-register operands.
328 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
329 // Ignore physregs for spilling, but remember that it is used by this
331 PhysRegsUsed[MO.getReg()] = true;
335 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
336 "Not a virtual or a physical register?");
338 unsigned VirtReg = MO.getReg();
339 if (!VRM.hasStackSlot(VirtReg)) {
340 // This virtual register was assigned a physreg!
341 unsigned Phys = VRM.getPhys(VirtReg);
342 PhysRegsUsed[Phys] = true;
343 MI.SetMachineOperandReg(i, Phys);
347 // This virtual register is now known to be a spilled value.
349 continue; // Handle defs in the loop below (handle use&def here though)
351 // If this is both a def and a use, we need to emit a store to the
352 // stack slot after the instruction. Keep track of D&U operands
353 // because we are about to change it to a physreg here.
355 // Remember that this was a def-and-use operand, and that the
356 // stack slot is live after this instruction executes.
357 DefAndUseVReg.push_back(std::make_pair(i, VirtReg));
360 int StackSlot = VRM.getStackSlot(VirtReg);
363 // Check to see if this stack slot is available.
364 std::map<int, unsigned>::iterator SSI =
365 SpillSlotsAvailable.find(StackSlot);
366 if (SSI != SpillSlotsAvailable.end()) {
367 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
368 << MRI->getName(SSI->second) << " for vreg"
369 << VirtReg <<" instead of reloading into physreg "
370 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
371 // If this stack slot value is already available, reuse it!
372 PhysReg = SSI->second;
373 MI.SetMachineOperandReg(i, PhysReg);
375 // The only technical detail we have is that we don't know that
376 // PhysReg won't be clobbered by a reloaded stack slot that occurs
377 // later in the instruction. In particular, consider 'op V1, V2'.
378 // If V1 is available in physreg R0, we would choose to reuse it
379 // here, instead of reloading it into the register the allocator
380 // indicated (say R1). However, V2 might have to be reloaded
381 // later, and it might indicate that it needs to live in R0. When
382 // this occurs, we need to have information available that
383 // indicates it is safe to use R1 for the reload instead of R0.
385 // To further complicate matters, we might conflict with an alias,
386 // or R0 and R1 might not be compatible with each other. In this
387 // case, we actually insert a reload for V1 in R1, ensuring that
388 // we can get at R0 or its alias.
389 ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
390 VRM.getPhys(VirtReg), VirtReg));
395 // Otherwise, reload it and remember that we have it.
396 PhysReg = VRM.getPhys(VirtReg);
397 assert(PhysReg && "Must map virtreg to physreg!");
398 const TargetRegisterClass* RC =
399 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
402 // Note that, if we reused a register for a previous operand, the
403 // register we want to reload into might not actually be
404 // available. If this occurs, use the register indicated by the
406 if (!ReusedOperands.empty()) // This is most often empty.
407 for (unsigned ro = 0, e = ReusedOperands.size(); ro != e; ++ro)
408 if (ReusedOperands[ro].PhysRegReused == PhysReg) {
409 // Yup, use the reload register that we didn't use before.
410 PhysReg = ReusedOperands[ro].AssignedPhysReg;
411 goto RecheckRegister;
413 ReusedOp &Op = ReusedOperands[ro];
414 unsigned PRRU = Op.PhysRegReused;
415 if (MRI->areAliases(PRRU, PhysReg)) {
416 // Okay, we found out that an alias of a reused register
417 // was used. This isn't good because it means we have
418 // to undo a previous reuse.
419 const TargetRegisterClass *AliasRC =
420 MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
421 MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
422 Op.StackSlot, AliasRC);
423 ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
426 // Any stores to this stack slot are not dead anymore.
427 MaybeDeadStores.erase(Op.StackSlot);
429 MI.SetMachineOperandReg(Op.Operand, Op.AssignedPhysReg);
430 PhysRegsAvailable[Op.AssignedPhysReg] = Op.StackSlot;
431 SpillSlotsAvailable[Op.StackSlot] = Op.AssignedPhysReg;
432 PhysRegsAvailable.erase(Op.PhysRegReused);
433 DEBUG(std::cerr << "Remembering SS#" << Op.StackSlot
435 << MRI->getName(Op.AssignedPhysReg) << "\n");
437 DEBUG(std::cerr << '\t' << *prior(MII));
439 DEBUG(std::cerr << "Reuse undone!\n");
440 ReusedOperands.erase(ReusedOperands.begin()+ro);
446 PhysRegsUsed[PhysReg] = true;
447 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
448 // This invalidates PhysReg.
449 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
451 // Any stores to this stack slot are not dead anymore.
452 MaybeDeadStores.erase(StackSlot);
454 MI.SetMachineOperandReg(i, PhysReg);
455 PhysRegsAvailable[PhysReg] = StackSlot;
456 SpillSlotsAvailable[StackSlot] = PhysReg;
457 DEBUG(std::cerr << "Remembering SS#" << StackSlot <<" in physreg "
458 << MRI->getName(PhysReg) << "\n");
460 DEBUG(std::cerr << '\t' << *prior(MII));
463 // Loop over all of the implicit defs, clearing them from our available
465 for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
467 PhysRegsUsed[*ImpDef] = true;
468 ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable);
471 DEBUG(std::cerr << '\t' << MI);
473 // If we have folded references to memory operands, make sure we clear all
474 // physical registers that may contain the value of the spilled virtual
476 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
477 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
478 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
479 << I->second.second);
480 unsigned VirtReg = I->second.first;
481 VirtRegMap::ModRef MR = I->second.second;
482 if (!VRM.hasStackSlot(VirtReg)) {
483 DEBUG(std::cerr << ": No stack slot!\n");
486 int SS = VRM.getStackSlot(VirtReg);
487 DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
489 // If this folded instruction is just a use, check to see if it's a
490 // straight load from the virt reg slot.
491 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
493 if (unsigned DestReg = MRI->isLoadFromStackSlot(&MI, FrameIdx)) {
494 // If this spill slot is available, insert a copy for it!
495 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS);
496 if (FrameIdx == SS && It != SpillSlotsAvailable.end()) {
497 DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
498 MachineFunction &MF = *MBB.getParent();
499 if (DestReg != It->second) {
500 MRI->copyRegToReg(MBB, &MI, DestReg, It->second,
501 MF.getSSARegMap()->getRegClass(VirtReg));
502 // Revisit the copy so we make sure to notice the effects of the
503 // operation on the destreg (either needing to RA it if it's
504 // virtual or needing to clobber any values if it's physical).
506 --NextMII; // backtrack to the copy.
509 goto ProcessNextInst;
514 // If this reference is not a use, any previous store is now dead.
515 // Otherwise, the store to this stack slot is not dead anymore.
516 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
517 if (MDSI != MaybeDeadStores.end()) {
518 if (MR & VirtRegMap::isRef) // Previous store is not dead.
519 MaybeDeadStores.erase(MDSI);
521 // If we get here, the store is dead, nuke it now.
522 assert(MR == VirtRegMap::isMod && "Can't be modref!");
523 MBB.erase(MDSI->second);
524 MaybeDeadStores.erase(MDSI);
529 // If the spill slot value is available, and this is a new definition of
530 // the value, the value is not available anymore.
531 if (MR & VirtRegMap::isMod) {
532 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS);
533 if (It != SpillSlotsAvailable.end()) {
534 PhysRegsAvailable.erase(It->second);
535 SpillSlotsAvailable.erase(It);
540 // Process all of the spilled defs.
541 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
542 MachineOperand &MO = MI.getOperand(i);
543 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
544 unsigned VirtReg = MO.getReg();
546 bool TakenCareOf = false;
547 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
548 // Check to see if this is a def-and-use vreg operand that we do need
549 // to insert a store for.
550 bool OpTakenCareOf = false;
551 if (MO.isUse() && !DefAndUseVReg.empty()) {
552 for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau)
553 if (DefAndUseVReg[dau].first == i) {
554 VirtReg = DefAndUseVReg[dau].second;
555 OpTakenCareOf = true;
560 if (!OpTakenCareOf) {
561 ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable);
567 // The only vregs left are stack slot definitions.
568 int StackSlot = VRM.getStackSlot(VirtReg);
569 const TargetRegisterClass *RC =
570 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
573 // If this is a def&use operand, and we used a different physreg for
574 // it than the one assigned, make sure to execute the store from the
575 // correct physical register.
576 if (MO.getReg() == VirtReg)
577 PhysReg = VRM.getPhys(VirtReg);
579 PhysReg = MO.getReg();
581 PhysRegsUsed[PhysReg] = true;
582 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
583 DEBUG(std::cerr << "Store:\t" << *next(MII));
584 MI.SetMachineOperandReg(i, PhysReg);
586 // If there is a dead store to this stack slot, nuke it now.
587 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
589 DEBUG(std::cerr << " Killed store:\t" << *LastStore);
591 MBB.erase(LastStore);
593 LastStore = next(MII);
595 // If the stack slot value was previously available in some other
596 // register, change it now. Otherwise, make the register available,
598 std::map<int, unsigned>::iterator SSA =
599 SpillSlotsAvailable.find(StackSlot);
600 if (SSA != SpillSlotsAvailable.end()) {
601 // Remove the record for physreg.
602 PhysRegsAvailable.erase(SSA->second);
603 SpillSlotsAvailable.erase(SSA);
605 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
607 PhysRegsAvailable[PhysReg] = StackSlot;
608 SpillSlotsAvailable[StackSlot] = PhysReg;
609 DEBUG(std::cerr << "Updating SS#" << StackSlot <<" in physreg "
610 << MRI->getName(PhysReg) << " for virtreg #"
625 llvm::Spiller* llvm::createSpiller() {
626 switch (SpillerOpt) {
627 default: assert(0 && "Unreachable!");
629 return new LocalSpiller();
631 return new SimpleSpiller();