1 //===-- llvm/CodeGen/Rewriter.cpp - Rewriter -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "virtregrewriter"
11 #include "VirtRegRewriter.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFrameInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Support/CommandLine.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/ADT/DepthFirstIterator.h"
23 #include "llvm/ADT/Statistic.h"
27 STATISTIC(NumDSE , "Number of dead stores elided");
28 STATISTIC(NumDSS , "Number of dead spill slots removed");
29 STATISTIC(NumCommutes, "Number of instructions commuted");
30 STATISTIC(NumDRM , "Number of re-materializable defs elided");
31 STATISTIC(NumStores , "Number of stores added");
32 STATISTIC(NumPSpills , "Number of physical register spills");
33 STATISTIC(NumOmitted , "Number of reloads omited");
34 STATISTIC(NumAvoided , "Number of reloads deemed unnecessary");
35 STATISTIC(NumCopified, "Number of available reloads turned into copies");
36 STATISTIC(NumReMats , "Number of re-materialization");
37 STATISTIC(NumLoads , "Number of loads added");
38 STATISTIC(NumReused , "Number of values reused");
39 STATISTIC(NumDCE , "Number of copies elided");
40 STATISTIC(NumSUnfold , "Number of stores unfolded");
41 STATISTIC(NumModRefUnfold, "Number of modref unfolded");
44 enum RewriterName { local, trivial };
47 static cl::opt<RewriterName>
48 RewriterOpt("rewriter",
49 cl::desc("Rewriter to use (default=local)"),
51 cl::values(clEnumVal(local, "local rewriter"),
52 clEnumVal(trivial, "trivial rewriter"),
57 ScheduleSpills("schedule-spills",
58 cl::desc("Schedule spill code"),
61 VirtRegRewriter::~VirtRegRewriter() {}
63 /// substitutePhysReg - Replace virtual register in MachineOperand with a
64 /// physical register. Do the right thing with the sub-register index.
65 /// Note that operands may be added, so the MO reference is no longer valid.
66 static void substitutePhysReg(MachineOperand &MO, unsigned Reg,
67 const TargetRegisterInfo &TRI) {
68 if (unsigned SubIdx = MO.getSubReg()) {
69 // Insert the physical subreg and reset the subreg field.
70 MO.setReg(TRI.getSubReg(Reg, SubIdx));
73 // Any def, dead, and kill flags apply to the full virtual register, so they
74 // also apply to the full physical register. Add imp-def/dead and imp-kill
76 MachineInstr &MI = *MO.getParent();
79 MI.addRegisterDead(Reg, &TRI, /*AddIfNotFound=*/ true);
81 MI.addRegisterDefined(Reg, &TRI);
82 else if (!MO.isUndef() &&
84 MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0))))
85 MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true);
93 /// This class is intended for use with the new spilling framework only. It
94 /// rewrites vreg def/uses to use the assigned preg, but does not insert any
96 struct TrivialRewriter : public VirtRegRewriter {
98 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
100 DEBUG(dbgs() << "********** REWRITE MACHINE CODE **********\n");
101 DEBUG(dbgs() << "********** Function: "
102 << MF.getFunction()->getName() << '\n');
103 DEBUG(dbgs() << "**** Machine Instrs"
104 << "(NOTE! Does not include spills and reloads!) ****\n");
107 MachineRegisterInfo *mri = &MF.getRegInfo();
108 const TargetRegisterInfo *tri = MF.getTarget().getRegisterInfo();
110 bool changed = false;
112 for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end();
113 liItr != liEnd; ++liItr) {
115 const LiveInterval *li = liItr->second;
116 unsigned reg = li->reg;
118 if (TargetRegisterInfo::isPhysicalRegister(reg)) {
120 mri->setPhysRegUsed(reg);
123 if (!VRM.hasPhys(reg))
125 unsigned pReg = VRM.getPhys(reg);
126 mri->setPhysRegUsed(pReg);
127 // Copy the register use-list before traversing it.
128 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
129 for (MachineRegisterInfo::reg_iterator I = mri->reg_begin(reg),
130 E = mri->reg_end(); I != E; ++I)
131 reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
132 for (unsigned N=0; N != reglist.size(); ++N)
133 substitutePhysReg(reglist[N].first->getOperand(reglist[N].second),
135 changed |= !reglist.empty();
139 DEBUG(dbgs() << "**** Post Machine Instrs ****\n");
149 // ************************************************************************ //
153 /// AvailableSpills - As the local rewriter is scanning and rewriting an MBB
154 /// from top down, keep track of which spill slots or remat are available in
157 /// Note that not all physregs are created equal here. In particular, some
158 /// physregs are reloads that we are allowed to clobber or ignore at any time.
159 /// Other physregs are values that the register allocated program is using
160 /// that we cannot CHANGE, but we can read if we like. We keep track of this
161 /// on a per-stack-slot / remat id basis as the low bit in the value of the
162 /// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
163 /// this bit and addAvailable sets it if.
164 class AvailableSpills {
165 const TargetRegisterInfo *TRI;
166 const TargetInstrInfo *TII;
168 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
169 // or remat'ed virtual register values that are still available, due to
170 // being loaded or stored to, but not invalidated yet.
171 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
173 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
174 // indicating which stack slot values are currently held by a physreg. This
175 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
176 // physreg is modified.
177 std::multimap<unsigned, int> PhysRegsAvailable;
179 void disallowClobberPhysRegOnly(unsigned PhysReg);
181 void ClobberPhysRegOnly(unsigned PhysReg);
183 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
184 : TRI(tri), TII(tii) {
187 /// clear - Reset the state.
189 SpillSlotsOrReMatsAvailable.clear();
190 PhysRegsAvailable.clear();
193 const TargetRegisterInfo *getRegInfo() const { return TRI; }
195 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
196 /// available in a physical register, return that PhysReg, otherwise
198 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
199 std::map<int, unsigned>::const_iterator I =
200 SpillSlotsOrReMatsAvailable.find(Slot);
201 if (I != SpillSlotsOrReMatsAvailable.end()) {
202 return I->second >> 1; // Remove the CanClobber bit.
207 /// addAvailable - Mark that the specified stack slot / remat is available
208 /// in the specified physreg. If CanClobber is true, the physreg can be
209 /// modified at any time without changing the semantics of the program.
210 void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) {
211 // If this stack slot is thought to be available in some other physreg,
212 // remove its record.
213 ModifyStackSlotOrReMat(SlotOrReMat);
215 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
216 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) |
217 (unsigned)CanClobber;
219 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
220 DEBUG(dbgs() << "Remembering RM#"
221 << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1);
223 DEBUG(dbgs() << "Remembering SS#" << SlotOrReMat);
224 DEBUG(dbgs() << " in physreg " << TRI->getName(Reg) << "\n");
227 /// canClobberPhysRegForSS - Return true if the spiller is allowed to change
228 /// the value of the specified stackslot register if it desires. The
229 /// specified stack slot must be available in a physreg for this query to
231 bool canClobberPhysRegForSS(int SlotOrReMat) const {
232 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
233 "Value not available!");
234 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
237 /// canClobberPhysReg - Return true if the spiller is allowed to clobber the
238 /// physical register where values for some stack slot(s) might be
240 bool canClobberPhysReg(unsigned PhysReg) const {
241 std::multimap<unsigned, int>::const_iterator I =
242 PhysRegsAvailable.lower_bound(PhysReg);
243 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
244 int SlotOrReMat = I->second;
246 if (!canClobberPhysRegForSS(SlotOrReMat))
252 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
253 /// stackslot register. The register is still available but is no longer
254 /// allowed to be modifed.
255 void disallowClobberPhysReg(unsigned PhysReg);
257 /// ClobberPhysReg - This is called when the specified physreg changes
258 /// value. We use this to invalidate any info about stuff that lives in
259 /// it and any of its aliases.
260 void ClobberPhysReg(unsigned PhysReg);
262 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
263 /// slot changes. This removes information about which register the
264 /// previous value for this slot lives in (as the previous value is dead
266 void ModifyStackSlotOrReMat(int SlotOrReMat);
268 /// AddAvailableRegsToLiveIn - Availability information is being kept coming
269 /// into the specified MBB. Add available physical registers as potential
270 /// live-in's. If they are reused in the MBB, they will be added to the
271 /// live-in set to make register scavenger and post-allocation scheduler.
272 void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB, BitVector &RegKills,
273 std::vector<MachineOperand*> &KillOps);
278 // ************************************************************************ //
280 // Given a location where a reload of a spilled register or a remat of
281 // a constant is to be inserted, attempt to find a safe location to
282 // insert the load at an earlier point in the basic-block, to hide
283 // latency of the load and to avoid address-generation interlock
285 static MachineBasicBlock::iterator
286 ComputeReloadLoc(MachineBasicBlock::iterator const InsertLoc,
287 MachineBasicBlock::iterator const Begin,
289 const TargetRegisterInfo *TRI,
292 const TargetInstrInfo *TII,
293 const MachineFunction &MF)
298 // Spill backscheduling is of primary interest to addresses, so
299 // don't do anything if the register isn't in the register class
300 // used for pointers.
302 const TargetLowering *TL = MF.getTarget().getTargetLowering();
304 if (!TL->isTypeLegal(TL->getPointerTy()))
305 // Believe it or not, this is true on PIC16.
308 const TargetRegisterClass *ptrRegClass =
309 TL->getRegClassFor(TL->getPointerTy());
310 if (!ptrRegClass->contains(PhysReg))
313 // Scan upwards through the preceding instructions. If an instruction doesn't
314 // reference the stack slot or the register we're loading, we can
315 // backschedule the reload up past it.
316 MachineBasicBlock::iterator NewInsertLoc = InsertLoc;
317 while (NewInsertLoc != Begin) {
318 MachineBasicBlock::iterator Prev = prior(NewInsertLoc);
319 for (unsigned i = 0; i < Prev->getNumOperands(); ++i) {
320 MachineOperand &Op = Prev->getOperand(i);
321 if (!DoReMat && Op.isFI() && Op.getIndex() == SSorRMId)
324 if (Prev->findRegisterUseOperandIdx(PhysReg) != -1 ||
325 Prev->findRegisterDefOperand(PhysReg))
327 for (const unsigned *Alias = TRI->getAliasSet(PhysReg); *Alias; ++Alias)
328 if (Prev->findRegisterUseOperandIdx(*Alias) != -1 ||
329 Prev->findRegisterDefOperand(*Alias))
335 // If we made it to the beginning of the block, turn around and move back
336 // down just past any existing reloads. They're likely to be reloads/remats
337 // for instructions earlier than what our current reload/remat is for, so
338 // they should be scheduled earlier.
339 if (NewInsertLoc == Begin) {
341 while (InsertLoc != NewInsertLoc &&
342 (TII->isLoadFromStackSlot(NewInsertLoc, FrameIdx) ||
343 TII->isTriviallyReMaterializable(NewInsertLoc)))
352 // ReusedOp - For each reused operand, we keep track of a bit of information,
353 // in case we need to rollback upon processing a new operand. See comments
356 // The MachineInstr operand that reused an available value.
359 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
360 unsigned StackSlotOrReMat;
362 // PhysRegReused - The physical register the value was available in.
363 unsigned PhysRegReused;
365 // AssignedPhysReg - The physreg that was assigned for use by the reload.
366 unsigned AssignedPhysReg;
368 // VirtReg - The virtual register itself.
371 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
373 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
374 AssignedPhysReg(apr), VirtReg(vreg) {}
377 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
378 /// is reused instead of reloaded.
381 std::vector<ReusedOp> Reuses;
382 BitVector PhysRegsClobbered;
384 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
385 PhysRegsClobbered.resize(tri->getNumRegs());
388 bool hasReuses() const {
389 return !Reuses.empty();
392 /// addReuse - If we choose to reuse a virtual register that is already
393 /// available instead of reloading it, remember that we did so.
394 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
395 unsigned PhysRegReused, unsigned AssignedPhysReg,
397 // If the reload is to the assigned register anyway, no undo will be
399 if (PhysRegReused == AssignedPhysReg) return;
401 // Otherwise, remember this.
402 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
403 AssignedPhysReg, VirtReg));
406 void markClobbered(unsigned PhysReg) {
407 PhysRegsClobbered.set(PhysReg);
410 bool isClobbered(unsigned PhysReg) const {
411 return PhysRegsClobbered.test(PhysReg);
414 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
415 /// is some other operand that is using the specified register, either pick
416 /// a new register to use, or evict the previous reload and use this reg.
417 unsigned GetRegForReload(const TargetRegisterClass *RC, unsigned PhysReg,
418 MachineFunction &MF, MachineInstr *MI,
419 AvailableSpills &Spills,
420 std::vector<MachineInstr*> &MaybeDeadStores,
421 SmallSet<unsigned, 8> &Rejected,
423 std::vector<MachineOperand*> &KillOps,
426 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
427 /// 'Rejected' set to remember which registers have been considered and
428 /// rejected for the reload. This avoids infinite looping in case like
431 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
432 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
434 /// sees r1 is taken by t2, tries t2's reload register r0
435 /// sees r0 is taken by t3, tries t3's reload register r1
436 /// sees r1 is taken by t2, tries t2's reload register r0 ...
437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI,
438 AvailableSpills &Spills,
439 std::vector<MachineInstr*> &MaybeDeadStores,
441 std::vector<MachineOperand*> &KillOps,
443 SmallSet<unsigned, 8> Rejected;
444 MachineFunction &MF = *MI->getParent()->getParent();
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
446 return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
447 Rejected, RegKills, KillOps, VRM);
453 // ****************** //
454 // Utility Functions //
455 // ****************** //
457 /// findSinglePredSuccessor - Return via reference a vector of machine basic
458 /// blocks each of which is a successor of the specified BB and has no other
460 static void findSinglePredSuccessor(MachineBasicBlock *MBB,
461 SmallVectorImpl<MachineBasicBlock *> &Succs) {
462 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
463 SE = MBB->succ_end(); SI != SE; ++SI) {
464 MachineBasicBlock *SuccMBB = *SI;
465 if (SuccMBB->pred_size() == 1)
466 Succs.push_back(SuccMBB);
470 /// InvalidateKill - Invalidate register kill information for a specific
471 /// register. This also unsets the kills marker on the last kill operand.
472 static void InvalidateKill(unsigned Reg,
473 const TargetRegisterInfo* TRI,
475 std::vector<MachineOperand*> &KillOps) {
477 KillOps[Reg]->setIsKill(false);
478 // KillOps[Reg] might be a def of a super-register.
479 unsigned KReg = KillOps[Reg]->getReg();
480 KillOps[KReg] = NULL;
481 RegKills.reset(KReg);
482 for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) {
484 KillOps[*SR]->setIsKill(false);
492 /// InvalidateKills - MI is going to be deleted. If any of its operands are
493 /// marked kill, then invalidate the information.
494 static void InvalidateKills(MachineInstr &MI,
495 const TargetRegisterInfo* TRI,
497 std::vector<MachineOperand*> &KillOps,
498 SmallVector<unsigned, 2> *KillRegs = NULL) {
499 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
500 MachineOperand &MO = MI.getOperand(i);
501 if (!MO.isReg() || !MO.isUse() || !MO.isKill() || MO.isUndef())
503 unsigned Reg = MO.getReg();
504 if (TargetRegisterInfo::isVirtualRegister(Reg))
507 KillRegs->push_back(Reg);
508 assert(Reg < KillOps.size());
509 if (KillOps[Reg] == &MO) {
512 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
522 /// InvalidateRegDef - If the def operand of the specified def MI is now dead
523 /// (since its spill instruction is removed), mark it isDead. Also checks if
524 /// the def MI has other definition operands that are not dead. Returns it by
526 static bool InvalidateRegDef(MachineBasicBlock::iterator I,
527 MachineInstr &NewDef, unsigned Reg,
529 const TargetRegisterInfo *TRI) {
530 // Due to remat, it's possible this reg isn't being reused. That is,
531 // the def of this reg (by prev MI) is now dead.
532 MachineInstr *DefMI = I;
533 MachineOperand *DefOp = NULL;
534 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
535 MachineOperand &MO = DefMI->getOperand(i);
536 if (!MO.isReg() || !MO.isDef() || !MO.isKill() || MO.isUndef())
538 if (MO.getReg() == Reg)
540 else if (!MO.isDead())
546 bool FoundUse = false, Done = false;
547 MachineBasicBlock::iterator E = &NewDef;
549 for (; !Done && I != E; ++I) {
550 MachineInstr *NMI = I;
551 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
552 MachineOperand &MO = NMI->getOperand(j);
553 if (!MO.isReg() || MO.getReg() == 0 ||
554 (MO.getReg() != Reg && !TRI->isSubRegister(Reg, MO.getReg())))
558 Done = true; // Stop after scanning all the operands of this MI.
569 /// UpdateKills - Track and update kill info. If a MI reads a register that is
570 /// marked kill, then it must be due to register reuse. Transfer the kill info
572 static void UpdateKills(MachineInstr &MI, const TargetRegisterInfo* TRI,
574 std::vector<MachineOperand*> &KillOps) {
575 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
576 MachineOperand &MO = MI.getOperand(i);
577 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
579 unsigned Reg = MO.getReg();
583 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) {
584 // That can't be right. Register is killed but not re-defined and it's
585 // being reused. Let's fix that.
586 KillOps[Reg]->setIsKill(false);
587 // KillOps[Reg] might be a def of a super-register.
588 unsigned KReg = KillOps[Reg]->getReg();
589 KillOps[KReg] = NULL;
590 RegKills.reset(KReg);
592 // Must be a def of a super-register. Its other sub-regsters are no
593 // longer killed as well.
594 for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) {
599 // Check for subreg kills as well.
605 // = d4 <avoiding reload>
606 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
608 if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI) {
609 KillOps[SReg]->setIsKill(false);
610 unsigned KReg = KillOps[SReg]->getReg();
611 KillOps[KReg] = NULL;
612 RegKills.reset(KReg);
614 for (const unsigned *SSR = TRI->getSubRegisters(KReg); *SSR; ++SSR) {
615 KillOps[*SSR] = NULL;
616 RegKills.reset(*SSR);
625 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
632 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
633 const MachineOperand &MO = MI.getOperand(i);
634 if (!MO.isReg() || !MO.getReg() || !MO.isDef())
636 unsigned Reg = MO.getReg();
639 // It also defines (or partially define) aliases.
640 for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
644 for (const unsigned *SR = TRI->getSuperRegisters(Reg); *SR; ++SR) {
651 /// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
653 static void ReMaterialize(MachineBasicBlock &MBB,
654 MachineBasicBlock::iterator &MII,
655 unsigned DestReg, unsigned Reg,
656 const TargetInstrInfo *TII,
657 const TargetRegisterInfo *TRI,
659 MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
661 const TargetInstrDesc &TID = ReMatDefMI->getDesc();
662 assert(TID.getNumDefs() == 1 &&
663 "Don't know how to remat instructions that define > 1 values!");
665 TII->reMaterialize(MBB, MII, DestReg,
666 ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI, TRI);
667 MachineInstr *NewMI = prior(MII);
668 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
669 MachineOperand &MO = NewMI->getOperand(i);
670 if (!MO.isReg() || MO.getReg() == 0)
672 unsigned VirtReg = MO.getReg();
673 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
676 unsigned Phys = VRM.getPhys(VirtReg);
677 assert(Phys && "Virtual register is not assigned a register?");
678 substitutePhysReg(MO, Phys, *TRI);
683 /// findSuperReg - Find the SubReg's super-register of given register class
684 /// where its SubIdx sub-register is SubReg.
685 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
686 unsigned SubIdx, const TargetRegisterInfo *TRI) {
687 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
690 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
696 // ******************************** //
697 // Available Spills Implementation //
698 // ******************************** //
700 /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
701 /// stackslot register. The register is still available but is no longer
702 /// allowed to be modifed.
703 void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
704 std::multimap<unsigned, int>::iterator I =
705 PhysRegsAvailable.lower_bound(PhysReg);
706 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
707 int SlotOrReMat = I->second;
709 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
710 "Bidirectional map mismatch!");
711 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
712 DEBUG(dbgs() << "PhysReg " << TRI->getName(PhysReg)
713 << " copied, it is available for use but can no longer be modified\n");
717 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
718 /// stackslot register and its aliases. The register and its aliases may
719 /// still available but is no longer allowed to be modifed.
720 void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
721 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
722 disallowClobberPhysRegOnly(*AS);
723 disallowClobberPhysRegOnly(PhysReg);
726 /// ClobberPhysRegOnly - This is called when the specified physreg changes
727 /// value. We use this to invalidate any info about stuff we thing lives in it.
728 void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
729 std::multimap<unsigned, int>::iterator I =
730 PhysRegsAvailable.lower_bound(PhysReg);
731 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
732 int SlotOrReMat = I->second;
733 PhysRegsAvailable.erase(I++);
734 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
735 "Bidirectional map mismatch!");
736 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
737 DEBUG(dbgs() << "PhysReg " << TRI->getName(PhysReg)
738 << " clobbered, invalidating ");
739 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
740 DEBUG(dbgs() << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 <<"\n");
742 DEBUG(dbgs() << "SS#" << SlotOrReMat << "\n");
746 /// ClobberPhysReg - This is called when the specified physreg changes
747 /// value. We use this to invalidate any info about stuff we thing lives in
748 /// it and any of its aliases.
749 void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
750 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
751 ClobberPhysRegOnly(*AS);
752 ClobberPhysRegOnly(PhysReg);
755 /// AddAvailableRegsToLiveIn - Availability information is being kept coming
756 /// into the specified MBB. Add available physical registers as potential
757 /// live-in's. If they are reused in the MBB, they will be added to the
758 /// live-in set to make register scavenger and post-allocation scheduler.
759 void AvailableSpills::AddAvailableRegsToLiveIn(MachineBasicBlock &MBB,
761 std::vector<MachineOperand*> &KillOps) {
762 std::set<unsigned> NotAvailable;
763 for (std::multimap<unsigned, int>::iterator
764 I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end();
766 unsigned Reg = I->first;
767 const TargetRegisterClass* RC = TRI->getPhysicalRegisterRegClass(Reg);
768 // FIXME: A temporary workaround. We can't reuse available value if it's
769 // not safe to move the def of the virtual register's class. e.g.
770 // X86::RFP* register classes. Do not add it as a live-in.
771 if (!TII->isSafeToMoveRegClassDefs(RC))
772 // This is no longer available.
773 NotAvailable.insert(Reg);
776 InvalidateKill(Reg, TRI, RegKills, KillOps);
779 // Skip over the same register.
780 std::multimap<unsigned, int>::iterator NI = llvm::next(I);
781 while (NI != E && NI->first == Reg) {
787 for (std::set<unsigned>::iterator I = NotAvailable.begin(),
788 E = NotAvailable.end(); I != E; ++I) {
790 for (const unsigned *SubRegs = TRI->getSubRegisters(*I);
792 ClobberPhysReg(*SubRegs);
796 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
797 /// slot changes. This removes information about which register the previous
798 /// value for this slot lives in (as the previous value is dead now).
799 void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
800 std::map<int, unsigned>::iterator It =
801 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
802 if (It == SpillSlotsOrReMatsAvailable.end()) return;
803 unsigned Reg = It->second >> 1;
804 SpillSlotsOrReMatsAvailable.erase(It);
806 // This register may hold the value of multiple stack slots, only remove this
807 // stack slot from the set of values the register contains.
808 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
810 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
811 "Map inverse broken!");
812 if (I->second == SlotOrReMat) break;
814 PhysRegsAvailable.erase(I);
817 // ************************** //
818 // Reuse Info Implementation //
819 // ************************** //
821 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
822 /// is some other operand that is using the specified register, either pick
823 /// a new register to use, or evict the previous reload and use this reg.
824 unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
827 MachineInstr *MI, AvailableSpills &Spills,
828 std::vector<MachineInstr*> &MaybeDeadStores,
829 SmallSet<unsigned, 8> &Rejected,
831 std::vector<MachineOperand*> &KillOps,
833 const TargetInstrInfo* TII = MF.getTarget().getInstrInfo();
834 const TargetRegisterInfo *TRI = Spills.getRegInfo();
836 if (Reuses.empty()) return PhysReg; // This is most often empty.
838 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
839 ReusedOp &Op = Reuses[ro];
840 // If we find some other reuse that was supposed to use this register
841 // exactly for its reload, we can change this reload to use ITS reload
842 // register. That is, unless its reload register has already been
843 // considered and subsequently rejected because it has also been reused
844 // by another operand.
845 if (Op.PhysRegReused == PhysReg &&
846 Rejected.count(Op.AssignedPhysReg) == 0 &&
847 RC->contains(Op.AssignedPhysReg)) {
848 // Yup, use the reload register that we didn't use before.
849 unsigned NewReg = Op.AssignedPhysReg;
850 Rejected.insert(PhysReg);
851 return GetRegForReload(RC, NewReg, MF, MI, Spills, MaybeDeadStores, Rejected,
852 RegKills, KillOps, VRM);
854 // Otherwise, we might also have a problem if a previously reused
855 // value aliases the new register. If so, codegen the previous reload
857 unsigned PRRU = Op.PhysRegReused;
858 if (TRI->regsOverlap(PRRU, PhysReg)) {
859 // Okay, we found out that an alias of a reused register
860 // was used. This isn't good because it means we have
861 // to undo a previous reuse.
862 MachineBasicBlock *MBB = MI->getParent();
863 const TargetRegisterClass *AliasRC =
864 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
866 // Copy Op out of the vector and remove it, we're going to insert an
867 // explicit load for it.
869 Reuses.erase(Reuses.begin()+ro);
871 // MI may be using only a sub-register of PhysRegUsed.
872 unsigned RealPhysRegUsed = MI->getOperand(NewOp.Operand).getReg();
874 assert(TargetRegisterInfo::isPhysicalRegister(RealPhysRegUsed) &&
875 "A reuse cannot be a virtual register");
876 if (PRRU != RealPhysRegUsed) {
877 // What was the sub-register index?
878 SubIdx = TRI->getSubRegIndex(PRRU, RealPhysRegUsed);
880 "Operand physreg is not a sub-register of PhysRegUsed");
883 // Ok, we're going to try to reload the assigned physreg into the
884 // slot that we were supposed to in the first place. However, that
885 // register could hold a reuse. Check to see if it conflicts or
886 // would prefer us to use a different register.
887 unsigned NewPhysReg = GetRegForReload(RC, NewOp.AssignedPhysReg,
888 MF, MI, Spills, MaybeDeadStores,
889 Rejected, RegKills, KillOps, VRM);
891 bool DoReMat = NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT;
892 int SSorRMId = DoReMat
893 ? VRM.getReMatId(NewOp.VirtReg) : NewOp.StackSlotOrReMat;
895 // Back-schedule reloads and remats.
896 MachineBasicBlock::iterator InsertLoc =
897 ComputeReloadLoc(MI, MBB->begin(), PhysReg, TRI,
898 DoReMat, SSorRMId, TII, MF);
901 ReMaterialize(*MBB, InsertLoc, NewPhysReg, NewOp.VirtReg, TII,
904 TII->loadRegFromStackSlot(*MBB, InsertLoc, NewPhysReg,
905 NewOp.StackSlotOrReMat, AliasRC);
906 MachineInstr *LoadMI = prior(InsertLoc);
907 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
908 // Any stores to this stack slot are not dead anymore.
909 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
912 Spills.ClobberPhysReg(NewPhysReg);
913 Spills.ClobberPhysReg(NewOp.PhysRegReused);
915 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) :NewPhysReg;
916 MI->getOperand(NewOp.Operand).setReg(RReg);
917 MI->getOperand(NewOp.Operand).setSubReg(0);
919 Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg);
920 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
921 DEBUG(dbgs() << '\t' << *prior(InsertLoc));
923 DEBUG(dbgs() << "Reuse undone!\n");
926 // Finally, PhysReg is now available, go ahead and use it.
934 // ************************************************************************ //
936 /// FoldsStackSlotModRef - Return true if the specified MI folds the specified
937 /// stack slot mod/ref. It also checks if it's possible to unfold the
938 /// instruction by having it define a specified physical register instead.
939 static bool FoldsStackSlotModRef(MachineInstr &MI, int SS, unsigned PhysReg,
940 const TargetInstrInfo *TII,
941 const TargetRegisterInfo *TRI,
943 if (VRM.hasEmergencySpills(&MI) || VRM.isSpillPt(&MI))
947 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
948 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
949 unsigned VirtReg = I->second.first;
950 VirtRegMap::ModRef MR = I->second.second;
951 if (MR & VirtRegMap::isModRef)
952 if (VRM.getStackSlot(VirtReg) == SS) {
953 Found= TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), true, true) != 0;
960 // Does the instruction uses a register that overlaps the scratch register?
961 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
962 MachineOperand &MO = MI.getOperand(i);
963 if (!MO.isReg() || MO.getReg() == 0)
965 unsigned Reg = MO.getReg();
966 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
967 if (!VRM.hasPhys(Reg))
969 Reg = VRM.getPhys(Reg);
971 if (TRI->regsOverlap(PhysReg, Reg))
977 /// FindFreeRegister - Find a free register of a given register class by looking
978 /// at (at most) the last two machine instructions.
979 static unsigned FindFreeRegister(MachineBasicBlock::iterator MII,
980 MachineBasicBlock &MBB,
981 const TargetRegisterClass *RC,
982 const TargetRegisterInfo *TRI,
983 BitVector &AllocatableRegs) {
984 BitVector Defs(TRI->getNumRegs());
985 BitVector Uses(TRI->getNumRegs());
986 SmallVector<unsigned, 4> LocalUses;
987 SmallVector<unsigned, 4> Kills;
989 // Take a look at 2 instructions at most.
990 for (unsigned Count = 0; Count < 2; ++Count) {
991 if (MII == MBB.begin())
993 MachineInstr *PrevMI = prior(MII);
994 for (unsigned i = 0, e = PrevMI->getNumOperands(); i != e; ++i) {
995 MachineOperand &MO = PrevMI->getOperand(i);
996 if (!MO.isReg() || MO.getReg() == 0)
998 unsigned Reg = MO.getReg();
1001 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
1004 LocalUses.push_back(Reg);
1005 if (MO.isKill() && AllocatableRegs[Reg])
1006 Kills.push_back(Reg);
1010 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
1011 unsigned Kill = Kills[i];
1012 if (!Defs[Kill] && !Uses[Kill] &&
1013 TRI->getPhysicalRegisterRegClass(Kill) == RC)
1016 for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
1017 unsigned Reg = LocalUses[i];
1019 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
1030 void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg,
1031 const TargetRegisterInfo &TRI) {
1032 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1033 MachineOperand &MO = MI->getOperand(i);
1034 if (MO.isReg() && MO.getReg() == VirtReg)
1035 substitutePhysReg(MO, PhysReg, TRI);
1041 bool operator()(const std::pair<MachineInstr*, int> &A,
1042 const std::pair<MachineInstr*, int> &B) {
1043 return A.second < B.second;
1048 // ***************************** //
1049 // Local Spiller Implementation //
1050 // ***************************** //
1054 class LocalRewriter : public VirtRegRewriter {
1055 MachineRegisterInfo *RegInfo;
1056 const TargetRegisterInfo *TRI;
1057 const TargetInstrInfo *TII;
1058 BitVector AllocatableRegs;
1059 DenseMap<MachineInstr*, unsigned> DistanceMap;
1062 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
1063 LiveIntervals* LIs) {
1064 RegInfo = &MF.getRegInfo();
1065 TRI = MF.getTarget().getRegisterInfo();
1066 TII = MF.getTarget().getInstrInfo();
1067 AllocatableRegs = TRI->getAllocatableSet(MF);
1068 DEBUG(dbgs() << "\n**** Local spiller rewriting function '"
1069 << MF.getFunction()->getName() << "':\n");
1070 DEBUG(dbgs() << "**** Machine Instrs (NOTE! Does not include spills and"
1071 " reloads!) ****\n");
1074 // Spills - Keep track of which spilled values are available in physregs
1075 // so that we can choose to reuse the physregs instead of emitting
1076 // reloads. This is usually refreshed per basic block.
1077 AvailableSpills Spills(TRI, TII);
1079 // Keep track of kill information.
1080 BitVector RegKills(TRI->getNumRegs());
1081 std::vector<MachineOperand*> KillOps;
1082 KillOps.resize(TRI->getNumRegs(), NULL);
1084 // SingleEntrySuccs - Successor blocks which have a single predecessor.
1085 SmallVector<MachineBasicBlock*, 4> SinglePredSuccs;
1086 SmallPtrSet<MachineBasicBlock*,16> EarlyVisited;
1088 // Traverse the basic blocks depth first.
1089 MachineBasicBlock *Entry = MF.begin();
1090 SmallPtrSet<MachineBasicBlock*,16> Visited;
1091 for (df_ext_iterator<MachineBasicBlock*,
1092 SmallPtrSet<MachineBasicBlock*,16> >
1093 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1095 MachineBasicBlock *MBB = *DFI;
1096 if (!EarlyVisited.count(MBB))
1097 RewriteMBB(*MBB, VRM, LIs, Spills, RegKills, KillOps);
1099 // If this MBB is the only predecessor of a successor. Keep the
1100 // availability information and visit it next.
1102 // Keep visiting single predecessor successor as long as possible.
1103 SinglePredSuccs.clear();
1104 findSinglePredSuccessor(MBB, SinglePredSuccs);
1105 if (SinglePredSuccs.empty())
1108 // FIXME: More than one successors, each of which has MBB has
1109 // the only predecessor.
1110 MBB = SinglePredSuccs[0];
1111 if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) {
1112 Spills.AddAvailableRegsToLiveIn(*MBB, RegKills, KillOps);
1113 RewriteMBB(*MBB, VRM, LIs, Spills, RegKills, KillOps);
1118 // Clear the availability info.
1122 DEBUG(dbgs() << "**** Post Machine Instrs ****\n");
1125 // Mark unused spill slots.
1126 MachineFrameInfo *MFI = MF.getFrameInfo();
1127 int SS = VRM.getLowSpillSlot();
1128 if (SS != VirtRegMap::NO_STACK_SLOT)
1129 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
1130 if (!VRM.isSpillSlotUsed(SS)) {
1131 MFI->RemoveStackObject(SS);
1140 /// OptimizeByUnfold2 - Unfold a series of load / store folding instructions if
1141 /// a scratch register is available.
1142 /// xorq %r12<kill>, %r13
1143 /// addq %rax, -184(%rbp)
1144 /// addq %r13, -184(%rbp)
1146 /// xorq %r12<kill>, %r13
1147 /// movq -184(%rbp), %r12
1150 /// movq %r12, -184(%rbp)
1151 bool OptimizeByUnfold2(unsigned VirtReg, int SS,
1152 MachineBasicBlock &MBB,
1153 MachineBasicBlock::iterator &MII,
1154 std::vector<MachineInstr*> &MaybeDeadStores,
1155 AvailableSpills &Spills,
1156 BitVector &RegKills,
1157 std::vector<MachineOperand*> &KillOps,
1160 MachineBasicBlock::iterator NextMII = llvm::next(MII);
1161 if (NextMII == MBB.end())
1164 if (TII->getOpcodeAfterMemoryUnfold(MII->getOpcode(), true, true) == 0)
1167 // Now let's see if the last couple of instructions happens to have freed up
1169 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1170 unsigned PhysReg = FindFreeRegister(MII, MBB, RC, TRI, AllocatableRegs);
1174 MachineFunction &MF = *MBB.getParent();
1175 TRI = MF.getTarget().getRegisterInfo();
1176 MachineInstr &MI = *MII;
1177 if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, VRM))
1180 // If the next instruction also folds the same SS modref and can be unfoled,
1181 // then it's worthwhile to issue a load from SS into the free register and
1182 // then unfold these instructions.
1183 if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM))
1186 // Back-schedule reloads and remats.
1187 ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
1189 // Load from SS to the spare physical register.
1190 TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
1191 // This invalidates Phys.
1192 Spills.ClobberPhysReg(PhysReg);
1193 // Remember it's available.
1194 Spills.addAvailable(SS, PhysReg);
1195 MaybeDeadStores[SS] = NULL;
1197 // Unfold current MI.
1198 SmallVector<MachineInstr*, 4> NewMIs;
1199 if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
1200 llvm_unreachable("Unable unfold the load / store folding instruction!");
1201 assert(NewMIs.size() == 1);
1202 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
1203 VRM.transferRestorePts(&MI, NewMIs[0]);
1204 MII = MBB.insert(MII, NewMIs[0]);
1205 InvalidateKills(MI, TRI, RegKills, KillOps);
1206 VRM.RemoveMachineInstrFromMaps(&MI);
1210 // Unfold next instructions that fold the same SS.
1212 MachineInstr &NextMI = *NextMII;
1213 NextMII = llvm::next(NextMII);
1215 if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
1216 llvm_unreachable("Unable unfold the load / store folding instruction!");
1217 assert(NewMIs.size() == 1);
1218 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
1219 VRM.transferRestorePts(&NextMI, NewMIs[0]);
1220 MBB.insert(NextMII, NewMIs[0]);
1221 InvalidateKills(NextMI, TRI, RegKills, KillOps);
1222 VRM.RemoveMachineInstrFromMaps(&NextMI);
1225 if (NextMII == MBB.end())
1227 } while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM));
1229 // Store the value back into SS.
1230 TII->storeRegToStackSlot(MBB, NextMII, PhysReg, true, SS, RC);
1231 MachineInstr *StoreMI = prior(NextMII);
1232 VRM.addSpillSlotUse(SS, StoreMI);
1233 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1238 /// OptimizeByUnfold - Turn a store folding instruction into a load folding
1239 /// instruction. e.g.
1241 /// movl %eax, -32(%ebp)
1242 /// movl -36(%ebp), %eax
1243 /// orl %eax, -32(%ebp)
1246 /// orl -36(%ebp), %eax
1247 /// mov %eax, -32(%ebp)
1248 /// This enables unfolding optimization for a subsequent instruction which will
1249 /// also eliminate the newly introduced store instruction.
1250 bool OptimizeByUnfold(MachineBasicBlock &MBB,
1251 MachineBasicBlock::iterator &MII,
1252 std::vector<MachineInstr*> &MaybeDeadStores,
1253 AvailableSpills &Spills,
1254 BitVector &RegKills,
1255 std::vector<MachineOperand*> &KillOps,
1257 MachineFunction &MF = *MBB.getParent();
1258 MachineInstr &MI = *MII;
1259 unsigned UnfoldedOpc = 0;
1260 unsigned UnfoldPR = 0;
1261 unsigned UnfoldVR = 0;
1262 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
1263 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1264 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
1265 // Only transform a MI that folds a single register.
1268 UnfoldVR = I->second.first;
1269 VirtRegMap::ModRef MR = I->second.second;
1270 // MI2VirtMap be can updated which invalidate the iterator.
1271 // Increment the iterator first.
1273 if (VRM.isAssignedReg(UnfoldVR))
1275 // If this reference is not a use, any previous store is now dead.
1276 // Otherwise, the store to this stack slot is not dead anymore.
1277 FoldedSS = VRM.getStackSlot(UnfoldVR);
1278 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
1279 if (DeadStore && (MR & VirtRegMap::isModRef)) {
1280 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
1281 if (!PhysReg || !DeadStore->readsRegister(PhysReg))
1284 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1293 // Look for other unfolding opportunities.
1294 return OptimizeByUnfold2(UnfoldVR, FoldedSS, MBB, MII,
1295 MaybeDeadStores, Spills, RegKills, KillOps, VRM);
1298 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1299 MachineOperand &MO = MI.getOperand(i);
1300 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
1302 unsigned VirtReg = MO.getReg();
1303 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
1305 if (VRM.isAssignedReg(VirtReg)) {
1306 unsigned PhysReg = VRM.getPhys(VirtReg);
1307 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
1309 } else if (VRM.isReMaterialized(VirtReg))
1311 int SS = VRM.getStackSlot(VirtReg);
1312 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1314 if (TRI->regsOverlap(PhysReg, UnfoldPR))
1318 if (VRM.hasPhys(VirtReg)) {
1319 PhysReg = VRM.getPhys(VirtReg);
1320 if (!TRI->regsOverlap(PhysReg, UnfoldPR))
1324 // Ok, we'll need to reload the value into a register which makes
1325 // it impossible to perform the store unfolding optimization later.
1326 // Let's see if it is possible to fold the load if the store is
1327 // unfolded. This allows us to perform the store unfolding
1329 SmallVector<MachineInstr*, 4> NewMIs;
1330 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
1331 assert(NewMIs.size() == 1);
1332 MachineInstr *NewMI = NewMIs.back();
1334 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
1336 SmallVector<unsigned, 1> Ops;
1338 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
1340 VRM.addSpillSlotUse(SS, FoldedMI);
1341 if (!VRM.hasPhys(UnfoldVR))
1342 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
1343 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1344 MII = MBB.insert(MII, FoldedMI);
1345 InvalidateKills(MI, TRI, RegKills, KillOps);
1346 VRM.RemoveMachineInstrFromMaps(&MI);
1348 MF.DeleteMachineInstr(NewMI);
1351 MF.DeleteMachineInstr(NewMI);
1358 /// CommuteChangesDestination - We are looking for r0 = op r1, r2 and
1359 /// where SrcReg is r1 and it is tied to r0. Return true if after
1360 /// commuting this instruction it will be r0 = op r2, r1.
1361 static bool CommuteChangesDestination(MachineInstr *DefMI,
1362 const TargetInstrDesc &TID,
1364 const TargetInstrInfo *TII,
1366 if (TID.getNumDefs() != 1 && TID.getNumOperands() != 3)
1368 if (!DefMI->getOperand(1).isReg() ||
1369 DefMI->getOperand(1).getReg() != SrcReg)
1372 if (!DefMI->isRegTiedToDefOperand(1, &DefIdx) || DefIdx != 0)
1374 unsigned SrcIdx1, SrcIdx2;
1375 if (!TII->findCommutedOpIndices(DefMI, SrcIdx1, SrcIdx2))
1377 if (SrcIdx1 == 1 && SrcIdx2 == 2) {
1384 /// CommuteToFoldReload -
1387 /// r1 = op r1, r2<kill>
1390 /// If op is commutable and r2 is killed, then we can xform these to
1391 /// r2 = op r2, fi#1
1393 bool CommuteToFoldReload(MachineBasicBlock &MBB,
1394 MachineBasicBlock::iterator &MII,
1395 unsigned VirtReg, unsigned SrcReg, int SS,
1396 AvailableSpills &Spills,
1397 BitVector &RegKills,
1398 std::vector<MachineOperand*> &KillOps,
1399 const TargetRegisterInfo *TRI,
1401 if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
1404 MachineFunction &MF = *MBB.getParent();
1405 MachineInstr &MI = *MII;
1406 MachineBasicBlock::iterator DefMII = prior(MII);
1407 MachineInstr *DefMI = DefMII;
1408 const TargetInstrDesc &TID = DefMI->getDesc();
1410 if (DefMII != MBB.begin() &&
1411 TID.isCommutable() &&
1412 CommuteChangesDestination(DefMI, TID, SrcReg, TII, NewDstIdx)) {
1413 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
1414 unsigned NewReg = NewDstMO.getReg();
1415 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
1417 MachineInstr *ReloadMI = prior(DefMII);
1419 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
1420 if (DestReg != SrcReg || FrameIdx != SS)
1422 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
1426 if (!MI.isRegTiedToDefOperand(UseIdx, &DefIdx))
1428 assert(DefMI->getOperand(DefIdx).isReg() &&
1429 DefMI->getOperand(DefIdx).getReg() == SrcReg);
1431 // Now commute def instruction.
1432 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true);
1435 SmallVector<unsigned, 1> Ops;
1436 Ops.push_back(NewDstIdx);
1437 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
1438 // Not needed since foldMemoryOperand returns new MI.
1439 MF.DeleteMachineInstr(CommutedMI);
1443 VRM.addSpillSlotUse(SS, FoldedMI);
1444 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1445 // Insert new def MI and spill MI.
1446 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1447 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
1449 MachineInstr *StoreMI = MII;
1450 VRM.addSpillSlotUse(SS, StoreMI);
1451 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1452 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack.
1454 // Delete all 3 old instructions.
1455 InvalidateKills(*ReloadMI, TRI, RegKills, KillOps);
1456 VRM.RemoveMachineInstrFromMaps(ReloadMI);
1457 MBB.erase(ReloadMI);
1458 InvalidateKills(*DefMI, TRI, RegKills, KillOps);
1459 VRM.RemoveMachineInstrFromMaps(DefMI);
1461 InvalidateKills(MI, TRI, RegKills, KillOps);
1462 VRM.RemoveMachineInstrFromMaps(&MI);
1465 // If NewReg was previously holding value of some SS, it's now clobbered.
1466 // This has to be done now because it's a physical register. When this
1467 // instruction is re-visited, it's ignored.
1468 Spills.ClobberPhysReg(NewReg);
1477 /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
1478 /// the last store to the same slot is now dead. If so, remove the last store.
1479 void SpillRegToStackSlot(MachineBasicBlock &MBB,
1480 MachineBasicBlock::iterator &MII,
1481 int Idx, unsigned PhysReg, int StackSlot,
1482 const TargetRegisterClass *RC,
1483 bool isAvailable, MachineInstr *&LastStore,
1484 AvailableSpills &Spills,
1485 SmallSet<MachineInstr*, 4> &ReMatDefs,
1486 BitVector &RegKills,
1487 std::vector<MachineOperand*> &KillOps,
1490 MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
1491 TII->storeRegToStackSlot(MBB, llvm::next(MII), PhysReg, true, StackSlot, RC);
1492 MachineInstr *StoreMI = prior(oldNextMII);
1493 VRM.addSpillSlotUse(StackSlot, StoreMI);
1494 DEBUG(dbgs() << "Store:\t" << *StoreMI);
1496 // If there is a dead store to this stack slot, nuke it now.
1498 DEBUG(dbgs() << "Removed dead store:\t" << *LastStore);
1500 SmallVector<unsigned, 2> KillRegs;
1501 InvalidateKills(*LastStore, TRI, RegKills, KillOps, &KillRegs);
1502 MachineBasicBlock::iterator PrevMII = LastStore;
1503 bool CheckDef = PrevMII != MBB.begin();
1506 VRM.RemoveMachineInstrFromMaps(LastStore);
1507 MBB.erase(LastStore);
1509 // Look at defs of killed registers on the store. Mark the defs
1510 // as dead since the store has been deleted and they aren't
1512 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1513 bool HasOtherDef = false;
1514 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef, TRI)) {
1515 MachineInstr *DeadDef = PrevMII;
1516 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1517 // FIXME: This assumes a remat def does not have side effects.
1518 VRM.RemoveMachineInstrFromMaps(DeadDef);
1527 // Allow for multi-instruction spill sequences, as on PPC Altivec. Presume
1528 // the last of multiple instructions is the actual store.
1529 LastStore = prior(oldNextMII);
1531 // If the stack slot value was previously available in some other
1532 // register, change it now. Otherwise, make the register available,
1534 Spills.ModifyStackSlotOrReMat(StackSlot);
1535 Spills.ClobberPhysReg(PhysReg);
1536 Spills.addAvailable(StackSlot, PhysReg, isAvailable);
1540 /// isSafeToDelete - Return true if this instruction doesn't produce any side
1541 /// effect and all of its defs are dead.
1542 static bool isSafeToDelete(MachineInstr &MI) {
1543 const TargetInstrDesc &TID = MI.getDesc();
1544 if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
1545 TID.isCall() || TID.isBarrier() || TID.isReturn() ||
1546 TID.hasUnmodeledSideEffects())
1548 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1549 MachineOperand &MO = MI.getOperand(i);
1550 if (!MO.isReg() || !MO.getReg())
1552 if (MO.isDef() && !MO.isDead())
1554 if (MO.isUse() && MO.isKill())
1555 // FIXME: We can't remove kill markers or else the scavenger will assert.
1556 // An alternative is to add a ADD pseudo instruction to replace kill
1563 /// TransferDeadness - A identity copy definition is dead and it's being
1564 /// removed. Find the last def or use and mark it as dead / kill.
1565 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
1566 unsigned Reg, BitVector &RegKills,
1567 std::vector<MachineOperand*> &KillOps,
1569 SmallPtrSet<MachineInstr*, 4> Seens;
1570 SmallVector<std::pair<MachineInstr*, int>,8> Refs;
1571 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
1572 RE = RegInfo->reg_end(); RI != RE; ++RI) {
1573 MachineInstr *UDMI = &*RI;
1574 if (UDMI->getParent() != MBB)
1576 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
1577 if (DI == DistanceMap.end() || DI->second > CurDist)
1579 if (Seens.insert(UDMI))
1580 Refs.push_back(std::make_pair(UDMI, DI->second));
1585 std::sort(Refs.begin(), Refs.end(), RefSorter());
1587 while (!Refs.empty()) {
1588 MachineInstr *LastUDMI = Refs.back().first;
1591 MachineOperand *LastUD = NULL;
1592 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
1593 MachineOperand &MO = LastUDMI->getOperand(i);
1594 if (!MO.isReg() || MO.getReg() != Reg)
1596 if (!LastUD || (LastUD->isUse() && MO.isDef()))
1598 if (LastUDMI->isRegTiedToDefOperand(i))
1601 if (LastUD->isDef()) {
1602 // If the instruction has no side effect, delete it and propagate
1603 // backward further. Otherwise, mark is dead and we are done.
1604 if (!isSafeToDelete(*LastUDMI)) {
1605 LastUD->setIsDead();
1608 VRM.RemoveMachineInstrFromMaps(LastUDMI);
1609 MBB->erase(LastUDMI);
1611 LastUD->setIsKill();
1613 KillOps[Reg] = LastUD;
1619 /// rewriteMBB - Keep track of which spills are available even after the
1620 /// register allocator is done with them. If possible, avid reloading vregs.
1621 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
1623 AvailableSpills &Spills, BitVector &RegKills,
1624 std::vector<MachineOperand*> &KillOps) {
1626 DEBUG(dbgs() << "\n**** Local spiller rewriting MBB '"
1627 << MBB.getName() << "':\n");
1629 MachineFunction &MF = *MBB.getParent();
1631 // MaybeDeadStores - When we need to write a value back into a stack slot,
1632 // keep track of the inserted store. If the stack slot value is never read
1633 // (because the value was used from some available register, for example), and
1634 // subsequently stored to, the original store is dead. This map keeps track
1635 // of inserted stores that are not used. If we see a subsequent store to the
1636 // same stack slot, the original store is deleted.
1637 std::vector<MachineInstr*> MaybeDeadStores;
1638 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
1640 // ReMatDefs - These are rematerializable def MIs which are not deleted.
1641 SmallSet<MachineInstr*, 4> ReMatDefs;
1644 SmallSet<unsigned, 2> KilledMIRegs;
1647 KillOps.resize(TRI->getNumRegs(), NULL);
1650 DistanceMap.clear();
1651 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
1653 MachineBasicBlock::iterator NextMII = llvm::next(MII);
1655 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1656 bool Erased = false;
1657 bool BackTracked = false;
1658 if (OptimizeByUnfold(MBB, MII,
1659 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
1660 NextMII = llvm::next(MII);
1662 MachineInstr &MI = *MII;
1664 if (VRM.hasEmergencySpills(&MI)) {
1665 // Spill physical register(s) in the rare case the allocator has run out
1666 // of registers to allocate.
1667 SmallSet<int, 4> UsedSS;
1668 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
1669 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
1670 unsigned PhysReg = EmSpills[i];
1671 const TargetRegisterClass *RC =
1672 TRI->getPhysicalRegisterRegClass(PhysReg);
1673 assert(RC && "Unable to determine register class!");
1674 int SS = VRM.getEmergencySpillSlot(RC);
1675 if (UsedSS.count(SS))
1676 llvm_unreachable("Need to spill more than one physical registers!");
1678 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
1679 MachineInstr *StoreMI = prior(MII);
1680 VRM.addSpillSlotUse(SS, StoreMI);
1682 // Back-schedule reloads and remats.
1683 MachineBasicBlock::iterator InsertLoc =
1684 ComputeReloadLoc(llvm::next(MII), MBB.begin(), PhysReg, TRI, false,
1687 TII->loadRegFromStackSlot(MBB, InsertLoc, PhysReg, SS, RC);
1689 MachineInstr *LoadMI = prior(InsertLoc);
1690 VRM.addSpillSlotUse(SS, LoadMI);
1692 DistanceMap.insert(std::make_pair(LoadMI, Dist++));
1694 NextMII = llvm::next(MII);
1697 // Insert restores here if asked to.
1698 if (VRM.isRestorePt(&MI)) {
1699 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
1700 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
1701 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
1702 if (!VRM.getPreSplitReg(VirtReg))
1703 continue; // Split interval spilled again.
1704 unsigned Phys = VRM.getPhys(VirtReg);
1705 RegInfo->setPhysRegUsed(Phys);
1707 // Check if the value being restored if available. If so, it must be
1708 // from a predecessor BB that fallthrough into this BB. We do not
1714 // ... # r1 not clobbered
1717 bool DoReMat = VRM.isReMaterialized(VirtReg);
1718 int SSorRMId = DoReMat
1719 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1720 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1721 unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1722 if (InReg == Phys) {
1723 // If the value is already available in the expected register, save
1724 // a reload / remat.
1726 DEBUG(dbgs() << "Reusing RM#"
1727 << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1);
1729 DEBUG(dbgs() << "Reusing SS#" << SSorRMId);
1730 DEBUG(dbgs() << " from physreg "
1731 << TRI->getName(InReg) << " for vreg"
1732 << VirtReg <<" instead of reloading into physreg "
1733 << TRI->getName(Phys) << '\n');
1736 } else if (InReg && InReg != Phys) {
1738 DEBUG(dbgs() << "Reusing RM#"
1739 << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1);
1741 DEBUG(dbgs() << "Reusing SS#" << SSorRMId);
1742 DEBUG(dbgs() << " from physreg "
1743 << TRI->getName(InReg) << " for vreg"
1744 << VirtReg <<" by copying it into physreg "
1745 << TRI->getName(Phys) << '\n');
1747 // If the reloaded / remat value is available in another register,
1748 // copy it to the desired register.
1750 // Back-schedule reloads and remats.
1751 MachineBasicBlock::iterator InsertLoc =
1752 ComputeReloadLoc(MII, MBB.begin(), Phys, TRI, DoReMat,
1755 TII->copyRegToReg(MBB, InsertLoc, Phys, InReg, RC, RC);
1757 // This invalidates Phys.
1758 Spills.ClobberPhysReg(Phys);
1759 // Remember it's available.
1760 Spills.addAvailable(SSorRMId, Phys);
1763 MachineInstr *CopyMI = prior(InsertLoc);
1764 CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
1765 MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg);
1766 KillOpnd->setIsKill();
1767 UpdateKills(*CopyMI, TRI, RegKills, KillOps);
1769 DEBUG(dbgs() << '\t' << *CopyMI);
1774 // Back-schedule reloads and remats.
1775 MachineBasicBlock::iterator InsertLoc =
1776 ComputeReloadLoc(MII, MBB.begin(), Phys, TRI, DoReMat,
1779 if (VRM.isReMaterialized(VirtReg)) {
1780 ReMaterialize(MBB, InsertLoc, Phys, VirtReg, TII, TRI, VRM);
1782 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1783 TII->loadRegFromStackSlot(MBB, InsertLoc, Phys, SSorRMId, RC);
1784 MachineInstr *LoadMI = prior(InsertLoc);
1785 VRM.addSpillSlotUse(SSorRMId, LoadMI);
1787 DistanceMap.insert(std::make_pair(LoadMI, Dist++));
1790 // This invalidates Phys.
1791 Spills.ClobberPhysReg(Phys);
1792 // Remember it's available.
1793 Spills.addAvailable(SSorRMId, Phys);
1795 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
1796 DEBUG(dbgs() << '\t' << *prior(MII));
1800 // Insert spills here if asked to.
1801 if (VRM.isSpillPt(&MI)) {
1802 std::vector<std::pair<unsigned,bool> > &SpillRegs =
1803 VRM.getSpillPtSpills(&MI);
1804 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
1805 unsigned VirtReg = SpillRegs[i].first;
1806 bool isKill = SpillRegs[i].second;
1807 if (!VRM.getPreSplitReg(VirtReg))
1808 continue; // Split interval spilled again.
1809 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1810 unsigned Phys = VRM.getPhys(VirtReg);
1811 int StackSlot = VRM.getStackSlot(VirtReg);
1812 MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
1813 TII->storeRegToStackSlot(MBB, llvm::next(MII), Phys, isKill, StackSlot, RC);
1814 MachineInstr *StoreMI = prior(oldNextMII);
1815 VRM.addSpillSlotUse(StackSlot, StoreMI);
1816 DEBUG(dbgs() << "Store:\t" << *StoreMI);
1817 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1819 NextMII = llvm::next(MII);
1822 /// ReusedOperands - Keep track of operand reuse in case we need to undo
1824 ReuseInfo ReusedOperands(MI, TRI);
1825 SmallVector<unsigned, 4> VirtUseOps;
1826 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1827 MachineOperand &MO = MI.getOperand(i);
1828 if (!MO.isReg() || MO.getReg() == 0)
1829 continue; // Ignore non-register operands.
1831 unsigned VirtReg = MO.getReg();
1832 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
1833 // Ignore physregs for spilling, but remember that it is used by this
1835 RegInfo->setPhysRegUsed(VirtReg);
1839 // We want to process implicit virtual register uses first.
1840 if (MO.isImplicit())
1841 // If the virtual register is implicitly defined, emit a implicit_def
1842 // before so scavenger knows it's "defined".
1843 // FIXME: This is a horrible hack done the by register allocator to
1844 // remat a definition with virtual register operand.
1845 VirtUseOps.insert(VirtUseOps.begin(), i);
1847 VirtUseOps.push_back(i);
1850 // Process all of the spilled uses and all non spilled reg references.
1851 SmallVector<int, 2> PotentialDeadStoreSlots;
1852 KilledMIRegs.clear();
1853 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
1854 unsigned i = VirtUseOps[j];
1855 unsigned VirtReg = MI.getOperand(i).getReg();
1856 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
1857 "Not a virtual register?");
1859 unsigned SubIdx = MI.getOperand(i).getSubReg();
1860 if (VRM.isAssignedReg(VirtReg)) {
1861 // This virtual register was assigned a physreg!
1862 unsigned Phys = VRM.getPhys(VirtReg);
1863 RegInfo->setPhysRegUsed(Phys);
1864 if (MI.getOperand(i).isDef())
1865 ReusedOperands.markClobbered(Phys);
1866 substitutePhysReg(MI.getOperand(i), Phys, *TRI);
1867 if (VRM.isImplicitlyDefined(VirtReg))
1868 // FIXME: Is this needed?
1869 BuildMI(MBB, &MI, MI.getDebugLoc(),
1870 TII->get(TargetOpcode::IMPLICIT_DEF), Phys);
1874 // This virtual register is now known to be a spilled value.
1875 if (!MI.getOperand(i).isUse())
1876 continue; // Handle defs in the loop below (handle use&def here though)
1878 bool AvoidReload = MI.getOperand(i).isUndef();
1879 // Check if it is defined by an implicit def. It should not be spilled.
1880 // Note, this is for correctness reason. e.g.
1881 // 8 %reg1024<def> = IMPLICIT_DEF
1882 // 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
1883 // The live range [12, 14) are not part of the r1024 live interval since
1884 // it's defined by an implicit def. It will not conflicts with live
1885 // interval of r1025. Now suppose both registers are spilled, you can
1886 // easily see a situation where both registers are reloaded before
1887 // the INSERT_SUBREG and both target registers that would overlap.
1888 bool DoReMat = VRM.isReMaterialized(VirtReg);
1889 int SSorRMId = DoReMat
1890 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1891 int ReuseSlot = SSorRMId;
1893 // Check to see if this stack slot is available.
1894 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1896 // If this is a sub-register use, make sure the reuse register is in the
1897 // right register class. For example, for x86 not all of the 32-bit
1898 // registers have accessible sub-registers.
1899 // Similarly so for EXTRACT_SUBREG. Consider this:
1901 // MOV32_mr fi#1, EDI
1903 // = EXTRACT_SUBREG fi#1
1904 // fi#1 is available in EDI, but it cannot be reused because it's not in
1905 // the right register file.
1906 if (PhysReg && !AvoidReload && (SubIdx || MI.isExtractSubreg())) {
1907 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1908 if (!RC->contains(PhysReg))
1912 if (PhysReg && !AvoidReload) {
1913 // This spilled operand might be part of a two-address operand. If this
1914 // is the case, then changing it will necessarily require changing the
1915 // def part of the instruction as well. However, in some cases, we
1916 // aren't allowed to modify the reused register. If none of these cases
1918 bool CanReuse = true;
1919 bool isTied = MI.isRegTiedToDefOperand(i);
1921 // Okay, we have a two address operand. We can reuse this physreg as
1922 // long as we are allowed to clobber the value and there isn't an
1923 // earlier def that has already clobbered the physreg.
1924 CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
1925 Spills.canClobberPhysReg(PhysReg);
1929 // If this stack slot value is already available, reuse it!
1930 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1931 DEBUG(dbgs() << "Reusing RM#"
1932 << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
1934 DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
1935 DEBUG(dbgs() << " from physreg "
1936 << TRI->getName(PhysReg) << " for vreg"
1937 << VirtReg <<" instead of reloading into physreg "
1938 << TRI->getName(VRM.getPhys(VirtReg)) << '\n');
1939 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1940 MI.getOperand(i).setReg(RReg);
1941 MI.getOperand(i).setSubReg(0);
1943 // The only technical detail we have is that we don't know that
1944 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1945 // later in the instruction. In particular, consider 'op V1, V2'.
1946 // If V1 is available in physreg R0, we would choose to reuse it
1947 // here, instead of reloading it into the register the allocator
1948 // indicated (say R1). However, V2 might have to be reloaded
1949 // later, and it might indicate that it needs to live in R0. When
1950 // this occurs, we need to have information available that
1951 // indicates it is safe to use R1 for the reload instead of R0.
1953 // To further complicate matters, we might conflict with an alias,
1954 // or R0 and R1 might not be compatible with each other. In this
1955 // case, we actually insert a reload for V1 in R1, ensuring that
1956 // we can get at R0 or its alias.
1957 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
1958 VRM.getPhys(VirtReg), VirtReg);
1960 // Only mark it clobbered if this is a use&def operand.
1961 ReusedOperands.markClobbered(PhysReg);
1964 if (MI.getOperand(i).isKill() &&
1965 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1967 // The store of this spilled value is potentially dead, but we
1968 // won't know for certain until we've confirmed that the re-use
1969 // above is valid, which means waiting until the other operands
1970 // are processed. For now we just track the spill slot, we'll
1971 // remove it after the other operands are processed if valid.
1973 PotentialDeadStoreSlots.push_back(ReuseSlot);
1976 // Mark is isKill if it's there no other uses of the same virtual
1977 // register and it's not a two-address operand. IsKill will be
1978 // unset if reg is reused.
1979 if (!isTied && KilledMIRegs.count(VirtReg) == 0) {
1980 MI.getOperand(i).setIsKill();
1981 KilledMIRegs.insert(VirtReg);
1987 // Otherwise we have a situation where we have a two-address instruction
1988 // whose mod/ref operand needs to be reloaded. This reload is already
1989 // available in some register "PhysReg", but if we used PhysReg as the
1990 // operand to our 2-addr instruction, the instruction would modify
1991 // PhysReg. This isn't cool if something later uses PhysReg and expects
1992 // to get its initial value.
1994 // To avoid this problem, and to avoid doing a load right after a store,
1995 // we emit a copy from PhysReg into the designated register for this
1997 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1998 assert(DesignatedReg && "Must map virtreg to physreg!");
2000 // Note that, if we reused a register for a previous operand, the
2001 // register we want to reload into might not actually be
2002 // available. If this occurs, use the register indicated by the
2004 if (ReusedOperands.hasReuses())
2005 DesignatedReg = ReusedOperands.GetRegForReload(VirtReg,
2007 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
2009 // If the mapped designated register is actually the physreg we have
2010 // incoming, we don't need to inserted a dead copy.
2011 if (DesignatedReg == PhysReg) {
2012 // If this stack slot value is already available, reuse it!
2013 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
2014 DEBUG(dbgs() << "Reusing RM#"
2015 << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
2017 DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
2018 DEBUG(dbgs() << " from physreg " << TRI->getName(PhysReg)
2019 << " for vreg" << VirtReg
2020 << " instead of reloading into same physreg.\n");
2021 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
2022 MI.getOperand(i).setReg(RReg);
2023 MI.getOperand(i).setSubReg(0);
2024 ReusedOperands.markClobbered(RReg);
2029 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
2030 RegInfo->setPhysRegUsed(DesignatedReg);
2031 ReusedOperands.markClobbered(DesignatedReg);
2033 // Back-schedule reloads and remats.
2034 MachineBasicBlock::iterator InsertLoc =
2035 ComputeReloadLoc(&MI, MBB.begin(), PhysReg, TRI, DoReMat,
2038 TII->copyRegToReg(MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC);
2040 MachineInstr *CopyMI = prior(InsertLoc);
2041 CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
2042 UpdateKills(*CopyMI, TRI, RegKills, KillOps);
2044 // This invalidates DesignatedReg.
2045 Spills.ClobberPhysReg(DesignatedReg);
2047 Spills.addAvailable(ReuseSlot, DesignatedReg);
2049 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
2050 MI.getOperand(i).setReg(RReg);
2051 MI.getOperand(i).setSubReg(0);
2052 DEBUG(dbgs() << '\t' << *prior(MII));
2057 // Otherwise, reload it and remember that we have it.
2058 PhysReg = VRM.getPhys(VirtReg);
2059 assert(PhysReg && "Must map virtreg to physreg!");
2061 // Note that, if we reused a register for a previous operand, the
2062 // register we want to reload into might not actually be
2063 // available. If this occurs, use the register indicated by the
2065 if (ReusedOperands.hasReuses())
2066 PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
2067 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
2069 RegInfo->setPhysRegUsed(PhysReg);
2070 ReusedOperands.markClobbered(PhysReg);
2074 // Back-schedule reloads and remats.
2075 MachineBasicBlock::iterator InsertLoc =
2076 ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, DoReMat,
2080 ReMaterialize(MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, VRM);
2082 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
2083 TII->loadRegFromStackSlot(MBB, InsertLoc, PhysReg, SSorRMId, RC);
2084 MachineInstr *LoadMI = prior(InsertLoc);
2085 VRM.addSpillSlotUse(SSorRMId, LoadMI);
2087 DistanceMap.insert(std::make_pair(LoadMI, Dist++));
2089 // This invalidates PhysReg.
2090 Spills.ClobberPhysReg(PhysReg);
2092 // Any stores to this stack slot are not dead anymore.
2094 MaybeDeadStores[SSorRMId] = NULL;
2095 Spills.addAvailable(SSorRMId, PhysReg);
2096 // Assumes this is the last use. IsKill will be unset if reg is reused
2097 // unless it's a two-address operand.
2098 if (!MI.isRegTiedToDefOperand(i) &&
2099 KilledMIRegs.count(VirtReg) == 0) {
2100 MI.getOperand(i).setIsKill();
2101 KilledMIRegs.insert(VirtReg);
2104 UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
2105 DEBUG(dbgs() << '\t' << *prior(InsertLoc));
2107 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
2108 MI.getOperand(i).setReg(RReg);
2109 MI.getOperand(i).setSubReg(0);
2112 // Ok - now we can remove stores that have been confirmed dead.
2113 for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
2114 // This was the last use and the spilled value is still available
2115 // for reuse. That means the spill was unnecessary!
2116 int PDSSlot = PotentialDeadStoreSlots[j];
2117 MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
2119 DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
2120 InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
2121 VRM.RemoveMachineInstrFromMaps(DeadStore);
2122 MBB.erase(DeadStore);
2123 MaybeDeadStores[PDSSlot] = NULL;
2129 DEBUG(dbgs() << '\t' << MI);
2132 // If we have folded references to memory operands, make sure we clear all
2133 // physical registers that may contain the value of the spilled virtual
2135 SmallSet<int, 2> FoldedSS;
2136 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
2137 unsigned VirtReg = I->second.first;
2138 VirtRegMap::ModRef MR = I->second.second;
2139 DEBUG(dbgs() << "Folded vreg: " << VirtReg << " MR: " << MR);
2141 // MI2VirtMap be can updated which invalidate the iterator.
2142 // Increment the iterator first.
2144 int SS = VRM.getStackSlot(VirtReg);
2145 if (SS == VirtRegMap::NO_STACK_SLOT)
2147 FoldedSS.insert(SS);
2148 DEBUG(dbgs() << " - StackSlot: " << SS << "\n");
2150 // If this folded instruction is just a use, check to see if it's a
2151 // straight load from the virt reg slot.
2152 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
2154 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
2155 if (DestReg && FrameIdx == SS) {
2156 // If this spill slot is available, turn it into a copy (or nothing)
2157 // instead of leaving it as a load!
2158 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
2159 DEBUG(dbgs() << "Promoted Load To Copy: " << MI);
2160 if (DestReg != InReg) {
2161 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
2162 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
2163 MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
2164 unsigned SubIdx = DefMO->getSubReg();
2165 // Revisit the copy so we make sure to notice the effects of the
2166 // operation on the destreg (either needing to RA it if it's
2167 // virtual or needing to clobber any values if it's physical).
2169 --NextMII; // backtrack to the copy.
2170 NextMII->setAsmPrinterFlag(MachineInstr::ReloadReuse);
2171 // Propagate the sub-register index over.
2173 DefMO = NextMII->findRegisterDefOperand(DestReg);
2174 DefMO->setSubReg(SubIdx);
2178 MachineOperand *KillOpnd = NextMII->findRegisterUseOperand(InReg);
2179 KillOpnd->setIsKill();
2183 DEBUG(dbgs() << "Removing now-noop copy: " << MI);
2184 // Unset last kill since it's being reused.
2185 InvalidateKill(InReg, TRI, RegKills, KillOps);
2186 Spills.disallowClobberPhysReg(InReg);
2189 InvalidateKills(MI, TRI, RegKills, KillOps);
2190 VRM.RemoveMachineInstrFromMaps(&MI);
2193 goto ProcessNextInst;
2196 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
2197 SmallVector<MachineInstr*, 4> NewMIs;
2199 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
2200 MBB.insert(MII, NewMIs[0]);
2201 InvalidateKills(MI, TRI, RegKills, KillOps);
2202 VRM.RemoveMachineInstrFromMaps(&MI);
2205 --NextMII; // backtrack to the unfolded instruction.
2207 goto ProcessNextInst;
2212 // If this reference is not a use, any previous store is now dead.
2213 // Otherwise, the store to this stack slot is not dead anymore.
2214 MachineInstr* DeadStore = MaybeDeadStores[SS];
2216 bool isDead = !(MR & VirtRegMap::isRef);
2217 MachineInstr *NewStore = NULL;
2218 if (MR & VirtRegMap::isModRef) {
2219 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
2220 SmallVector<MachineInstr*, 4> NewMIs;
2221 // We can reuse this physreg as long as we are allowed to clobber
2222 // the value and there isn't an earlier def that has already clobbered
2225 !ReusedOperands.isClobbered(PhysReg) &&
2226 Spills.canClobberPhysReg(PhysReg) &&
2227 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
2228 MachineOperand *KillOpnd =
2229 DeadStore->findRegisterUseOperand(PhysReg, true);
2230 // Note, if the store is storing a sub-register, it's possible the
2231 // super-register is needed below.
2232 if (KillOpnd && !KillOpnd->getSubReg() &&
2233 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
2234 MBB.insert(MII, NewMIs[0]);
2235 NewStore = NewMIs[1];
2236 MBB.insert(MII, NewStore);
2237 VRM.addSpillSlotUse(SS, NewStore);
2238 InvalidateKills(MI, TRI, RegKills, KillOps);
2239 VRM.RemoveMachineInstrFromMaps(&MI);
2243 --NextMII; // backtrack to the unfolded instruction.
2251 if (isDead) { // Previous store is dead.
2252 // If we get here, the store is dead, nuke it now.
2253 DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
2254 InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
2255 VRM.RemoveMachineInstrFromMaps(DeadStore);
2256 MBB.erase(DeadStore);
2261 MaybeDeadStores[SS] = NULL;
2263 // Treat this store as a spill merged into a copy. That makes the
2264 // stack slot value available.
2265 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
2266 goto ProcessNextInst;
2270 // If the spill slot value is available, and this is a new definition of
2271 // the value, the value is not available anymore.
2272 if (MR & VirtRegMap::isMod) {
2273 // Notice that the value in this stack slot has been modified.
2274 Spills.ModifyStackSlotOrReMat(SS);
2276 // If this is *just* a mod of the value, check to see if this is just a
2277 // store to the spill slot (i.e. the spill got merged into the copy). If
2278 // so, realize that the vreg is available now, and add the store to the
2279 // MaybeDeadStore info.
2281 if (!(MR & VirtRegMap::isRef)) {
2282 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
2283 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
2284 "Src hasn't been allocated yet?");
2286 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot,
2287 Spills, RegKills, KillOps, TRI, VRM)) {
2288 NextMII = llvm::next(MII);
2290 goto ProcessNextInst;
2293 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
2294 // this as a potentially dead store in case there is a subsequent
2295 // store into the stack slot without a read from it.
2296 MaybeDeadStores[StackSlot] = &MI;
2298 // If the stack slot value was previously available in some other
2299 // register, change it now. Otherwise, make the register
2300 // available in PhysReg.
2301 Spills.addAvailable(StackSlot, SrcReg, MI.killsRegister(SrcReg));
2307 // Process all of the spilled defs.
2308 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2309 MachineOperand &MO = MI.getOperand(i);
2310 if (!(MO.isReg() && MO.getReg() && MO.isDef()))
2313 unsigned VirtReg = MO.getReg();
2314 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
2315 // Check to see if this is a noop copy. If so, eliminate the
2316 // instruction before considering the dest reg to be changed.
2317 // Also check if it's copying from an "undef", if so, we can't
2318 // eliminate this or else the undef marker is lost and it will
2319 // confuses the scavenger. This is extremely rare.
2320 unsigned Src, Dst, SrcSR, DstSR;
2321 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst &&
2322 !MI.findRegisterUseOperand(Src)->isUndef()) {
2324 DEBUG(dbgs() << "Removing now-noop copy: " << MI);
2325 SmallVector<unsigned, 2> KillRegs;
2326 InvalidateKills(MI, TRI, RegKills, KillOps, &KillRegs);
2327 if (MO.isDead() && !KillRegs.empty()) {
2328 // Source register or an implicit super/sub-register use is killed.
2329 assert(KillRegs[0] == Dst ||
2330 TRI->isSubRegister(KillRegs[0], Dst) ||
2331 TRI->isSuperRegister(KillRegs[0], Dst));
2332 // Last def is now dead.
2333 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps, VRM);
2335 VRM.RemoveMachineInstrFromMaps(&MI);
2338 Spills.disallowClobberPhysReg(VirtReg);
2339 goto ProcessNextInst;
2342 // If it's not a no-op copy, it clobbers the value in the destreg.
2343 Spills.ClobberPhysReg(VirtReg);
2344 ReusedOperands.markClobbered(VirtReg);
2346 // Check to see if this instruction is a load from a stack slot into
2347 // a register. If so, this provides the stack slot value in the reg.
2349 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
2350 assert(DestReg == VirtReg && "Unknown load situation!");
2352 // If it is a folded reference, then it's not safe to clobber.
2353 bool Folded = FoldedSS.count(FrameIdx);
2354 // Otherwise, if it wasn't available, remember that it is now!
2355 Spills.addAvailable(FrameIdx, DestReg, !Folded);
2356 goto ProcessNextInst;
2362 unsigned SubIdx = MO.getSubReg();
2363 bool DoReMat = VRM.isReMaterialized(VirtReg);
2365 ReMatDefs.insert(&MI);
2367 // The only vregs left are stack slot definitions.
2368 int StackSlot = VRM.getStackSlot(VirtReg);
2369 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
2371 // If this def is part of a two-address operand, make sure to execute
2372 // the store from the correct physical register.
2375 if (MI.isRegTiedToUseOperand(i, &TiedOp)) {
2376 PhysReg = MI.getOperand(TiedOp).getReg();
2378 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
2379 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
2380 "Can't find corresponding super-register!");
2384 PhysReg = VRM.getPhys(VirtReg);
2385 if (ReusedOperands.isClobbered(PhysReg)) {
2386 // Another def has taken the assigned physreg. It must have been a
2387 // use&def which got it due to reuse. Undo the reuse!
2388 PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
2389 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
2393 assert(PhysReg && "VR not assigned a physical register?");
2394 RegInfo->setPhysRegUsed(PhysReg);
2395 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
2396 ReusedOperands.markClobbered(RReg);
2397 MI.getOperand(i).setReg(RReg);
2398 MI.getOperand(i).setSubReg(0);
2401 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
2402 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
2403 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
2404 NextMII = llvm::next(MII);
2406 // Check to see if this is a noop copy. If so, eliminate the
2407 // instruction before considering the dest reg to be changed.
2409 unsigned Src, Dst, SrcSR, DstSR;
2410 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) {
2412 DEBUG(dbgs() << "Removing now-noop copy: " << MI);
2413 InvalidateKills(MI, TRI, RegKills, KillOps);
2414 VRM.RemoveMachineInstrFromMaps(&MI);
2417 UpdateKills(*LastStore, TRI, RegKills, KillOps);
2418 goto ProcessNextInst;
2424 // Delete dead instructions without side effects.
2425 if (!Erased && !BackTracked && isSafeToDelete(MI)) {
2426 InvalidateKills(MI, TRI, RegKills, KillOps);
2427 VRM.RemoveMachineInstrFromMaps(&MI);
2432 DistanceMap.insert(std::make_pair(&MI, Dist++));
2433 if (!Erased && !BackTracked) {
2434 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
2435 UpdateKills(*II, TRI, RegKills, KillOps);
2446 llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
2447 switch (RewriterOpt) {
2448 default: llvm_unreachable("Unreachable!");
2450 return new LocalRewriter();
2452 return new TrivialRewriter();