1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "Disassembler.h"
11 #include "llvm-c/Disassembler.h"
12 #include "llvm/MC/MCAsmInfo.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDisassembler.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstPrinter.h"
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCRelocationInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbolizer.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/TargetRegistry.h"
29 // LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
30 // disassembly is supported by passing a block of information in the DisInfo
31 // parameter and specifying the TagType and callback functions as described in
32 // the header llvm-c/Disassembler.h . The pointer to the block and the
33 // functions can all be passed as NULL. If successful, this returns a
34 // disassembler context. If not, it returns NULL.
36 LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU,
37 void *DisInfo, int TagType,
38 LLVMOpInfoCallback GetOpInfo,
39 LLVMSymbolLookupCallback SymbolLookUp){
42 const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error);
46 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
50 // Get the assembler info needed to setup the MCContext.
51 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple);
55 const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
59 // Package up features to be passed to target/subtarget
60 std::string FeaturesStr;
62 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU,
67 // Set up the MCContext for creating symbols and MCExpr's.
68 MCContext *Ctx = new MCContext(MAI, MRI, 0);
72 // Set up disassembler.
73 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
77 std::unique_ptr<MCRelocationInfo> RelInfo(
78 TheTarget->createMCRelocationInfo(Triple, *Ctx));
82 std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
83 Triple, GetOpInfo, SymbolLookUp, DisInfo, Ctx, RelInfo.release()));
84 DisAsm->setSymbolizer(std::move(Symbolizer));
85 DisAsm->setupForSymbolicDisassembly(GetOpInfo, SymbolLookUp, DisInfo,
87 // Set up the instruction printer.
88 int AsmPrinterVariant = MAI->getAssemblerDialect();
89 MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant,
90 *MAI, *MII, *MRI, *STI);
94 LLVMDisasmContext *DC = new LLVMDisasmContext(Triple, DisInfo, TagType,
95 GetOpInfo, SymbolLookUp,
97 STI, MII, Ctx, DisAsm, IP);
105 LLVMDisasmContextRef LLVMCreateDisasm(const char *Triple, void *DisInfo,
106 int TagType, LLVMOpInfoCallback GetOpInfo,
107 LLVMSymbolLookupCallback SymbolLookUp) {
108 return LLVMCreateDisasmCPU(Triple, "", DisInfo, TagType, GetOpInfo,
113 // LLVMDisasmDispose() disposes of the disassembler specified by the context.
115 void LLVMDisasmDispose(LLVMDisasmContextRef DCR){
116 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
122 // The memory object created by LLVMDisasmInstruction().
124 class DisasmMemoryObject : public MemoryObject {
129 DisasmMemoryObject(uint8_t *bytes, uint64_t size, uint64_t basePC) :
130 Bytes(bytes), Size(size), BasePC(basePC) {}
132 uint64_t getBase() const override { return BasePC; }
133 uint64_t getExtent() const override { return Size; }
135 int readByte(uint64_t Addr, uint8_t *Byte) const override {
136 if (Addr - BasePC >= Size)
138 *Byte = Bytes[Addr - BasePC];
142 } // end anonymous namespace
144 /// \brief Emits the comments that are stored in \p DC comment stream.
145 /// Each comment in the comment stream must end with a newline.
146 static void emitComments(LLVMDisasmContext *DC,
147 formatted_raw_ostream &FormattedOS) {
148 // Flush the stream before taking its content.
149 DC->CommentStream.flush();
150 StringRef Comments = DC->CommentsToEmit.str();
151 // Get the default information for printing a comment.
152 const MCAsmInfo *MAI = DC->getAsmInfo();
153 const char *CommentBegin = MAI->getCommentString();
154 unsigned CommentColumn = MAI->getCommentColumn();
156 while (!Comments.empty()) {
159 // Emit a line of comments.
160 FormattedOS.PadToColumn(CommentColumn);
161 size_t Position = Comments.find('\n');
162 FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
163 // Move after the newline character.
164 Comments = Comments.substr(Position+1);
169 // Tell the comment stream that the vector changed underneath it.
170 DC->CommentsToEmit.clear();
171 DC->CommentStream.resync();
174 /// \brief Gets latency information for \p Inst form the itinerary
175 /// scheduling model, based on \p DC information.
176 /// \return The maximum expected latency over all the operands or -1
177 /// if no information are available.
178 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
179 const int NoInformationAvailable = -1;
181 // Check if we have a CPU to get the itinerary information.
182 if (DC->getCPU().empty())
183 return NoInformationAvailable;
185 // Get itinerary information.
186 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
187 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
188 // Get the scheduling class of the requested instruction.
189 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
190 unsigned SCClass = Desc.getSchedClass();
193 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
195 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
200 /// \brief Gets latency information for \p Inst, based on \p DC information.
201 /// \return The maximum expected latency over all the definitions or -1
202 /// if no information are available.
203 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
204 // Try to compute scheduling information.
205 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
206 const MCSchedModel *SCModel = STI->getSchedModel();
207 const int NoInformationAvailable = -1;
209 // Check if we have a scheduling model for instructions.
210 if (!SCModel || !SCModel->hasInstrSchedModel())
211 // Try to fall back to the itinerary model if we do not have a
213 return getItineraryLatency(DC, Inst);
215 // Get the scheduling class of the requested instruction.
216 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
217 unsigned SCClass = Desc.getSchedClass();
218 const MCSchedClassDesc *SCDesc = SCModel->getSchedClassDesc(SCClass);
219 // Resolving the variant SchedClass requires an MI to pass to
220 // SubTargetInfo::resolveSchedClass.
221 if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
222 return NoInformationAvailable;
224 // Compute output latency.
226 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
227 DefIdx != DefEnd; ++DefIdx) {
228 // Lookup the definition's write latency in SubtargetInfo.
229 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
231 Latency = std::max(Latency, WLEntry->Cycles);
238 /// \brief Emits latency information in DC->CommentStream for \p Inst, based
239 /// on the information available in \p DC.
240 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
241 int Latency = getLatency(DC, Inst);
243 // Report only interesting latency.
247 DC->CommentStream << "Latency: " << Latency << '\n';
251 // LLVMDisasmInstruction() disassembles a single instruction using the
252 // disassembler context specified in the parameter DC. The bytes of the
253 // instruction are specified in the parameter Bytes, and contains at least
254 // BytesSize number of bytes. The instruction is at the address specified by
255 // the PC parameter. If a valid instruction can be disassembled its string is
256 // returned indirectly in OutString which whos size is specified in the
257 // parameter OutStringSize. This function returns the number of bytes in the
258 // instruction or zero if there was no valid instruction. If this function
259 // returns zero the caller will have to pick how many bytes they want to step
260 // over by printing a .byte, .long etc. to continue.
262 size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
263 uint64_t BytesSize, uint64_t PC, char *OutString,
264 size_t OutStringSize){
265 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
266 // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
267 DisasmMemoryObject MemoryObject(Bytes, BytesSize, PC);
271 const MCDisassembler *DisAsm = DC->getDisAsm();
272 MCInstPrinter *IP = DC->getIP();
273 MCDisassembler::DecodeStatus S;
274 SmallVector<char, 64> InsnStr;
275 raw_svector_ostream Annotations(InsnStr);
276 S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC,
277 /*REMOVE*/ nulls(), Annotations);
279 case MCDisassembler::Fail:
280 case MCDisassembler::SoftFail:
281 // FIXME: Do something different for soft failure modes?
284 case MCDisassembler::Success: {
286 StringRef AnnotationsStr = Annotations.str();
288 SmallVector<char, 64> InsnStr;
289 raw_svector_ostream OS(InsnStr);
290 formatted_raw_ostream FormattedOS(OS);
291 IP->printInst(&Inst, FormattedOS, AnnotationsStr);
293 if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
294 emitLatency(DC, Inst);
296 emitComments(DC, FormattedOS);
299 assert(OutStringSize != 0 && "Output buffer cannot be zero size");
300 size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
301 std::memcpy(OutString, InsnStr.data(), OutputSize);
302 OutString[OutputSize] = '\0'; // Terminate string.
307 llvm_unreachable("Invalid DecodeStatus!");
311 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
312 // can set all the Options and 0 otherwise.
314 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
315 if (Options & LLVMDisassembler_Option_UseMarkup){
316 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
317 MCInstPrinter *IP = DC->getIP();
319 DC->addOptions(LLVMDisassembler_Option_UseMarkup);
320 Options &= ~LLVMDisassembler_Option_UseMarkup;
322 if (Options & LLVMDisassembler_Option_PrintImmHex){
323 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
324 MCInstPrinter *IP = DC->getIP();
325 IP->setPrintImmHex(1);
326 DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
327 Options &= ~LLVMDisassembler_Option_PrintImmHex;
329 if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
330 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
331 // Try to set up the new instruction printer.
332 const MCAsmInfo *MAI = DC->getAsmInfo();
333 const MCInstrInfo *MII = DC->getInstrInfo();
334 const MCRegisterInfo *MRI = DC->getRegisterInfo();
335 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
336 int AsmPrinterVariant = MAI->getAssemblerDialect();
337 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
338 MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
339 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
342 DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
343 Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
346 if (Options & LLVMDisassembler_Option_SetInstrComments) {
347 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
348 MCInstPrinter *IP = DC->getIP();
349 IP->setCommentStream(DC->CommentStream);
350 DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
351 Options &= ~LLVMDisassembler_Option_SetInstrComments;
353 if (Options & LLVMDisassembler_Option_PrintLatency) {
354 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
355 DC->addOptions(LLVMDisassembler_Option_PrintLatency);
356 Options &= ~LLVMDisassembler_Option_PrintLatency;
358 return (Options == 0);