1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCSubtargetInfo.h"
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/ADT/Triple.h"
13 #include "llvm/MC/MCInstrItineraries.h"
14 #include "llvm/MC/SubtargetFeature.h"
15 #include "llvm/Support/raw_ostream.h"
20 static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
21 ArrayRef<SubtargetFeatureKV> ProcDesc,
22 ArrayRef<SubtargetFeatureKV> ProcFeatures) {
23 SubtargetFeatures Features(FS);
24 return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
27 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
28 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
30 CPUSchedModel = &getSchedModelForCPU(CPU);
32 CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
35 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
36 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
39 MCSubtargetInfo::MCSubtargetInfo(
40 const Triple &TT, StringRef C, StringRef FS,
41 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
42 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
43 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
44 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
45 : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
46 ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
47 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
48 InitMCProcessorInfo(CPU, FS);
51 /// ToggleFeature - Toggle a feature and returns the re-computed feature
52 /// bits. This version does not change the implied bits.
53 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
58 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
63 /// ToggleFeature - Toggle a feature and returns the re-computed feature
64 /// bits. This version will also change all implied bits.
65 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
66 SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
70 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
71 SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
75 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
76 assert(ProcSchedModels && "Processor machine model not available!");
78 ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
80 assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
81 [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
82 return strcmp(LHS.Key, RHS.Key) < 0;
84 "Processor machine model table is not sorted");
88 std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
89 if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
90 if (CPU != "help") // Don't error if the user asked for help.
92 << "' is not a recognized processor for this target"
93 << " (ignoring processor)\n";
94 return MCSchedModel::GetDefaultSchedModel();
96 assert(Found->Value && "Missing processor SchedModel value");
97 return *(const MCSchedModel *)Found->Value;
101 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
102 const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
103 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
106 /// Initialize an InstrItineraryData instance.
107 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
108 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,