1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCSubtargetInfo.h"
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/ADT/Triple.h"
13 #include "llvm/MC/MCInstrItineraries.h"
14 #include "llvm/MC/SubtargetFeature.h"
15 #include "llvm/Support/raw_ostream.h"
20 MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
22 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
23 /// with feature string). Recompute feature bits and scheduling model.
25 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
26 SubtargetFeatures Features(FS);
27 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
28 ProcFeatures, NumFeatures);
30 InitCPUSchedModel(CPU);
34 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
36 CPUSchedModel = getSchedModelForCPU(CPU);
38 CPUSchedModel = &MCSchedModel::DefaultSchedModel;
42 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
43 const SubtargetFeatureKV *PF,
44 const SubtargetFeatureKV *PD,
45 const SubtargetInfoKV *ProcSched,
46 const MCWriteProcResEntry *WPR,
47 const MCWriteLatencyEntry *WL,
48 const MCReadAdvanceEntry *RA,
52 unsigned NF, unsigned NP) {
56 ProcSchedModels = ProcSched;
57 WriteProcResTable = WPR;
58 WriteLatencyTable = WL;
59 ReadAdvanceTable = RA;
67 InitMCProcessorInfo(CPU, FS);
70 /// ToggleFeature - Toggle a feature and returns the re-computed feature
71 /// bits. This version does not change the implied bits.
72 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
77 /// ToggleFeature - Toggle a feature and returns the re-computed feature
78 /// bits. This version will also change all implied bits.
79 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
80 SubtargetFeatures Features;
81 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
82 ProcFeatures, NumFeatures);
88 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
89 assert(ProcSchedModels && "Processor machine model not available!");
92 for (size_t i = 1; i < NumProcs; i++) {
93 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
94 "Processor machine model table is not sorted");
101 const SubtargetInfoKV *Found =
102 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, KV);
103 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
105 << "' is not a recognized processor for this target"
106 << " (ignoring processor)\n";
107 return &MCSchedModel::DefaultSchedModel;
109 assert(Found->Value && "Missing processor SchedModel value");
110 return (const MCSchedModel *)Found->Value;
114 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
115 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
116 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
119 /// Initialize an InstrItineraryData instance.
120 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
122 InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);