1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCSubtargetInfo.h"
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/ADT/Triple.h"
13 #include "llvm/MC/MCInstrItineraries.h"
14 #include "llvm/MC/SubtargetFeature.h"
15 #include "llvm/Support/raw_ostream.h"
20 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
21 /// with feature string). Recompute feature bits and scheduling model.
23 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
24 SubtargetFeatures Features(FS);
25 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
26 InitCPUSchedModel(CPU);
30 MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
32 CPUSchedModel = getSchedModelForCPU(CPU);
34 CPUSchedModel = MCSchedModel::GetDefaultSchedModel();
37 void MCSubtargetInfo::InitMCSubtargetInfo(
38 const Triple &TT, StringRef C, StringRef FS,
39 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
40 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
41 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
42 const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
47 ProcSchedModels = ProcSched;
48 WriteProcResTable = WPR;
49 WriteLatencyTable = WL;
50 ReadAdvanceTable = RA;
56 InitMCProcessorInfo(CPU, FS);
59 /// ToggleFeature - Toggle a feature and returns the re-computed feature
60 /// bits. This version does not change the implied bits.
61 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
66 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
71 /// ToggleFeature - Toggle a feature and returns the re-computed feature
72 /// bits. This version will also change all implied bits.
73 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
74 SubtargetFeatures Features;
75 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
79 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
80 SubtargetFeatures Features;
81 FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
86 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
87 assert(ProcSchedModels && "Processor machine model not available!");
89 unsigned NumProcs = ProcDesc.size();
91 for (size_t i = 1; i < NumProcs; i++) {
92 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
93 "Processor machine model table is not sorted");
98 const SubtargetInfoKV *Found =
99 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
100 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
101 if (CPU != "help") // Don't error if the user asked for help.
103 << "' is not a recognized processor for this target"
104 << " (ignoring processor)\n";
105 return MCSchedModel::GetDefaultSchedModel();
107 assert(Found->Value && "Missing processor SchedModel value");
108 return *(const MCSchedModel *)Found->Value;
112 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
113 const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
114 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
117 /// Initialize an InstrItineraryData instance.
118 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
120 InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);