1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCSubtargetInfo.h"
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/ADT/Triple.h"
13 #include "llvm/MC/MCInstrItineraries.h"
14 #include "llvm/MC/SubtargetFeature.h"
15 #include "llvm/Support/raw_ostream.h"
20 MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
22 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
23 /// with feature string). Recompute feature bits and scheduling model.
25 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
26 SubtargetFeatures Features(FS);
27 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
28 ProcFeatures, NumFeatures);
31 CPUSchedModel = getSchedModelForCPU(CPU);
33 CPUSchedModel = &MCSchedModel::DefaultSchedModel;
37 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
38 const SubtargetFeatureKV *PF,
39 const SubtargetFeatureKV *PD,
40 const SubtargetInfoKV *ProcSched,
41 const MCWriteProcResEntry *WPR,
42 const MCWriteLatencyEntry *WL,
43 const MCReadAdvanceEntry *RA,
47 unsigned NF, unsigned NP) {
51 ProcSchedModels = ProcSched;
52 WriteProcResTable = WPR;
53 WriteLatencyTable = WL;
54 ReadAdvanceTable = RA;
62 InitMCProcessorInfo(CPU, FS);
65 /// ToggleFeature - Toggle a feature and returns the re-computed feature
66 /// bits. This version does not change the implied bits.
67 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
72 /// ToggleFeature - Toggle a feature and returns the re-computed feature
73 /// bits. This version will also change all implied bits.
74 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
75 SubtargetFeatures Features;
76 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
77 ProcFeatures, NumFeatures);
83 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
84 assert(ProcSchedModels && "Processor machine model not available!");
87 for (size_t i = 1; i < NumProcs; i++) {
88 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
89 "Processor machine model table is not sorted");
96 const SubtargetInfoKV *Found =
97 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, KV);
98 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
100 << "' is not a recognized processor for this target"
101 << " (ignoring processor)\n";
102 return &MCSchedModel::DefaultSchedModel;
104 assert(Found->Value && "Missing processor SchedModel value");
105 return (const MCSchedModel *)Found->Value;
109 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
110 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
111 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
114 /// Initialize an InstrItineraryData instance.
115 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
117 InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);