1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This header file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 //===----------------------------------------------------------------------===//
44 // Implementations of the CPU detection routines
46 //===----------------------------------------------------------------------===//
50 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
51 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
53 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
54 /// specified arguments. If we can't run cpuid on the host, return true.
55 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
56 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
57 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
59 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
60 asm ("movq\t%%rbx, %%rsi\n\t"
62 "xchgq\t%%rbx, %%rsi\n\t"
69 #elif defined(_MSC_VER)
71 __cpuid(registers, value);
80 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
82 asm ("movl\t%%ebx, %%esi\n\t"
84 "xchgl\t%%ebx, %%esi\n\t"
91 #elif defined(_MSC_VER)
96 mov dword ptr [esi],eax
98 mov dword ptr [esi],ebx
100 mov dword ptr [esi],ecx
102 mov dword ptr [esi],edx
105 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
106 // postprocessed code that looks like "return true; return false;")
115 static bool OSHasAVXSupport() {
116 #if defined(__GNUC__)
117 // Check xgetbv; this uses a .byte sequence instead of the instruction
118 // directly because older assemblers do not include support for xgetbv and
119 // there is no easy way to conditionally compile based on the assembler used.
121 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
122 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
123 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
125 int rEAX = 0; // Ensures we return false
127 return (rEAX & 6) == 6;
130 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
132 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
133 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
134 if (Family == 6 || Family == 0xf) {
136 // Examine extended family ID if family ID is F.
137 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
138 // Examine extended model ID if family ID is 6 or F.
139 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
143 std::string sys::getHostCPUName() {
144 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
145 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
149 DetectX86FamilyModel(EAX, Family, Model);
151 bool HasSSE3 = (ECX & 0x1);
152 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
153 // indicates that the AVX registers will be saved and restored on context
154 // switch, then we have full AVX support.
155 const unsigned AVXBits = (1 << 27) | (1 << 28);
156 bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
157 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
158 bool Em64T = (EDX >> 29) & 0x1;
165 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
166 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
172 case 0: // Intel486 DX processors
173 case 1: // Intel486 DX processors
174 case 2: // Intel486 SX processors
175 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
176 // IntelDX2 processors
177 case 4: // Intel486 SL processor
178 case 5: // IntelSX2 processors
179 case 7: // Write-Back Enhanced IntelDX2 processors
180 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
181 default: return "i486";
185 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
186 // Pentium processors (60, 66)
187 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
188 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
190 case 3: // Pentium OverDrive processors for Intel486 processor-based
194 case 4: // Pentium OverDrive processor with MMX technology for Pentium
195 // processor (75, 90, 100, 120, 133), Pentium processor with
196 // MMX technology (166, 200)
197 return "pentium-mmx";
199 default: return "pentium";
203 case 1: // Pentium Pro processor
206 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
208 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
209 // model 05, and Intel Celeron processor, model 05
210 case 6: // Celeron processor, model 06
213 case 7: // Pentium III processor, model 07, and Pentium III Xeon
214 // processor, model 07
215 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
216 // model 08, and Celeron processor, model 08
217 case 10: // Pentium III Xeon processor, model 0Ah
218 case 11: // Pentium III processor, model 0Bh
221 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
222 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
223 // 0Dh. All processors are manufactured using the 90 nm process.
226 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
227 // 0Eh. All processors are manufactured using the 65 nm process.
230 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
231 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
232 // mobile processor, Intel Core 2 Extreme processor, Intel
233 // Pentium Dual-Core processor, Intel Xeon processor, model
234 // 0Fh. All processors are manufactured using the 65 nm process.
235 case 22: // Intel Celeron processor model 16h. All processors are
236 // manufactured using the 65 nm process
239 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
240 // Integrated Processor with Intel QuickAssist Technology
241 return "i686"; // FIXME: ???
243 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
244 // 17h. All processors are manufactured using the 45 nm process.
246 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
249 case 26: // Intel Core i7 processor and Intel Xeon processor. All
250 // processors are manufactured using the 45 nm process.
251 case 29: // Intel Xeon processor MP. All processors are manufactured using
252 // the 45 nm process.
253 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
254 // As found in a Summer 2010 model iMac.
255 case 37: // Intel Core i7, laptop version.
256 case 44: // Intel Core i7 processor and Intel Xeon processor. All
257 // processors are manufactured using the 32 nm process.
258 case 46: // Nehalem EX
259 case 47: // Westmere EX
263 case 42: // Intel Core i7 processor. All processors are manufactured
264 // using the 32 nm process.
266 // Not all Sandy Bridge processors support AVX (such as the Pentium
267 // versions instead of the i7 versions).
268 return HasAVX ? "corei7-avx" : "corei7";
272 // Not all Ivy Bridge processors support AVX (such as the Pentium
273 // versions instead of the i7 versions).
274 return HasAVX ? "core-avx-i" : "corei7";
276 case 28: // Most 45 nm Intel Atom processors
277 case 38: // 45 nm Atom Lincroft
278 case 39: // 32 nm Atom Medfield
279 case 53: // 32 nm Atom Midview
280 case 54: // 32 nm Atom Midview
283 default: return (Em64T) ? "x86-64" : "i686";
287 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
288 // model 00h and manufactured using the 0.18 micron process.
289 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
290 // processor MP, and Intel Celeron processor. All processors are
291 // model 01h and manufactured using the 0.18 micron process.
292 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
293 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
294 // processor, and Mobile Intel Celeron processor. All processors
295 // are model 02h and manufactured using the 0.13 micron process.
296 return (Em64T) ? "x86-64" : "pentium4";
298 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
299 // processor. All processors are model 03h and manufactured using
300 // the 90 nm process.
301 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
302 // Pentium D processor, Intel Xeon processor, Intel Xeon
303 // processor MP, Intel Celeron D processor. All processors are
304 // model 04h and manufactured using the 90 nm process.
305 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
306 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
307 // MP, Intel Celeron D processor. All processors are model 06h
308 // and manufactured using the 65 nm process.
309 return (Em64T) ? "nocona" : "prescott";
312 return (Em64T) ? "x86-64" : "pentium4";
319 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
320 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
321 // appears to be no way to generate the wide variety of AMD-specific targets
322 // from the information returned from CPUID.
330 case 8: return "k6-2";
332 case 13: return "k6-3";
333 case 10: return "geode";
334 default: return "pentium";
338 case 4: return "athlon-tbird";
341 case 8: return "athlon-mp";
342 case 10: return "athlon-xp";
343 default: return "athlon";
349 case 1: return "opteron";
350 case 5: return "athlon-fx"; // also opteron
351 default: return "athlon64";
360 else if (Model <= 31)
368 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
369 std::string sys::getHostCPUName() {
370 host_basic_info_data_t hostInfo;
371 mach_msg_type_number_t infoCount;
373 infoCount = HOST_BASIC_INFO_COUNT;
374 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
377 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
379 switch(hostInfo.cpu_subtype) {
380 case CPU_SUBTYPE_POWERPC_601: return "601";
381 case CPU_SUBTYPE_POWERPC_602: return "602";
382 case CPU_SUBTYPE_POWERPC_603: return "603";
383 case CPU_SUBTYPE_POWERPC_603e: return "603e";
384 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
385 case CPU_SUBTYPE_POWERPC_604: return "604";
386 case CPU_SUBTYPE_POWERPC_604e: return "604e";
387 case CPU_SUBTYPE_POWERPC_620: return "620";
388 case CPU_SUBTYPE_POWERPC_750: return "750";
389 case CPU_SUBTYPE_POWERPC_7400: return "7400";
390 case CPU_SUBTYPE_POWERPC_7450: return "7450";
391 case CPU_SUBTYPE_POWERPC_970: return "970";
397 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
398 std::string sys::getHostCPUName() {
399 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
400 // and so we must use an operating-system interface to determine the current
401 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
402 const char *generic = "generic";
404 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
405 // memory buffer because the 'file' has 0 size (it can be read from only
409 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
411 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
415 // The cpu line is second (after the 'processor: 0' line), so if this
416 // buffer is too small then something has changed (or is wrong).
418 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
421 const char *CPUInfoStart = buffer;
422 const char *CPUInfoEnd = buffer + CPUInfoSize;
424 const char *CIP = CPUInfoStart;
426 const char *CPUStart = 0;
429 // We need to find the first line which starts with cpu, spaces, and a colon.
430 // After the colon, there may be some additional spaces and then the cpu type.
431 while (CIP < CPUInfoEnd && CPUStart == 0) {
432 if (CIP < CPUInfoEnd && *CIP == '\n')
435 if (CIP < CPUInfoEnd && *CIP == 'c') {
437 if (CIP < CPUInfoEnd && *CIP == 'p') {
439 if (CIP < CPUInfoEnd && *CIP == 'u') {
441 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
444 if (CIP < CPUInfoEnd && *CIP == ':') {
446 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
449 if (CIP < CPUInfoEnd) {
451 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
452 *CIP != ',' && *CIP != '\n'))
454 CPULen = CIP - CPUStart;
462 while (CIP < CPUInfoEnd && *CIP != '\n')
469 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
470 .Case("604e", "604e")
472 .Case("7400", "7400")
473 .Case("7410", "7400")
474 .Case("7447", "7400")
475 .Case("7455", "7450")
477 .Case("POWER4", "970")
478 .Case("PPC970FX", "970")
479 .Case("PPC970MP", "970")
481 .Case("POWER5", "g5")
483 .Case("POWER6", "pwr6")
484 .Case("POWER7", "pwr7")
487 #elif defined(__linux__) && defined(__arm__)
488 std::string sys::getHostCPUName() {
489 // The cpuid register on arm is not accessible from user space. On Linux,
490 // it is exposed through the /proc/cpuinfo file.
491 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
492 // memory buffer because the 'file' has 0 size (it can be read from only
496 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
498 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
502 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
505 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
508 StringRef Str(buffer, CPUInfoSize);
510 SmallVector<StringRef, 32> Lines;
511 Str.split(Lines, "\n");
513 // Look for the CPU implementer line.
514 StringRef Implementer;
515 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
516 if (Lines[I].startswith("CPU implementer"))
517 Implementer = Lines[I].substr(15).ltrim("\t :");
519 if (Implementer == "0x41") // ARM Ltd.
520 // Look for the CPU part line.
521 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
522 if (Lines[I].startswith("CPU part"))
523 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
524 // values correspond to the "Part number" in the CP15/c0 register. The
525 // contents are specified in the various processor manuals.
526 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
527 .Case("0x926", "arm926ej-s")
528 .Case("0xb02", "mpcore")
529 .Case("0xb36", "arm1136j-s")
530 .Case("0xb56", "arm1156t2-s")
531 .Case("0xb76", "arm1176jz-s")
532 .Case("0xc08", "cortex-a8")
533 .Case("0xc09", "cortex-a9")
534 .Case("0xc0f", "cortex-a15")
535 .Case("0xc20", "cortex-m0")
536 .Case("0xc23", "cortex-m3")
537 .Case("0xc24", "cortex-m4")
543 std::string sys::getHostCPUName() {
548 #if defined(__linux__) && defined(__arm__)
549 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
551 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
553 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
557 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
560 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
563 StringRef Str(buffer, CPUInfoSize);
565 SmallVector<StringRef, 32> Lines;
566 Str.split(Lines, "\n");
568 // Look for the CPU implementer line.
569 StringRef Implementer;
570 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
571 if (Lines[I].startswith("CPU implementer"))
572 Implementer = Lines[I].substr(15).ltrim("\t :");
574 if (Implementer == "0x41") { // ARM Ltd.
575 SmallVector<StringRef, 32> CPUFeatures;
577 // Look for the CPU features.
578 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
579 if (Lines[I].startswith("Features")) {
580 Lines[I].split(CPUFeatures, " ");
584 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
585 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
586 .Case("half", "fp16")
587 .Case("neon", "neon")
588 .Case("vfpv3", "vfp3")
589 .Case("vfpv3d16", "d16")
590 .Case("vfpv4", "vfp4")
591 .Case("idiva", "hwdiv-arm")
592 .Case("idivt", "hwdiv")
595 if (LLVMFeatureStr != "")
596 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
605 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
610 std::string sys::getProcessTriple() {
611 Triple PT(LLVM_HOSTTRIPLE);
613 if (sizeof(void *) == 8 && PT.isArch32Bit())
614 PT = PT.get64BitArchVariant();
615 if (sizeof(void *) == 4 && PT.isArch64Bit())
616 PT = PT.get32BitArchVariant();