1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This header file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 //===----------------------------------------------------------------------===//
44 // Implementations of the CPU detection routines
46 //===----------------------------------------------------------------------===//
50 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
51 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
53 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
54 /// specified arguments. If we can't run cpuid on the host, return true.
55 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
56 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
57 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
59 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
60 asm ("movq\t%%rbx, %%rsi\n\t"
62 "xchgq\t%%rbx, %%rsi\n\t"
69 #elif defined(_MSC_VER)
71 __cpuid(registers, value);
80 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
82 asm ("movl\t%%ebx, %%esi\n\t"
84 "xchgl\t%%ebx, %%esi\n\t"
91 #elif defined(_MSC_VER)
96 mov dword ptr [esi],eax
98 mov dword ptr [esi],ebx
100 mov dword ptr [esi],ecx
102 mov dword ptr [esi],edx
105 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
106 // postprocessed code that looks like "return true; return false;")
115 static bool OSHasAVXSupport() {
\r
116 #if defined( __GNUC__ )
\r
117 // Check xgetbv; this uses a .byte sequence instead of the instruction
\r
118 // directly because older assemblers do not include support for xgetbv and
\r
119 // there is no easy way to conditionally compile based on the assembler used.
\r
121 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
\r
122 #elif defined(_MSC_VER)
\r
123 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
\r
125 int rEAX = 0; // Ensures we return false
\r
127 return (rEAX & 6) == 6;
\r
130 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
132 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
133 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
134 if (Family == 6 || Family == 0xf) {
136 // Examine extended family ID if family ID is F.
137 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
138 // Examine extended model ID if family ID is 6 or F.
139 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
143 std::string sys::getHostCPUName() {
144 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
145 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
149 DetectX86FamilyModel(EAX, Family, Model);
151 bool HasSSE3 = (ECX & 0x1);
152 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
153 // indicates that the AVX registers will be saved and restored on context
154 // switch, then we have full AVX support.
155 bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
156 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
157 bool Em64T = (EDX >> 29) & 0x1;
164 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
165 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
171 case 0: // Intel486 DX processors
172 case 1: // Intel486 DX processors
173 case 2: // Intel486 SX processors
174 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
175 // IntelDX2 processors
176 case 4: // Intel486 SL processor
177 case 5: // IntelSX2 processors
178 case 7: // Write-Back Enhanced IntelDX2 processors
179 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
180 default: return "i486";
184 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
185 // Pentium processors (60, 66)
186 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
187 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
189 case 3: // Pentium OverDrive processors for Intel486 processor-based
193 case 4: // Pentium OverDrive processor with MMX technology for Pentium
194 // processor (75, 90, 100, 120, 133), Pentium processor with
195 // MMX technology (166, 200)
196 return "pentium-mmx";
198 default: return "pentium";
202 case 1: // Pentium Pro processor
205 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
207 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
208 // model 05, and Intel Celeron processor, model 05
209 case 6: // Celeron processor, model 06
212 case 7: // Pentium III processor, model 07, and Pentium III Xeon
213 // processor, model 07
214 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
215 // model 08, and Celeron processor, model 08
216 case 10: // Pentium III Xeon processor, model 0Ah
217 case 11: // Pentium III processor, model 0Bh
220 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
221 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
222 // 0Dh. All processors are manufactured using the 90 nm process.
225 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
226 // 0Eh. All processors are manufactured using the 65 nm process.
229 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
230 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
231 // mobile processor, Intel Core 2 Extreme processor, Intel
232 // Pentium Dual-Core processor, Intel Xeon processor, model
233 // 0Fh. All processors are manufactured using the 65 nm process.
234 case 22: // Intel Celeron processor model 16h. All processors are
235 // manufactured using the 65 nm process
238 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
239 // Integrated Processor with Intel QuickAssist Technology
240 return "i686"; // FIXME: ???
242 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
243 // 17h. All processors are manufactured using the 45 nm process.
245 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
248 case 26: // Intel Core i7 processor and Intel Xeon processor. All
249 // processors are manufactured using the 45 nm process.
250 case 29: // Intel Xeon processor MP. All processors are manufactured using
251 // the 45 nm process.
252 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
253 // As found in a Summer 2010 model iMac.
254 case 37: // Intel Core i7, laptop version.
255 case 44: // Intel Core i7 processor and Intel Xeon processor. All
256 // processors are manufactured using the 32 nm process.
257 case 46: // Nehalem EX
258 case 47: // Westmere EX
262 case 42: // Intel Core i7 processor. All processors are manufactured
263 // using the 32 nm process.
265 // Not all Sandy Bridge processors support AVX (such as the Pentium
266 // versions instead of the i7 versions).
267 return HasAVX ? "corei7-avx" : "corei7";
271 // Not all Ivy Bridge processors support AVX (such as the Pentium
272 // versions instead of the i7 versions).
273 return HasAVX ? "core-avx-i" : "corei7";
275 case 28: // Most 45 nm Intel Atom processors
276 case 38: // 45 nm Atom Lincroft
277 case 39: // 32 nm Atom Medfield
278 case 53: // 32 nm Atom Midview
279 case 54: // 32 nm Atom Midview
282 default: return (Em64T) ? "x86-64" : "i686";
286 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
287 // model 00h and manufactured using the 0.18 micron process.
288 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
289 // processor MP, and Intel Celeron processor. All processors are
290 // model 01h and manufactured using the 0.18 micron process.
291 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
292 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
293 // processor, and Mobile Intel Celeron processor. All processors
294 // are model 02h and manufactured using the 0.13 micron process.
295 return (Em64T) ? "x86-64" : "pentium4";
297 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
298 // processor. All processors are model 03h and manufactured using
299 // the 90 nm process.
300 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
301 // Pentium D processor, Intel Xeon processor, Intel Xeon
302 // processor MP, Intel Celeron D processor. All processors are
303 // model 04h and manufactured using the 90 nm process.
304 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
305 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
306 // MP, Intel Celeron D processor. All processors are model 06h
307 // and manufactured using the 65 nm process.
308 return (Em64T) ? "nocona" : "prescott";
311 return (Em64T) ? "x86-64" : "pentium4";
318 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
319 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
320 // appears to be no way to generate the wide variety of AMD-specific targets
321 // from the information returned from CPUID.
329 case 8: return "k6-2";
331 case 13: return "k6-3";
332 case 10: return "geode";
333 default: return "pentium";
337 case 4: return "athlon-tbird";
340 case 8: return "athlon-mp";
341 case 10: return "athlon-xp";
342 default: return "athlon";
348 case 1: return "opteron";
349 case 5: return "athlon-fx"; // also opteron
350 default: return "athlon64";
359 else if (Model <= 31)
367 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
368 std::string sys::getHostCPUName() {
369 host_basic_info_data_t hostInfo;
370 mach_msg_type_number_t infoCount;
372 infoCount = HOST_BASIC_INFO_COUNT;
373 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
376 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
378 switch(hostInfo.cpu_subtype) {
379 case CPU_SUBTYPE_POWERPC_601: return "601";
380 case CPU_SUBTYPE_POWERPC_602: return "602";
381 case CPU_SUBTYPE_POWERPC_603: return "603";
382 case CPU_SUBTYPE_POWERPC_603e: return "603e";
383 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
384 case CPU_SUBTYPE_POWERPC_604: return "604";
385 case CPU_SUBTYPE_POWERPC_604e: return "604e";
386 case CPU_SUBTYPE_POWERPC_620: return "620";
387 case CPU_SUBTYPE_POWERPC_750: return "750";
388 case CPU_SUBTYPE_POWERPC_7400: return "7400";
389 case CPU_SUBTYPE_POWERPC_7450: return "7450";
390 case CPU_SUBTYPE_POWERPC_970: return "970";
396 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
397 std::string sys::getHostCPUName() {
398 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
399 // and so we must use an operating-system interface to determine the current
400 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
401 const char *generic = "generic";
403 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
404 // memory buffer because the 'file' has 0 size (it can be read from only
408 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
410 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
414 // The cpu line is second (after the 'processor: 0' line), so if this
415 // buffer is too small then something has changed (or is wrong).
417 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
420 const char *CPUInfoStart = buffer;
421 const char *CPUInfoEnd = buffer + CPUInfoSize;
423 const char *CIP = CPUInfoStart;
425 const char *CPUStart = 0;
428 // We need to find the first line which starts with cpu, spaces, and a colon.
429 // After the colon, there may be some additional spaces and then the cpu type.
430 while (CIP < CPUInfoEnd && CPUStart == 0) {
431 if (CIP < CPUInfoEnd && *CIP == '\n')
434 if (CIP < CPUInfoEnd && *CIP == 'c') {
436 if (CIP < CPUInfoEnd && *CIP == 'p') {
438 if (CIP < CPUInfoEnd && *CIP == 'u') {
440 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
443 if (CIP < CPUInfoEnd && *CIP == ':') {
445 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
448 if (CIP < CPUInfoEnd) {
450 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
451 *CIP != ',' && *CIP != '\n'))
453 CPULen = CIP - CPUStart;
461 while (CIP < CPUInfoEnd && *CIP != '\n')
468 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
469 .Case("604e", "604e")
471 .Case("7400", "7400")
472 .Case("7410", "7400")
473 .Case("7447", "7400")
474 .Case("7455", "7450")
476 .Case("POWER4", "970")
477 .Case("PPC970FX", "970")
478 .Case("PPC970MP", "970")
480 .Case("POWER5", "g5")
482 .Case("POWER6", "pwr6")
483 .Case("POWER7", "pwr7")
486 #elif defined(__linux__) && defined(__arm__)
487 std::string sys::getHostCPUName() {
488 // The cpuid register on arm is not accessible from user space. On Linux,
489 // it is exposed through the /proc/cpuinfo file.
490 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
491 // memory buffer because the 'file' has 0 size (it can be read from only
495 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
497 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
501 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
504 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
507 StringRef Str(buffer, CPUInfoSize);
509 SmallVector<StringRef, 32> Lines;
510 Str.split(Lines, "\n");
512 // Look for the CPU implementer line.
513 StringRef Implementer;
514 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
515 if (Lines[I].startswith("CPU implementer"))
516 Implementer = Lines[I].substr(15).ltrim("\t :");
518 if (Implementer == "0x41") // ARM Ltd.
519 // Look for the CPU part line.
520 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
521 if (Lines[I].startswith("CPU part"))
522 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
523 // values correspond to the "Part number" in the CP15/c0 register. The
524 // contents are specified in the various processor manuals.
525 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
526 .Case("0x926", "arm926ej-s")
527 .Case("0xb02", "mpcore")
528 .Case("0xb36", "arm1136j-s")
529 .Case("0xb56", "arm1156t2-s")
530 .Case("0xb76", "arm1176jz-s")
531 .Case("0xc08", "cortex-a8")
532 .Case("0xc09", "cortex-a9")
533 .Case("0xc0f", "cortex-a15")
534 .Case("0xc20", "cortex-m0")
535 .Case("0xc23", "cortex-m3")
536 .Case("0xc24", "cortex-m4")
542 std::string sys::getHostCPUName() {
547 #if defined(__linux__) && defined(__arm__)
548 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
550 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
552 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
556 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
559 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
562 StringRef Str(buffer, CPUInfoSize);
564 SmallVector<StringRef, 32> Lines;
565 Str.split(Lines, "\n");
567 // Look for the CPU implementer line.
568 StringRef Implementer;
569 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
570 if (Lines[I].startswith("CPU implementer"))
571 Implementer = Lines[I].substr(15).ltrim("\t :");
573 if (Implementer == "0x41") { // ARM Ltd.
574 SmallVector<StringRef, 32> CPUFeatures;
576 // Look for the CPU features.
577 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
578 if (Lines[I].startswith("Features")) {
579 Lines[I].split(CPUFeatures, " ");
583 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
584 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
585 .Case("half", "fp16")
586 .Case("neon", "neon")
587 .Case("vfpv3", "vfp3")
588 .Case("vfpv3d16", "d16")
589 .Case("vfpv4", "vfp4")
590 .Case("idiva", "hwdiv-arm")
591 .Case("idivt", "hwdiv")
594 if (LLVMFeatureStr != "")
595 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
604 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
609 std::string sys::getProcessTriple() {
610 Triple PT(LLVM_HOSTTRIPLE);
612 if (sizeof(void *) == 8 && PT.isArch32Bit())
613 PT = PT.get64BitArchVariant();
614 if (sizeof(void *) == 4 && PT.isArch64Bit())
615 PT = PT.get32BitArchVariant();