1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(__linux__)
53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
55 // memory buffer because the 'file' has 0 size (it can be read from only
59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD);
61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n");
64 int Ret = read(FD, Buf, Size);
65 int CloseStatus = close(FD);
72 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
73 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
75 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
76 /// specified arguments. If we can't run cpuid on the host, return true.
77 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
78 unsigned *rECX, unsigned *rEDX) {
79 #if defined(__GNUC__) || defined(__clang__)
80 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
81 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
82 asm ("movq\t%%rbx, %%rsi\n\t"
84 "xchgq\t%%rbx, %%rsi\n\t"
91 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
92 asm ("movl\t%%ebx, %%esi\n\t"
94 "xchgl\t%%ebx, %%esi\n\t"
101 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
102 // postprocessed code that looks like "return true; return false;")
106 #elif defined(_MSC_VER)
107 // The MSVC intrinsic is portable across x86 and x64.
109 __cpuid(registers, value);
110 *rEAX = registers[0];
111 *rEBX = registers[1];
112 *rECX = registers[2];
113 *rEDX = registers[3];
120 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
121 /// 4 values in the specified arguments. If we can't run cpuid on the host,
123 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
124 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
126 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
127 #if defined(__GNUC__)
128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
129 asm ("movq\t%%rbx, %%rsi\n\t"
131 "xchgq\t%%rbx, %%rsi\n\t"
139 #elif defined(_MSC_VER)
141 __cpuidex(registers, value, subleaf);
142 *rEAX = registers[0];
143 *rEBX = registers[1];
144 *rECX = registers[2];
145 *rEDX = registers[3];
150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
151 #if defined(__GNUC__)
152 asm ("movl\t%%ebx, %%esi\n\t"
154 "xchgl\t%%ebx, %%esi\n\t"
162 #elif defined(_MSC_VER)
168 mov dword ptr [esi],eax
170 mov dword ptr [esi],ebx
172 mov dword ptr [esi],ecx
174 mov dword ptr [esi],edx
185 static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
186 #if defined(__GNUC__)
187 // Check xgetbv; this uses a .byte sequence instead of the instruction
188 // directly because older assemblers do not include support for xgetbv and
189 // there is no easy way to conditionally compile based on the assembler used.
190 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0));
192 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
193 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
195 *rEDX = Result >> 32;
202 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
204 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
205 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
206 if (Family == 6 || Family == 0xf) {
208 // Examine extended family ID if family ID is F.
209 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
210 // Examine extended model ID if family ID is 6 or F.
211 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
215 StringRef sys::getHostCPUName() {
216 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
217 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
221 DetectX86FamilyModel(EAX, Family, Model);
228 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
230 unsigned MaxLeaf = EAX;
231 bool HasSSE3 = (ECX & 0x1);
232 bool HasSSE41 = (ECX & 0x80000);
233 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
234 // indicates that the AVX registers will be saved and restored on context
235 // switch, then we have full AVX support.
236 const unsigned AVXBits = (1 << 27) | (1 << 28);
237 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
238 ((EAX & 0x6) == 0x6);
239 bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 &&
240 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) &&
242 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
243 bool Em64T = (EDX >> 29) & 0x1;
244 bool HasTBM = (ECX >> 21) & 0x1;
246 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
252 case 0: // Intel486 DX processors
253 case 1: // Intel486 DX processors
254 case 2: // Intel486 SX processors
255 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
256 // IntelDX2 processors
257 case 4: // Intel486 SL processor
258 case 5: // IntelSX2 processors
259 case 7: // Write-Back Enhanced IntelDX2 processors
260 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
261 default: return "i486";
265 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
266 // Pentium processors (60, 66)
267 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
268 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
270 case 3: // Pentium OverDrive processors for Intel486 processor-based
274 case 4: // Pentium OverDrive processor with MMX technology for Pentium
275 // processor (75, 90, 100, 120, 133), Pentium processor with
276 // MMX technology (166, 200)
277 return "pentium-mmx";
279 default: return "pentium";
283 case 1: // Pentium Pro processor
286 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
288 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
289 // model 05, and Intel Celeron processor, model 05
290 case 6: // Celeron processor, model 06
293 case 7: // Pentium III processor, model 07, and Pentium III Xeon
294 // processor, model 07
295 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
296 // model 08, and Celeron processor, model 08
297 case 10: // Pentium III Xeon processor, model 0Ah
298 case 11: // Pentium III processor, model 0Bh
301 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
302 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
303 // 0Dh. All processors are manufactured using the 90 nm process.
306 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
307 // 0Eh. All processors are manufactured using the 65 nm process.
310 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
311 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
312 // mobile processor, Intel Core 2 Extreme processor, Intel
313 // Pentium Dual-Core processor, Intel Xeon processor, model
314 // 0Fh. All processors are manufactured using the 65 nm process.
315 case 22: // Intel Celeron processor model 16h. All processors are
316 // manufactured using the 65 nm process
319 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
320 // Integrated Processor with Intel QuickAssist Technology
321 return "i686"; // FIXME: ???
323 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
324 // 17h. All processors are manufactured using the 45 nm process.
326 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
327 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
328 return HasSSE41 ? "penryn" : "core2";
330 case 26: // Intel Core i7 processor and Intel Xeon processor. All
331 // processors are manufactured using the 45 nm process.
332 case 29: // Intel Xeon processor MP. All processors are manufactured using
333 // the 45 nm process.
334 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
335 // As found in a Summer 2010 model iMac.
336 case 37: // Intel Core i7, laptop version.
337 case 44: // Intel Core i7 processor and Intel Xeon processor. All
338 // processors are manufactured using the 32 nm process.
339 case 46: // Nehalem EX
340 case 47: // Westmere EX
344 case 42: // Intel Core i7 processor. All processors are manufactured
345 // using the 32 nm process.
347 // Not all Sandy Bridge processors support AVX (such as the Pentium
348 // versions instead of the i7 versions).
349 return HasAVX ? "corei7-avx" : "corei7";
353 case 62: // Ivy Bridge EP
354 // Not all Ivy Bridge processors support AVX (such as the Pentium
355 // versions instead of the i7 versions).
356 return HasAVX ? "core-avx-i" : "corei7";
363 // Not all Haswell processors support AVX2 (such as the Pentium
364 // versions instead of the i7 versions).
365 return HasAVX2 ? "core-avx2" : "corei7";
369 // Not all Broadwell processors support AVX2 (such as the Pentium
370 // versions instead of the i7 versions).
371 return HasAVX2 ? "broadwell" : "corei7";
373 case 28: // Most 45 nm Intel Atom processors
374 case 38: // 45 nm Atom Lincroft
375 case 39: // 32 nm Atom Medfield
376 case 53: // 32 nm Atom Midview
377 case 54: // 32 nm Atom Midview
380 // Atom Silvermont codes from the Intel software optimization guide.
386 default: return (Em64T) ? "x86-64" : "i686";
390 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
391 // model 00h and manufactured using the 0.18 micron process.
392 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
393 // processor MP, and Intel Celeron processor. All processors are
394 // model 01h and manufactured using the 0.18 micron process.
395 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
396 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
397 // processor, and Mobile Intel Celeron processor. All processors
398 // are model 02h and manufactured using the 0.13 micron process.
399 return (Em64T) ? "x86-64" : "pentium4";
401 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
402 // processor. All processors are model 03h and manufactured using
403 // the 90 nm process.
404 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
405 // Pentium D processor, Intel Xeon processor, Intel Xeon
406 // processor MP, Intel Celeron D processor. All processors are
407 // model 04h and manufactured using the 90 nm process.
408 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
409 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
410 // MP, Intel Celeron D processor. All processors are model 06h
411 // and manufactured using the 65 nm process.
412 return (Em64T) ? "nocona" : "prescott";
415 return (Em64T) ? "x86-64" : "pentium4";
422 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
423 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
424 // appears to be no way to generate the wide variety of AMD-specific targets
425 // from the information returned from CPUID.
433 case 8: return "k6-2";
435 case 13: return "k6-3";
436 case 10: return "geode";
437 default: return "pentium";
441 case 4: return "athlon-tbird";
444 case 8: return "athlon-mp";
445 case 10: return "athlon-xp";
446 default: return "athlon";
452 case 1: return "opteron";
453 case 5: return "athlon-fx"; // also opteron
454 default: return "athlon64";
461 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
464 return "bdver4"; // 50h-6Fh: Excavator
466 return "bdver3"; // 30h-3Fh: Steamroller
467 if (Model >= 0x10 || HasTBM)
468 return "bdver2"; // 10h-1Fh: Piledriver
469 return "bdver1"; // 00h-0Fh: Bulldozer
471 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
480 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
481 StringRef sys::getHostCPUName() {
482 host_basic_info_data_t hostInfo;
483 mach_msg_type_number_t infoCount;
485 infoCount = HOST_BASIC_INFO_COUNT;
486 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
489 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
491 switch(hostInfo.cpu_subtype) {
492 case CPU_SUBTYPE_POWERPC_601: return "601";
493 case CPU_SUBTYPE_POWERPC_602: return "602";
494 case CPU_SUBTYPE_POWERPC_603: return "603";
495 case CPU_SUBTYPE_POWERPC_603e: return "603e";
496 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
497 case CPU_SUBTYPE_POWERPC_604: return "604";
498 case CPU_SUBTYPE_POWERPC_604e: return "604e";
499 case CPU_SUBTYPE_POWERPC_620: return "620";
500 case CPU_SUBTYPE_POWERPC_750: return "750";
501 case CPU_SUBTYPE_POWERPC_7400: return "7400";
502 case CPU_SUBTYPE_POWERPC_7450: return "7450";
503 case CPU_SUBTYPE_POWERPC_970: return "970";
509 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
510 StringRef sys::getHostCPUName() {
511 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
512 // and so we must use an operating-system interface to determine the current
513 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
514 const char *generic = "generic";
516 // The cpu line is second (after the 'processor: 0' line), so if this
517 // buffer is too small then something has changed (or is wrong).
519 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
520 if (CPUInfoSize == -1)
523 const char *CPUInfoStart = buffer;
524 const char *CPUInfoEnd = buffer + CPUInfoSize;
526 const char *CIP = CPUInfoStart;
528 const char *CPUStart = 0;
531 // We need to find the first line which starts with cpu, spaces, and a colon.
532 // After the colon, there may be some additional spaces and then the cpu type.
533 while (CIP < CPUInfoEnd && CPUStart == 0) {
534 if (CIP < CPUInfoEnd && *CIP == '\n')
537 if (CIP < CPUInfoEnd && *CIP == 'c') {
539 if (CIP < CPUInfoEnd && *CIP == 'p') {
541 if (CIP < CPUInfoEnd && *CIP == 'u') {
543 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
546 if (CIP < CPUInfoEnd && *CIP == ':') {
548 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
551 if (CIP < CPUInfoEnd) {
553 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
554 *CIP != ',' && *CIP != '\n'))
556 CPULen = CIP - CPUStart;
564 while (CIP < CPUInfoEnd && *CIP != '\n')
571 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
572 .Case("604e", "604e")
574 .Case("7400", "7400")
575 .Case("7410", "7400")
576 .Case("7447", "7400")
577 .Case("7455", "7450")
579 .Case("POWER4", "970")
580 .Case("PPC970FX", "970")
581 .Case("PPC970MP", "970")
583 .Case("POWER5", "g5")
585 .Case("POWER6", "pwr6")
586 .Case("POWER7", "pwr7")
587 .Case("POWER8", "pwr8")
588 .Case("POWER8E", "pwr8")
591 #elif defined(__linux__) && defined(__arm__)
592 StringRef sys::getHostCPUName() {
593 // The cpuid register on arm is not accessible from user space. On Linux,
594 // it is exposed through the /proc/cpuinfo file.
596 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
599 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
600 if (CPUInfoSize == -1)
603 StringRef Str(buffer, CPUInfoSize);
605 SmallVector<StringRef, 32> Lines;
606 Str.split(Lines, "\n");
608 // Look for the CPU implementer line.
609 StringRef Implementer;
610 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
611 if (Lines[I].startswith("CPU implementer"))
612 Implementer = Lines[I].substr(15).ltrim("\t :");
614 if (Implementer == "0x41") // ARM Ltd.
615 // Look for the CPU part line.
616 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
617 if (Lines[I].startswith("CPU part"))
618 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
619 // values correspond to the "Part number" in the CP15/c0 register. The
620 // contents are specified in the various processor manuals.
621 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
622 .Case("0x926", "arm926ej-s")
623 .Case("0xb02", "mpcore")
624 .Case("0xb36", "arm1136j-s")
625 .Case("0xb56", "arm1156t2-s")
626 .Case("0xb76", "arm1176jz-s")
627 .Case("0xc08", "cortex-a8")
628 .Case("0xc09", "cortex-a9")
629 .Case("0xc0f", "cortex-a15")
630 .Case("0xc20", "cortex-m0")
631 .Case("0xc23", "cortex-m3")
632 .Case("0xc24", "cortex-m4")
635 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
636 // Look for the CPU part line.
637 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
638 if (Lines[I].startswith("CPU part"))
639 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
640 // values correspond to the "Part number" in the CP15/c0 register. The
641 // contents are specified in the various processor manuals.
642 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
643 .Case("0x06f", "krait") // APQ8064
648 #elif defined(__linux__) && defined(__s390x__)
649 StringRef sys::getHostCPUName() {
650 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
652 // The "processor 0:" line comes after a fair amount of other information,
653 // including a cache breakdown, but this should be plenty.
655 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
656 if (CPUInfoSize == -1)
659 StringRef Str(buffer, CPUInfoSize);
660 SmallVector<StringRef, 32> Lines;
661 Str.split(Lines, "\n");
662 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
663 if (Lines[I].startswith("processor ")) {
664 size_t Pos = Lines[I].find("machine = ");
665 if (Pos != StringRef::npos) {
666 Pos += sizeof("machine = ") - 1;
668 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
682 StringRef sys::getHostCPUName() {
687 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
688 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
689 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
690 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
697 if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
701 GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
703 Features["cmov"] = (EDX >> 15) & 1;
704 Features["mmx"] = (EDX >> 23) & 1;
705 Features["sse"] = (EDX >> 25) & 1;
706 Features["sse2"] = (EDX >> 26) & 1;
707 Features["sse3"] = (ECX >> 0) & 1;
708 Features["ssse3"] = (ECX >> 9) & 1;
709 Features["sse4.1"] = (ECX >> 19) & 1;
710 Features["sse4.2"] = (ECX >> 20) & 1;
712 Features["pclmul"] = (ECX >> 1) & 1;
713 Features["fma"] = (ECX >> 12) & 1;
714 Features["cx16"] = (ECX >> 13) & 1;
715 Features["movbe"] = (ECX >> 22) & 1;
716 Features["popcnt"] = (ECX >> 23) & 1;
717 Features["aes"] = (ECX >> 25) & 1;
718 Features["f16c"] = (ECX >> 29) & 1;
719 Features["rdrnd"] = (ECX >> 30) & 1;
721 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
722 // indicates that the AVX registers will be saved and restored on context
723 // switch, then we have full AVX support.
724 bool HasAVX = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
725 !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
726 Features["avx"] = HasAVX;
728 // AVX512 requires additional context to be saved by the OS.
729 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
731 unsigned MaxExtLevel;
732 GetX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
734 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
735 !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
736 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
737 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
738 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
739 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1);
740 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1);
741 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
743 bool HasLeaf7 = MaxLevel >= 7 &&
744 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
746 // AVX2 is only supported if we have the OS save support from AVX.
747 Features["avx2"] = HasAVX && HasLeaf7 && (EBX >> 5) & 1;
749 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
750 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
751 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
752 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
753 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
754 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
755 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
756 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
758 // AVX512 is only supported if the OS supports the context save for it.
759 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
760 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
761 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
762 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
763 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
764 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
765 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
769 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
770 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
771 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
774 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
775 if (CPUInfoSize == -1)
778 StringRef Str(buffer, CPUInfoSize);
780 SmallVector<StringRef, 32> Lines;
781 Str.split(Lines, "\n");
783 SmallVector<StringRef, 32> CPUFeatures;
785 // Look for the CPU features.
786 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
787 if (Lines[I].startswith("Features")) {
788 Lines[I].split(CPUFeatures, " ");
792 #if defined(__aarch64__)
793 // Keep track of which crypto features we have seen
803 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
804 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
805 #if defined(__aarch64__)
806 .Case("asimd", "neon")
807 .Case("fp", "fp-armv8")
808 .Case("crc32", "crc")
810 .Case("half", "fp16")
811 .Case("neon", "neon")
812 .Case("vfpv3", "vfp3")
813 .Case("vfpv3d16", "d16")
814 .Case("vfpv4", "vfp4")
815 .Case("idiva", "hwdiv-arm")
816 .Case("idivt", "hwdiv")
820 #if defined(__aarch64__)
821 // We need to check crypto separately since we need all of the crypto
822 // extensions to enable the subtarget feature
823 if (CPUFeatures[I] == "aes")
825 else if (CPUFeatures[I] == "pmull")
827 else if (CPUFeatures[I] == "sha1")
829 else if (CPUFeatures[I] == "sha2")
833 if (LLVMFeatureStr != "")
834 Features[LLVMFeatureStr] = true;
837 #if defined(__aarch64__)
838 // If we have all crypto bits we can add the feature
839 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
840 Features["crypto"] = true;
846 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
851 std::string sys::getProcessTriple() {
852 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
854 if (sizeof(void *) == 8 && PT.isArch32Bit())
855 PT = PT.get64BitArchVariant();
856 if (sizeof(void *) == 4 && PT.isArch64Bit())
857 PT = PT.get32BitArchVariant();