1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 /// Cyclone has register move instructions which are "free".
36 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
37 "Has zero-cycle register moves">;
39 /// Cyclone has instructions which zero registers for "free".
40 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
41 "Has zero-cycle zeroing instructions">;
43 //===----------------------------------------------------------------------===//
44 // Register File Description
45 //===----------------------------------------------------------------------===//
47 include "AArch64RegisterInfo.td"
48 include "AArch64CallingConvention.td"
50 //===----------------------------------------------------------------------===//
51 // Instruction Descriptions
52 //===----------------------------------------------------------------------===//
54 include "AArch64Schedule.td"
55 include "AArch64InstrInfo.td"
57 def AArch64InstrInfo : InstrInfo;
59 //===----------------------------------------------------------------------===//
60 // AArch64 Processors supported.
62 include "AArch64SchedA53.td"
63 include "AArch64SchedCyclone.td"
65 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
66 "Cortex-A53 ARM processors",
72 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
73 "Cortex-A57 ARM processors",
79 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
85 FeatureZCRegMove, FeatureZCZeroing]>;
87 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
91 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
92 def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
93 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
99 def GenericAsmParserVariant : AsmParserVariant {
101 string Name = "generic";
104 def AppleAsmParserVariant : AsmParserVariant {
106 string Name = "apple-neon";
109 //===----------------------------------------------------------------------===//
111 //===----------------------------------------------------------------------===//
112 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
113 // AsmWriter bits get associated with the correct class.
114 def GenericAsmWriter : AsmWriter {
115 string AsmWriterClassName = "InstPrinter";
117 bit isMCAsmWriter = 1;
120 def AppleAsmWriter : AsmWriter {
121 let AsmWriterClassName = "AppleInstPrinter";
123 int isMCAsmWriter = 1;
126 //===----------------------------------------------------------------------===//
127 // Target Declaration
128 //===----------------------------------------------------------------------===//
130 def AArch64 : Target {
131 let InstructionSet = AArch64InstrInfo;
132 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
133 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];