lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions">;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 /// Cyclone has register move instructions which are "free".
  36 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  37                                         "Has zero-cycle register moves">;
  38
  39 /// Cyclone has instructions which zero registers for "free".
  40 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  41                                         "Has zero-cycle zeroing instructions">;
  42
  43 //===----------------------------------------------------------------------===//
  44 // Register File Description
  45 //===----------------------------------------------------------------------===//
  46
  47 include "AArch64RegisterInfo.td"
  48 include "AArch64CallingConvention.td"
  49
  50 //===----------------------------------------------------------------------===//
  51 // Instruction Descriptions
  52 //===----------------------------------------------------------------------===//
  53
  54 include "AArch64Schedule.td"
  55 include "AArch64InstrInfo.td"
  56
  57 def AArch64InstrInfo : InstrInfo;
  58
  59 //===----------------------------------------------------------------------===//
  60 // AArch64 Processors supported.
  61 //
  62 include "AArch64SchedA53.td"
  63 include "AArch64SchedCyclone.td"
  64
  65 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
  66                                    "Cortex-A53 ARM processors",
  67                                    [FeatureFPARMv8,
  68                                    FeatureNEON,
  69                                    FeatureCrypto,
  70                                    FeatureCRC]>;
  71
  72 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
  73                                    "Cortex-A57 ARM processors",
  74                                    [FeatureFPARMv8,
  75                                    FeatureNEON,
  76                                    FeatureCrypto,
  77                                    FeatureCRC]>;
  78
  79 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
  80                                    "Cyclone",
  81                                    [FeatureFPARMv8,
  82                                    FeatureNEON,
  83                                    FeatureCrypto,
  84                                    FeatureCRC,
  85                                    FeatureZCRegMove, FeatureZCZeroing]>;
  86
  87 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
  88                                               FeatureNEON,
  89                                               FeatureCRC]>;
  90
  91 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
  92 def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
  93 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
  94
  95 //===----------------------------------------------------------------------===//
  96 // Assembly parser
  97 //===----------------------------------------------------------------------===//
  98
  99 def GenericAsmParserVariant : AsmParserVariant {
 100   int Variant = 0;
 101   string Name = "generic";
 102 }
 103
 104 def AppleAsmParserVariant : AsmParserVariant {
 105   int Variant = 1;
 106   string Name = "apple-neon";
 107 }
 108
 109 //===----------------------------------------------------------------------===//
 110 // Assembly printer
 111 //===----------------------------------------------------------------------===//
 112 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 113 // AsmWriter bits get associated with the correct class.
 114 def GenericAsmWriter : AsmWriter {
 115   string AsmWriterClassName  = "InstPrinter";
 116   int Variant = 0;
 117   bit isMCAsmWriter = 1;
 118 }
 119
 120 def AppleAsmWriter : AsmWriter {
 121   let AsmWriterClassName = "AppleInstPrinter";
 122   int Variant = 1;
 123   int isMCAsmWriter = 1;
 124 }
 125
 126 //===----------------------------------------------------------------------===//
 127 // Target Declaration
 128 //===----------------------------------------------------------------------===//
 129
 130 def AArch64 : Target {
 131   let InstructionSet = AArch64InstrInfo;
 132   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 133   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 134 }